KR101204662B1 - Method for fabricating transistor in semiconductor device - Google Patents

Abstract

A transistor forming method of a semiconductor device may include forming a gate pattern on a semiconductor substrate on which a cell region and a peripheral circuit region are formed; Sequentially forming a buffer oxide film, a nitride film for a spacer, and a silicon film over the gate pattern and the semiconductor substrate; Oxidizing a silicon film into an oxide film for a spacer; Forming a photoresist pattern that blocks the gate pattern of the cell region, and then etching back the gate pattern of the peripheral circuit region to form a first spacer layer, and removing the photoresist pattern; Forming a photoresist pattern that blocks the gate pattern of the peripheral circuit area, and then removing the spacer oxide film of the cell area; Cleaning the semiconductor substrate to remove the silicon film remaining between the gate patterns; And etching the gate pattern of the cell region to form a second spacer layer.

Silicon film, oxide film for spacer, threshold voltage

Description

Method for fabricating transistor in semiconductor device

1 is a view showing a transistor of a semiconductor device according to the prior art.

2 to 8 are views illustrating a method of forming a transistor of a semiconductor device according to the present invention.

<Explanation of symbols for the main parts of the drawings>

200 semiconductor substrate 211 gate pattern

212: buffer oxide film 214: nitride film for spacer

216 silicon film 218 spacer oxide film

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a transistor of a semiconductor device.

In general, when a strong electric field is formed at the edge of the drain region, a hot carrier increases to deteriorate the characteristics of the transistor, thereby forming a gate spacer made of an insulating material on the sidewall of the gate stack, thereby preventing the transistor. At this time, the threshold voltage of the cell region and the peripheral circuit region transistor is affected by the thickness of the gate spacer. Accordingly, a threshold voltage spacer insulating layer having an appropriate thickness is formed on the sidewall of the gate pattern to adjust the threshold voltage.

1 is a view showing a transistor of a semiconductor device according to the prior art.

Referring to FIG. 1, a gate pattern 108 is formed on a semiconductor substrate 100 on which a cell region A and a peripheral circuit region B are defined. The gate pattern 110 has a structure in which a gate insulating film 102, a conductive film pattern 104, a metal film pattern 106, and a hard mask film 108 are stacked.

First gate spacers 116 including the first buffer oxide layer 112 and the first spacer nitride layer 114 are formed on both sides of the gate pattern 110 of the cell region A, and the peripheral circuit region B is formed. Second gate spacers 124 including the second buffer oxide layer 118, the second spacer nitride layer 120, and the spacer oxide layer 122 are formed on both sides of the gate pattern 110. The deposition thickness of the first and second gate spacers 116 and 124 affects the threshold voltage of the cell region A and the threshold voltage of the N-MOS / P-MOS of the peripheral circuit region B. Therefore, the thickness of the gate spacer 116 should be uniformly deposited on the entire surface of the wafer to maintain the threshold voltage appropriately. The thickness uniformity of the gate spacer 116 is generally controlled by controlling the material to be formed or by controlling the deposition method. Typically, the TEOS material is supplied to a source and a low pressure chemical vapor deposition (LPCVD) method is used. Spacer oxide film 114 is formed.

However, the spacer oxide film 114 having a TEOS material as a source does not have good step coverage, and the deposition thickness of the spacer oxide film 114 is uniform between the center and edges of the wafer or between the gate pattern having a high density and the gate pattern having a low density. Unloading effects are vulnerable. As the defects of the step coverage and the loading effect become weak, the threshold voltage of the peripheral circuit region B increases, resulting in a decrease in electrical characteristics of the semiconductor device.

The technical problem to be achieved by the present invention is to improve the method of forming a spacer oxide film of a semiconductor device to improve the uniformity of the sidewall thickness of the gate spacer, thereby providing a method of forming a transistor of a semiconductor device capable of maintaining a uniform threshold voltage. There is.

In order to achieve the above technical problem, a method of forming a transistor of a semiconductor device according to the present invention comprises the steps of: forming a gate pattern on a semiconductor substrate on which a cell region and a peripheral circuit region are formed; Sequentially forming a buffer oxide film, a spacer nitride film, and a silicon film over the gate pattern and the semiconductor substrate; Oxidizing the silicon film to an oxide film for a spacer; Forming a first spacer layer by etching back the gate pattern of the peripheral circuit region after forming the photoresist pattern blocking the gate pattern of the cell region, and removing the photoresist pattern; Forming a photoresist pattern that blocks the gate pattern of the peripheral circuit region, and then removing the spacer oxide layer of the cell region; Cleaning the semiconductor substrate to remove the silicon film remaining between the gate patterns; And forming a second spacer layer by etching back to the gate pattern of the cell region.

In the present invention, the silicon film may be formed to have a thickness of 15-150 하여 including any one of a polysilicon film and an amorphous silicon film.

The silicon film may be formed at a deposition temperature of 470-650 ℃.

The step of oxidizing the silicon film into an oxide film for a spacer may be performed at an oxidation temperature of 600-900 ° C.

The step of oxidizing the silicon film into an oxide film for a spacer may be performed at an oxidation temperature of 650-1000 ° C. using a rapid thermal oxidation (RTO) method.

The silicon film remaining between the gate patterns is preferably removed using a cleaning solution containing ammonia at a temperature of 50-95 ° C.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In the drawings, the thickness is enlarged to clearly represent the layers and regions. Like parts are designated by like reference numerals throughout the specification.

2 to 8 are views illustrating a method of forming a transistor of a semiconductor device according to the present invention.

First, referring to FIG. 2, a gate pattern 211 is formed on a semiconductor substrate 200 in which a cell region A and a peripheral circuit region B are defined. The gate pattern 211 has a structure in which a gate insulating film pattern 204, a conductive film pattern 206, a metal film pattern 208, and a hard mask film pattern 210 are stacked. Although not shown in the drawings, the process of forming the gate pattern 211 is briefly described. First, a gate insulating film, a conductive film, a metal film, and a hard mask film are sequentially stacked on the semiconductor substrate 200, and then a gate pattern is formed on the hard mask film. A photosensitive film pattern to be defined is formed. Next, an etching process using the photoresist pattern as a mask is performed to form the gate pattern 211. The gate insulating film pattern 204 may be formed of an oxide film, and the conductive film pattern 206 may be formed of a polysilicon film doped with impurities or a polysilicon film not doped with impurities, and the metal film pattern 208 may be formed of an oxide film. ) May be formed of tungsten silicide (WSix) or a tungsten film, and the hard mask film pattern 210 may be formed of a nitride film. At this time, as the semiconductor device is highly integrated, the density between patterns increases, so that the cell region A is relatively dense of the gate pattern 211, and the peripheral circuit region B is relatively gate pattern 211. ) Low density.

Next, referring to FIG. 3, a buffer oxide film 212 and a nitride nitride film 214 for spacers are formed over the gate pattern 211 and the semiconductor substrate 200. The buffer oxide film 212 may be formed to have a thickness of 50 to 150 kV using a chemical mechanical deposition (CVD) method, and may prevent stress caused by direct contact between the spacer nitride film 214 and the semiconductor substrate 200. It plays a role. The spacer nitride layer 214 may be formed to have a thickness of 50 to 350 μm on the buffer oxide layer 212, and may serve as a barrier layer to prevent further etching in an etching process for forming a subsequent gate spacer. ) To prevent damage. In addition, a short between the gate pattern 211 and the landing plug formed thereafter is prevented.

Subsequently, a silicon film 216 is formed over the spacer nitride film 214. In this case, the silicon film 216 may include polysilicon or amorphous silicon, and may be formed to have a thickness of 15-150 Å. The silicon film 216 has better step coverage and loading effect characteristics than the TEOS oxide film used as a spacer oxide film, thereby improving the uniformity of the gate spacer sidewalls.

Next, referring to FIG. 4, the semiconductor substrate 200 is oxidized to oxidize the silicon film 216 to the spacer oxide film 218. The oxidation process may use a thermal oxidation process, and proceeds to a temperature at which the stress generated during the change of the silicon film 216 into the spacer oxide film 218 can be suppressed as much as possible. In this invention, it is preferable to advance at the temperature of 600-900 degreeC. In addition, in order to suppress the occurrence of stress during the oxidation process may proceed to Rapid Thermal Oxidation (RTO; Rapid Thermal Oxidation), the rapid thermal oxidation is preferably carried out at 650-1000 ℃.

배 이상의 두께를 산화시키는 것이 바람직하다. On the other hand, in the case of the cell region A having a high density between the gate patterns 211 while the silicon film 216 is oxidized, and the space between the gate patterns 211 is narrow, the inlet of the gate pattern 211 is completely formed by the volume expansion. It may be a clogging situation. In addition, since the silicon film 216 is deposited thicker than other portions in the valleys between the gate patterns 211, the oxidation is not completely performed, and the silicon film 220 may remain at the bottom of the valleys. In this case, a long oxidation time is required to oxidize all of the lower silicon film 220. However, since the oxidation process applies a high-temperature thermal budget to the semiconductor substrate 200, impurities in the well region previously formed by ion implantation may be moved again. Accordingly, in order to completely oxidize the silicon film 216 without leaving the thermal budget applied to the semiconductor substrate 200, the deposition thickness of the silicon film 216 may be reduced.

It is preferable to oxidize at least twice the thickness.

Next, referring to FIG. 5, after the photoresist pattern 222 is formed to block the gate pattern 211 of the cell region A, an etching back is performed on the gate pattern 211 of the peripheral circuit region B. FIG. As a result, the first spacer layer 230 having the structure in which the buffer oxide layer 224, the spacer nitride layer 226, and the spacer oxide layer 228 are stacked is formed. Next, the photosensitive film pattern 222 is removed.

Next, referring to FIG. 6, after forming the photoresist pattern 232 that blocks the gate pattern 211 of the peripheral circuit region B, the spacer oxide layer 218 of the cell region A is removed. In this case, the spacer oxide layer 218 of the cell region A may be removed using wet etching.

Subsequently, the remaining silicon film 220 remaining in the valleys between the gate patterns 211 is removed using a cleaning solution containing ammonia with a high temperature of 50-95 ° C., for example, an SC-1 solution. The SC-1 solution is a solution in which ammonia, hydrogen peroxide, and water are mixed at a ratio of 1: 4: 20. As shown in FIG. 8, the SC-1 solution has a higher etching selectivity in silicon than an oxide film and a nitride film. At this time, while the spacer nitride film 214 of the cell region A suppresses the SC-1 solution from penetrating into the semiconductor substrate 200, the remaining silicon film 220 remaining between the gate patterns 211 is 50. All are removed by a hot SC-1 solution at -95 ° C leaving only the spacer nitride film 214.

Next, referring to FIG. 7, the second spacer layer 238 including the buffer oxide layer 234 and the spacer nitride layer 236 is formed by etching back to the gate pattern 211 of the cell region A. Referring to FIG.

As described so far, according to the transistor forming method of the semiconductor device according to the present invention, by using the silicon film as the spacer material, the thickness uniformity of the entire surface of the wafer can be improved and the threshold voltage can be stabilized. In addition, by removing the silicon film that is not completely oxidized in the oxidation process using a cleaning solution containing ammonia, it is possible to prevent the bridge phenomenon of the landing plug contact or the phenomenon that the landing plug does not open.

Claims (8)

Forming a gate pattern on the semiconductor substrate on which the cell region and the peripheral circuit region are formed; Sequentially forming a buffer oxide film, a spacer nitride film, and a silicon film over the gate pattern and the semiconductor substrate; Performing a thermal oxidation process on the silicon film to oxidize the silicon film to form an oxide film for a spacer; Forming a first spacer layer by etching back the gate pattern of the peripheral circuit region after forming the photoresist pattern blocking the gate pattern of the cell region, and removing the photoresist pattern; Forming a photoresist pattern that blocks the gate pattern of the peripheral circuit region, and then removing the spacer oxide layer of the cell region; Cleaning the semiconductor substrate to remove the silicon film remaining between the gate patterns; And Forming a second spacer layer by performing etch back on the gate pattern of the cell region. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, And the silicon film comprises one of a polysilicon film and an amorphous silicon film. Claim 3 has been abandoned due to the setting registration fee. The method of claim 1, And the silicon film is formed to a thickness of 15-150 kHz. Claim 4 has been abandoned due to the setting registration fee. The method of claim 1, The silicon film is a transistor forming method of a semiconductor device, characterized in that formed at a deposition temperature of 470-650 ℃. Claim 5 was abandoned upon payment of a set-up fee. The method of claim 1, And oxidizing the silicon film to form an oxide film for a spacer, wherein the oxide film is formed at an oxidation temperature of 600-900 ° C. Claim 6 has been abandoned due to the setting registration fee. The method of claim 1, And oxidizing the silicon film to form an oxide film for a spacer, using a rapid thermal oxidation (RTO) method to proceed at an oxidation temperature of 650-1000 ° C. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 1, The silicon film remaining between the gate patterns is removed using a cleaning solution containing ammonia at a temperature of 50-95 ℃. Claim 8 was abandoned when the registration fee was paid. The method of claim 1, And forming the spacer oxide layer to a thickness thicker than the thickness of the silicon layer.

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