JP2008135765A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device excellent in electrical characteristics by increasing the separation between a gate electrode and an extension region and a method for manufacturing the same, and at the same time, to provide a semiconductor device capable of etching a high dielectric insulating film without damaging a backing semiconductor substrate and a method for manufacturing the same. <P>SOLUTION: By dry etching when forming a gate electrode 8, a high dielectric insulating film 7 is changed into a damage layer and the damage layer is removed by wet etching. In a process for forming the gate electrode 8, a dimension W<SB>2</SB>in the direction of width is made smaller than a dimension W<SB>1</SB>in the direction of width of the high dielectric insulating film 7 by the etching in the direction of sidewall of the gate electrode 8. Preferably, the difference between W<SB>1</SB>and W<SB>2</SB>is in a range of 5 nm to 60 nm. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having an insulating film having a high dielectric constant and a manufacturing method thereof.

  2. Description of the Related Art In recent years, high integration in semiconductor integrated circuit devices has greatly advanced, and in a MOS (Metal Oxide Semiconductor) type semiconductor device, elements such as transistors and the like for achieving high integration have been miniaturized and improved in performance. Yes. In particular, with regard to the gate insulating film which is one of the elements constituting the MOS structure, the thinning is rapidly progressing to cope with the miniaturization, high speed operation and low voltage of the transistor.

As a material constituting the gate insulating film, a silicon oxide film (SiO ₂ film) has been conventionally used. On the other hand, when the gate insulating film becomes thinner with the miniaturization of the gate electrode, the tunnel current generated by the carriers (electrons and holes) directly tunneling through the gate insulating film, that is, the gate leakage current increases. . For example, a gate insulating film required for a 130 nm node device is about 2 nm in thickness of a silicon oxide film, but this region is a region where a tunnel current starts to flow. Therefore, when a silicon oxide film is used as the gate insulating film, the gate leakage current cannot be suppressed and the power consumption increases.

  In view of this, research has been conducted in which a material having a higher dielectric constant is used as the gate insulating film instead of the silicon oxide film.

  20 to 23 are cross-sectional views showing a manufacturing process of a field effect transistor by a conventional method when a high dielectric constant insulating film is used as a gate insulating film.

  First, element isolation regions 43 and 43 'and a diffusion layer 42 are formed on a silicon substrate 41 using a known method, and then a silicon oxide film 44 is formed by a thermal oxidation method. Next, a high dielectric constant insulating film 45, a polycrystalline silicon film 46 as a gate electrode material, and a silicon oxide film 47 as a hard mask are grown in order. Thereafter, a resist pattern 48 is formed by photolithography (FIG. 20).

  Next, the silicon oxide film 47 is dry-etched using the resist pattern 48 as a mask to form a silicon oxide film pattern 49 (FIG. 21).

  Next, the polycrystalline silicon film 46 is dry-etched using the silicon oxide film pattern 49 as a mask. Thereby, the gate electrode 50 is formed (FIG. 22). Thereafter, the high dielectric constant insulating film 45 and the silicon oxide film 44 are sequentially etched, and then extension regions 51 and 51 ', halo layers 52 and 52', sidewalls 53, and source / drain regions 54 and 54 'are formed. The structure shown in FIG.

  Conventionally, the extension regions 51 and 51 'are formed by ion implantation using the gate electrode 50 as a mask. However, when the extension injection region is formed at a distance of about 5 nm to 30 nm from the gate electrode, the leakage current at the time of OFF can be reduced, and a high-performance device can be obtained.

  The halo layers 52 and 52 'are impurity regions of the opposite type to the extension regions 51 (hereinafter referred to as halo layers), and have a role of adjusting the shape and depth of the junction. The halo layers 52 and 52 ′ are formed by implanting impurity ions obliquely with respect to the silicon substrate 41. Conventionally, ion implantation has been performed using the gate electrode 50 as a mask and the angle θ between the normal direction 55 of the silicon substrate 41 and the ion incident direction 56 being 20 degrees to 30 degrees. However, in this case, there is a problem that a region where adjacent halo layers 52 and 52 ′ overlap with each other in the channel portion becomes large, and a portion with a high impurity concentration is formed partially.

  Further, when the high dielectric constant insulating film 45 is etched, the selection ratio between the high dielectric constant insulating film 45 and the underlying silicon oxide film 44 can be obtained only at a value of 0.5 or less. In addition, there is a problem that the silicon substrate 41 underneath is etched.

  In general, in the manufacturing process of a semiconductor device, over-etching is performed in order to prevent generation of etching residues due to variations in etching rate and film thickness of a film to be processed. In the case of the high dielectric constant insulating film 45, if the state where the largest film thickness is etched is the state of just etching, over etching is performed thereafter. In the over-etching step, the time until the underlying silicon oxide film 44 is etched and the thinnest part of the silicon oxide film 44 disappears by etching is considered as a process margin.

  However, the high dielectric constant insulating film 45 has a large expected variation because peripheral techniques such as a film forming technique and an etching technique are not mature. For this reason, there has been a problem that the over-etching time required by calculation easily exceeds the process margin. When etching is performed beyond the process margin, the silicon substrate 41 underlying the silicon oxide film 44 is etched as described above, and the electrical characteristics and reliability of the semiconductor device are degraded.

  The present invention has been made in view of such problems. That is, an object of the present invention is to provide a semiconductor device having excellent electrical characteristics by increasing the distance between a gate electrode and an extension region and a method for manufacturing the same.

  Another object of the present invention is to provide a semiconductor device having excellent electrical characteristics by reducing the overlap of halo layers in the channel portion and a method for manufacturing the same.

  Furthermore, an object of the present invention is to provide a semiconductor device having excellent electrical characteristics and reliability and a method for manufacturing the same by etching a high dielectric constant insulating film without damaging the underlying semiconductor substrate. is there.

  Other objects and advantages of the present invention will become apparent from the following description.

  The present invention provides an oxide film containing silicon formed on a semiconductor substrate, a high dielectric constant insulating film formed on the oxide film containing silicon, and formed on the high dielectric constant insulating film. A semiconductor device having a gate electrode, characterized in that a dimension in the width direction of the high dielectric constant insulating film is larger than a dimension in the width direction of the gate electrode. The difference between the dimension in the width direction of the high dielectric constant insulating film and the dimension in the width direction of the gate electrode is preferably in the range of 5 nm to 60 nm.

  The present invention also provides an oxide film containing silicon formed on a semiconductor substrate, a high dielectric constant insulating film formed on the oxide film containing silicon, and formed on the high dielectric constant insulating film. A high-dielectric-constant insulating film having a tapered shape in which the cross-sectional shape of the high-dielectric-constant insulating film increases in the width direction as it approaches the oxide film containing silicon. Is characterized in that the dimension in the width direction of the high dielectric constant insulating film in the portion in contact with the oxide film containing silicon is larger than the dimension in the width direction of the gate electrode.

  In the semiconductor device of the present invention, the high dielectric constant insulating film is made of at least one material selected from the group consisting of hafnium oxide, titanium oxide, zirconium oxide, lanthanum oxide, tantalum oxide, and aluminum oxide. It can be a membrane. The oxide film containing silicon can be one film selected from the group consisting of a silicon oxide film, a silicon oxynitride film, and a silicate film.

  A method of manufacturing a semiconductor device according to the present invention includes a step of forming an oxide film containing silicon on a semiconductor substrate on which a diffusion layer and an element isolation region are formed, and a high dielectric constant insulating film on the oxide film containing silicon. Forming a gate electrode material on the high dielectric constant insulating film, forming a hard mask on the gate electrode material, and drying the gate electrode material using the hard mask. The gate electrode is formed by etching, the step of changing the entire high dielectric constant insulating film into a damaged layer by this dry etching, the step of removing this damaged layer by wet etching, and the high dielectric constant insulating film as a mask Implanting impurities into the semiconductor substrate to form extension regions, and using the high dielectric constant insulating film as a mask, And a step of forming a halo layer by implanting an impurity of a type opposite to that of the tension region, and performing etching in the direction of the side wall of the gate electrode in the step of forming the gate electrode. The dimension is smaller than the dimension in the width direction of the high dielectric constant insulating film.

  The method for manufacturing a semiconductor device according to the present invention includes a step of forming an oxide film containing silicon on a semiconductor substrate on which a diffusion layer and an element isolation region are formed, and a high dielectric constant on the oxide film containing silicon. A step of forming an insulating film, a step of forming a gate electrode material on the high dielectric constant insulating film, a step of forming a hard mask on the gate electrode material, and a gate electrode material using the hard mask The process of forming the gate electrode by dry etching and dry etching the high dielectric constant insulating film using a hard mask and leaving only the damaged layer formed on the high dielectric constant insulating film by this dry etching Removing the film, removing the damaged layer by wet etching, and implanting impurities into the semiconductor substrate using the high dielectric constant insulating film as a mask A step of forming an extension region and a step of forming a halo layer by implanting an impurity of a type opposite to the extension region into a semiconductor substrate using a high dielectric constant insulating film as a mask, and forming a gate electrode. Etching in the direction of the side wall of the electrode makes the dimension in the width direction of the gate electrode smaller than the dimension in the width direction of the high dielectric constant insulating film.

  The method for manufacturing a semiconductor device according to the present invention includes a step of forming an oxide film containing silicon on a semiconductor substrate on which a diffusion layer and an element isolation region are formed, and a high dielectric constant on the oxide film containing silicon. A step of forming an insulating film, a step of forming a gate electrode material on the high dielectric constant insulating film, a step of forming a hard mask on the gate electrode material, and a gate electrode material using the hard mask Forming a gate electrode by dry etching, changing the whole of the high dielectric constant insulating film into a damaged layer by dry etching, removing the damaged layer by wet etching, and forming a high dielectric constant insulating film Implanting impurities into the semiconductor substrate as a mask to form an extension region, and semiconductor substrate using a high dielectric constant insulating film as a mask A step of injecting impurities opposite to the extension region to form a halo layer, and in the step of forming the gate electrode, etching is performed in the direction of the sidewall of the gate electrode, and the film of the high dielectric constant insulating film By changing the amount of damage in the thickness direction, the cross-sectional shape of the high dielectric constant insulating film is a tapered shape in which the dimension in the width direction increases as it approaches the oxide film containing silicon, and the high dielectric constant insulating film contains silicon. The dimension in the width direction of the high dielectric constant insulating film in the portion in contact with the oxide film is made larger than the dimension in the width direction of the gate electrode. By adjusting at least one of the etching time and the plasma power density in the step of forming the gate electrode, the amount of damage in the film thickness direction of the high dielectric constant insulating film can be changed.

  Further, the method of manufacturing a semiconductor device according to the present invention includes a step of forming an oxide film containing silicon on a semiconductor substrate on which a diffusion layer and an element isolation region are formed, and a high dielectric constant on the oxide film containing silicon. A step of forming an insulating film, a step of forming a gate electrode material on the high dielectric constant insulating film, a step of forming a hard mask on the gate electrode material, and a gate electrode material using the hard mask The process of forming the gate electrode by dry etching and dry etching the high dielectric constant insulating film using a hard mask and leaving only the damaged layer formed on the high dielectric constant insulating film by this dry etching Removing the film, removing the damaged layer by wet etching, and injecting impurities into the semiconductor substrate using the high dielectric constant insulating film as a mask. A step of forming a gate electrode, and a step of forming a halo layer by implanting an impurity of a type opposite to the extension region into a semiconductor substrate using a high dielectric constant insulating film as a mask. A taper in which the dimension in the width direction increases as the cross-sectional shape of the high dielectric constant insulating film comes closer to the oxide film containing silicon in the step of performing etching in the direction of the side wall of the gate electrode and dry etching the high dielectric constant insulating film By making the shape, the dimension in the width direction of the high dielectric constant insulating film in the portion where the high dielectric constant insulating film is in contact with the oxide film containing silicon is larger than the dimension in the width direction of the gate electrode. .

In the method for manufacturing a semiconductor device of the present invention, dry etching is performed using at least one gas selected from the group consisting of BCl ₃ , Cl ₂ , HBr, CF ₄ , O ₂ , Ar, N ₂ and He. Can do. Further, wet etching can be performed using a DHF solution or a BHF solution.

  According to the present invention, ion implantation using the high dielectric constant insulating film as a mask is performed by making the dimension in the width direction of the gate electrode smaller than the dimension in the width direction of the high dielectric constant insulating film. Thereby, the extension region can be formed at a predetermined interval from the gate electrode.

  Further, according to the present invention, the angle formed between the incident angle of ions and the normal direction of the substrate can be made smaller than before by processing the high dielectric constant insulating film into a tapered shape. Thereby, the overlap of impurities in the channel portion can be reduced to reduce the reverse short channel effect.

  Furthermore, according to the present invention, a damaged layer is formed on the high dielectric constant insulating film, and the damaged layer is removed by wet etching. Therefore, the high dielectric constant insulating film can be etched without damaging the underlying silicon substrate.

  Embodiments of the present invention will be specifically described below with reference to the drawings.

Embodiment 1
FIG. 1 is an example of a cross-sectional view of the semiconductor device according to this embodiment.

  As shown in FIG. 1, a diffusion layer 2, element isolation regions 3 and 3 ', source / drain regions 4 and 4', extension regions 5 and 5 ', and halo layers 17 and 17' are formed on the silicon substrate 1. ing. On the silicon substrate 1, a silicon oxide film 6 as a silicon-containing oxide film, a high dielectric constant insulating film 7, and a gate electrode 8 are formed in this order, and side walls 9 are formed on these sidewalls. Has been. In FIG. 1, 10 is an interlayer insulating film, 11 is a contact, and 12 is a wiring layer.

  This embodiment is characterized in that the dimension W1 in the width direction of the high dielectric constant insulating film 7 is larger than the dimension W2 in the width direction of the gate electrode 8. With such a structure, the distance from the gate electrode 8 to each of the extension regions 5 and 5 'is increased, and the overlap of the halo layers 17 and 17' in the channel portion is reduced, so that the electrical characteristics of the semiconductor device are increased. Characteristics can be improved.

  In FIG. 1, the silicon oxide film 6 has the same width direction dimension W1 as that of the high dielectric constant insulating film 7, but the present invention is not limited to this. In the present invention, it is important that there is a relationship of W1> W2 between the high dielectric constant insulating film 7 and the gate electrode 8, and the dimension in the width direction of the silicon oxide film 6 is not particularly limited.

  FIG. 2 shows an example of the electrical characteristics of the semiconductor device (W1> W2) according to this embodiment. In addition, as Comparative Example 1, electrical characteristics of a semiconductor device (W1 = W2) according to a conventional method are also shown. In FIG. 2, when the current value when the voltage is 0 V is compared, the semiconductor device according to the present embodiment shows a value that is about one digit smaller than the semiconductor device according to the conventional method, and has good electrical characteristics. I understand.

  Next, a method for manufacturing the semiconductor device according to the present embodiment will be described. 3 to 13 are cross-sectional views showing an example of manufacturing steps of the semiconductor device shown in FIG. In these drawings, the same reference numerals as those in FIG. 1 indicate the same parts.

  First, as shown in FIG. 3, a silicon oxide film is embedded in a predetermined region of the silicon substrate 1 to form element isolation regions 3 and 3 ′ having an STI (Shallow Trench Isolation) structure.

  Next, the diffusion layer 2 is formed on the silicon substrate 1 using a photolithography method. For example, a resist pattern (not shown) is formed in a predetermined region, and N-type or P-type impurities are implanted into the silicon substrate 1 using this resist pattern as a mask. Thereafter, an N-type diffusion layer or a P-type diffusion layer can be formed by diffusing impurities by heat treatment.

  Next, as shown in FIG. 4, a silicon oxide film 6 is formed on the surface of the silicon substrate 1. Here, the silicon oxide film 6 is preferably formed as thin as possible. Specifically, a film thickness of about 0.5 nm to 2 nm is used by dry oxidation performed at a temperature of 800 ° C. to 1,200 ° C., radical oxidation using plasma at a low temperature, or ozone oxidation. it can. In this embodiment, a silicon oxynitride film or a silicate film may be formed instead of the silicon oxide film. As the silicon oxynitride film, for example, a silicon oxide film added with nitrogen at a concentration of 25 atom% or less can be used.

  After the silicon oxide film 6 is formed, a high dielectric constant insulating film 7 is subsequently formed (FIG. 4). The high dielectric constant insulating film 7 can be a film made of at least one material selected from the group consisting of hafnium oxide, titanium oxide, zirconium oxide, lanthanum oxide, tantalum oxide, and aluminum oxide. .

For next-generation semiconductor devices with a design rule of 0.15 μm or less, for example, a hafnium oxide film (HfO ₂ film) with a film thickness of about ₂ nm to 10 nm formed by ALD (Atomic Layer Deposition) is used. It is preferable to use it as a dielectric constant insulating film.

  From the viewpoint of electrical characteristics of the semiconductor device, the total thickness of the silicon oxide film 6 and the high dielectric constant insulating film 7 is 1.0 nm to 5.0 nm in terms of silicon oxide film equivalent thickness (EOT). It is preferable to be within the range.

  Next, as shown in FIG. 5, a polycrystalline silicon film 13 as a gate electrode material is formed on the high dielectric constant insulating film 7. The polycrystalline silicon film 13 can be formed by, for example, a CVD method. In place of the polycrystalline silicon film 13, an amorphous silicon film may be used as the gate electrode.

  After the polycrystalline silicon film 13 is formed, a silicon oxide film 14 as a hard mask material is formed thereon.

  After the silicon oxide film 14 is formed, an antireflection film (not shown) may be formed thereon. The antireflection film plays a role of eliminating exposure light reflection at the interface between the resist film and the antireflection film by absorbing exposure light transmitted through the resist film when patterning a resist film to be formed next. As the antireflection film, a film containing an organic substance as a main component can be used. For example, the antireflection film can be formed by a spin coating method or the like.

  Next, a resist film (not shown) is formed on the silicon oxide film 14, and a resist pattern 15 having a desired line width is formed by photolithography to obtain the structure of FIG.

  Next, the silicon oxide film 14 is dry etched using the resist pattern 15 as a mask. Thereafter, by removing the resist pattern 15 which is no longer necessary, a silicon oxide film pattern 16 as a hard mask can be formed as shown in FIG.

Next, dry etching of the polycrystalline silicon film 13 is performed using the silicon oxide film pattern 16 as a mask. As the etching gas, for example, at least one gas selected from the group consisting of BCl ₃ , Cl ₂ , HBr, CF ₄ , O ₂ , Ar, N ₂ and He is used.

  Here, the etching selection ratio between the polycrystalline silicon film 13 and the underlying high dielectric constant insulating film 7 generally has a sufficiently large value. Therefore, the polycrystalline silicon film 13 can be etched so as to be overetched, but in the present embodiment, the process further proceeds and a damaged layer is formed by dry etching on the entire high dielectric constant insulating film 7. Like that. In order to achieve this object, the silicon oxide film 14 is preferably formed thicker than before. Specifically, the thickness of the silicon oxide film 14 is preferably about 10 nm to 100 nm.

  The high dielectric constant insulating film is altered by plasma damage during dry etching, implantation of an etching species, or the like, and forms a damage layer that can be removed by wet etching. Therefore, in the present embodiment, the polycrystalline silicon film is dry-etched, and the high dielectric constant insulating film is changed to a damaged layer by this dry etching. Thereafter, wet etching is performed to remove the damaged layer, thereby completing the etching of the high dielectric constant insulating film in place of the conventional dry etching. According to this method, the high dielectric constant insulating film can be etched without damaging the silicon substrate. Accordingly, unlike the conventional method, a heat treatment or the like for recovering the damage applied to the silicon substrate is unnecessary.

  FIG. 8 shows a state after the polycrystalline silicon film 13 is dry-etched. As shown in the figure, a gate electrode 8 is formed by dry etching of the polycrystalline silicon film 13, and a damaged layer 7 'is formed in a portion of the high dielectric constant insulating film 7 exposed to plasma.

For the wet etching of the damaged layer 7 ′, for example, a DHF solution (a mixed solution of HF and H ₂ O) or a BHF solution (a mixed solution of HF, NH ₄ F and H ₂ O) can be used. Note that a part or all of the silicon oxide film 6 which is the base of the high dielectric constant insulating film 7 may be removed together by this wet etching.

  In the present embodiment, dry etching in the direction of the side wall of the gate electrode 8 is also performed by adjusting the composition ratio, pressure, and the like of the etching gas. By doing so, the dimension in the width direction of the gate electrode 8 can be reduced. On the other hand, in the region where the gate electrode 8 is etched in the direction of the side wall, plasma damage in the direction perpendicular to the main surface 1a of the silicon substrate 1 and damage due to collision of etching species are reduced. The amount of damage given to the high dielectric constant insulating film 7 is small. As a result, the high dielectric constant insulating film 7 is difficult to be removed by wet etching, so that the dimension in the width direction of the high dielectric constant insulating film 7 can be made larger than the dimension in the width direction of the gate electrode 8.

FIG. 9 is a diagram showing a state after wet etching. As shown in the drawing, the dimension W _{1 in} the width direction of the high dielectric constant insulating film 7 is larger than the dimension W _{2 in} the width direction of the gate electrode 8. Here, the difference between the dimension W ₁ and the dimension W ₂ is preferably in the range of 5 nm to 60 nm. FIG. 9 shows a state where the silicon oxide film 6 is also removed by wet etching.

  In this embodiment, the high dielectric constant insulating film may be dry-etched subsequent to the dry etching of the polycrystalline silicon film, and then the damaged layer may be wet-etched.

  Specifically, after the polycrystalline silicon film is dry etched, the high dielectric constant insulating film is dry etched using a hard mask. As described above, dry etching of the polycrystalline silicon film is accompanied by etching in the direction of the side wall of the gate electrode to be formed. On the other hand, the dry etching of the high dielectric constant insulating film is completed so that only the damaged layer remains. Thereafter, all the high dielectric constant insulating films are removed by wet etching the remaining damaged layer. Here, the film thickness of the damage layer to be formed varies depending on the dry etching conditions and the type of the high dielectric constant insulating film. On the other hand, the larger the damage layer thickness, the larger the etching margin. Therefore, it is preferable to set the film thickness of the high dielectric constant insulating film to be removed by dry etching in consideration of these conditions.

  Note that when the high dielectric constant insulating film is dry-etched, the side walls of the gate electrode are also slightly etched. Therefore, before the dry etching of the high dielectric constant insulating film, the dimension in the width direction of the gate electrode is previously set to a dimension to which the amount disappeared by the etching is added. By doing so, a desired gate electrode pattern can be formed. Specifically, the dimensions of the gate electrode can be controlled by changing the composition ratio or pressure of the etching gas in the dry etching process of the polycrystalline silicon film.

Next, as shown in FIG. 10, after ion-implanting impurities into the diffusion layer 2 in the silicon substrate 1, the extension regions 5 and 5 'are formed by activation by heat treatment. In the present embodiment, since there is a relationship of W ₂ <W ₁ between the dimension W _{2 in} the width direction of the gate electrode and the dimension W _{1 in} the width direction of the high dielectric constant insulating film, the extension regions 5, 5 ′ The high dielectric constant insulating film 7 is not the gate electrode 8 but serves as a mask during the formation.

  From the viewpoint of device characteristics, the extension regions 5 and 5 ′ are preferably formed away from the gate electrode 8. Specifically, if the distance between the extension region 5 and the gate electrode 8 and the distance between the extension region 5 ′ and the gate electrode 8 are in the range of about 5 nm to 30 nm, respectively, the generation of leakage current is suppressed and a high performance semiconductor is achieved. The device can be manufactured. According to the present embodiment, the extension regions 5 and 5 ′ are formed by ion implantation using the high dielectric constant insulating film 7 as a mask. Therefore, the extension regions 5 and 5 ′ are formed at a position away from the gate electrode 8. Can do.

  Next, the sidewalls 9 are formed according to a known method to obtain the structure shown in FIG. At this time, the side walls 9 are formed on the side walls of the gate electrode 8, the high dielectric constant insulating film 7 and the silicon oxide film 6. If a portion of the silicon oxide film 6 remains on the silicon substrate 1 after wet etching of the high dielectric constant insulating film 7, except under the high dielectric constant insulating film 7 and the sidewalls 9, The silicon oxide film 6 is removed when the sidewalls 9 are formed.

  After the sidewalls 9 are formed, as shown in FIG. 12, halo implantation is performed using the high dielectric constant insulating film 7 as a mask. According to the present embodiment, since the high dielectric constant insulating film 7 has a dimension in the width direction larger than that of the gate electrode 8, the halo layer 17 in the channel portion is compared with the conventional halo implantation performed using the gate electrode 8 as a mask. , 17 'can be reduced. In FIG. 12, reference numerals 18 and 18 'denote ion incident directions.

  In the present embodiment, the sidewalls 9 may be formed after the halo implantation is performed following the formation of the extension regions 5 and 5 '. In addition, in the formation of the extension regions 5 and 5 ′ and the halo implantation process, it is preferable to set the ion incident energy high in consideration of the stopping power by the high dielectric constant insulating film 7.

  Next, as in the conventional method, impurities are ion-implanted into the diffusion layer 2 in the silicon substrate 1. Subsequently, activation by heat treatment can be performed to form the source / drain diffusion regions 4 and 4 '(FIG. 13). Thereafter, the structure shown in FIG. 1 can be obtained by forming the interlayer insulating film 10, the contact 11 and the wiring 12 by a known method.

  According to the present embodiment, the dimension in the width direction of the gate electrode is made smaller than the dimension in the width direction of the high dielectric constant insulating film, and the extension region is formed and the halo implantation is performed using the high dielectric constant insulating film as a mask. The distance between the electrode and the extension region can be increased. In addition, the overlap of the halo layers in the channel portion can be reduced. Thereby, it becomes possible to reduce the leakage current at the time of OFF. Note that according to the present embodiment, it is not necessary to form an offset spacer, which has been conventionally required with miniaturization.

  Further, according to the present embodiment, the high dielectric constant insulating film is changed into a damaged layer in the dry etching process when forming the gate electrode, and the high dielectric constant insulating film is processed into a desired pattern by wet etching. To do. As a result, the high dielectric constant insulating film can be etched without damaging the silicon substrate.

Embodiment 2. FIG.
FIG. 14 is an example of a cross-sectional view of the semiconductor device according to this embodiment.

  As shown in FIG. 14, a diffusion layer 22, element isolation regions 23 and 23 ', source / drain regions 24 and 24', extension regions 25 and 25 ', and halo layers 37 and 37' are formed on the silicon substrate 21. ing. On the silicon substrate 21, a silicon oxide film 26 as a film containing silicon, a high dielectric constant insulating film 27, and a gate electrode 28 are formed in this order, and sidewalls 29 are formed on these sidewalls. ing. In FIG. 14, 30 is an interlayer insulating film, 31 is a contact, and 32 is a wiring layer.

In the present embodiment, the high dielectric constant insulating film 27 has a tapered shape in which the dimension in the width direction increases as it approaches the silicon oxide film 26, and the high dielectric constant insulating film 27 is further oxidized by silicon oxide. A feature is that a width dimension W ₃ in a portion in contact with the film 26 is larger than a width dimension W _{4 of the} gate electrode 28. By adopting such a structure, the angle formed by the incident direction of ions in the halo implantation step and the normal direction of the silicon substrate 21 is reduced, and the overlap of the halo layers 37 and 37 'in the channel portion is reduced. be able to.

  Conventionally, halo implantation has been performed so that the angle formed by the normal direction of the silicon substrate and the incident direction of ions is 20 degrees to 30 degrees. However, in a miniaturized semiconductor device, the line width of the gate electrode pattern is reduced, and the integrated circuits are arranged close to each other. Therefore, in consideration of shadowing during ion implantation, the angle formed by the normal direction of the silicon substrate and the ion incident direction is preferably 0 degrees.

  FIG. 15 shows an example of the result of measuring the change in threshold voltage with respect to the gate length for the semiconductor device according to the present embodiment. In the example shown in the figure, the halo implantation is performed so that the angle formed by the normal direction of the silicon substrate and the incident direction of ions is 0 degrees. Further, as Comparative Example 2, the result of the semiconductor device according to the conventional method shown in FIG. 23 is also shown. In Comparative Example 2, the angle formed by the normal direction of the silicon substrate and the incident direction of ions is 20 degrees. As can be seen from FIG. 15, according to the present embodiment, it is possible to satisfactorily suppress the reverse short channel effect while maintaining the roll-off characteristics equivalent to the conventional one.

  Next, a method for manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS.

  First, element isolation regions 23 and 23 'and a diffusion layer 22 are formed on a silicon substrate 21 in accordance with the method shown in FIGS. 3 to 7 described in the first embodiment, and then a silicon oxide film 26 and a high dielectric constant are formed thereon. A rate insulating film 27, a polycrystalline silicon film 33 as a gate electrode material, and a silicon oxide film pattern 36 as a hard mask are formed in this order to obtain the structure shown in FIG.

  In this embodiment, a silicon oxynitride film or a silicate film may be formed instead of the silicon oxide film. As the silicon oxynitride film, for example, a silicon oxide film added with nitrogen at a concentration of 25 atom% or less can be used. The high dielectric constant insulating film 27 is, for example, a film made of at least one material selected from the group consisting of hafnium oxide, titanium oxide, zirconium oxide, lanthanum oxide, tantalum oxide, and aluminum oxide. Can be used.

Next, the polycrystalline silicon film 33 is dry etched using the silicon oxide film pattern 36 as a mask. As an etching gas, for example, at least one gas selected from the group consisting of BCl ₃ , Cl ₂ , HBr, CF ₄ , O ₂ , Ar, N ₂ and He can be used.

  Similarly to the first embodiment, when the polycrystalline silicon film 33 is dry-etched, a damage layer 27 ′ is formed by dry etching on the entire high dielectric constant insulating film 27 (FIG. 17). For this reason, the silicon oxide film pattern 36 as a hard mask is preferably formed thicker than the conventional one, as in the first embodiment.

Next, the etching of the high dielectric constant insulating film is completed by removing the damaged layer by wet etching. For wet etching, for example, a DHF solution (a mixed solution of HF and H ₂ O) or a BHF solution (a mixed solution of HF, NH ₄ F and H ₂ O) can be used. Note that a part or all of the silicon oxide film 26 which is the base of the high dielectric constant insulating film 27 may be removed together by this wet etching.

  Similarly to the first embodiment, dry etching is also performed in the direction of the side wall of the gate electrode 28 by adjusting the composition ratio and pressure of the etching gas. By doing so, the dimension of the gate electrode 28 in the width direction can be reduced. On the other hand, in the region where the gate electrode 28 is etched in the direction of the side wall, plasma damage in a direction perpendicular to the main surface 21a of the silicon substrate 21 and damage due to collision of etching species are reduced. The amount of damage given to the high dielectric constant insulating film 27 is small. As a result, the high dielectric constant insulating film 27 is difficult to be removed by wet etching, so that the dimension in the width direction of the high dielectric constant insulating film 27 can be made larger than the dimension in the width direction of the gate electrode 28.

In the present embodiment, further, by adjusting at least one of the etching time and the plasma power density in the dry etching process, the amount of damage applied to the high dielectric constant insulating film 27 is reduced as shown in FIG. Change direction as well. By doing so, as shown in FIG. 18, the cross-sectional shape of the high dielectric constant insulating film 27 after the wet etching can be tapered. Here, since the dimension in the width direction of the gate electrode 28 is reduced by etching in the direction of the side wall of the gate electrode 28, the high dielectric constant insulating film in a portion where the high dielectric constant insulating film 27 is in contact with the silicon oxide film 26. The dimension W _{3 in} the width direction 27 is larger than the dimension W _{4 in} the width direction of the gate electrode 28.

  In this embodiment, the high dielectric constant insulating film may be dry-etched subsequent to the dry etching of the polycrystalline silicon film, and then the damaged layer may be wet-etched.

  Specifically, after the polycrystalline silicon film is dry etched, the high dielectric constant insulating film is dry etched using a hard mask. At this time, the etching conditions are adjusted so that the cross-sectional shape of the high dielectric constant insulating film is tapered. Then, the dry etching is finished so that only the damaged layer formed by the dry etching remains. Thereafter, all the high dielectric constant insulating films are removed by wet etching the remaining damaged layer. Here, the film thickness of the damage layer to be formed varies depending on the dry etching conditions and the type of the high dielectric constant insulating film. On the other hand, the larger the damage layer thickness, the larger the etching margin. Therefore, it is preferable to set the film thickness of the high dielectric constant insulating film to be removed by dry etching in consideration of these conditions.

  When the high dielectric constant insulating film is dry-etched, the side wall portion of the gate electrode is also etched. Therefore, before the dry etching of the high dielectric constant insulating film, the dimension in the width direction of the gate electrode is previously set to a dimension to which the amount disappeared by the etching is added. By doing so, a desired gate electrode pattern can be formed. Specifically, the dimensions of the gate electrode can be controlled by changing the composition ratio or pressure of the etching gas in the dry etching process of the polycrystalline silicon film.

  Next, after implanting impurities into the diffusion layer 22 in the silicon substrate 21 using the high dielectric constant insulating film 27 as a mask, extension regions 25 and 25 ′ are formed by activation by heat treatment. According to the present embodiment, since the cross-sectional shape of the high-dielectric-constant insulating film 27 is processed into a tapered shape, the distance between the gate electrode 28 and each of the extension regions 25 and 25 ′ can be made larger than before.

  After the extension regions 25 and 25 'are formed, the sidewalls 29 are formed according to a known method, and then halo implantation is performed using the high dielectric constant insulating film 27 as a mask (FIG. 19).

  If a part of the silicon oxide film 26 remains on the silicon substrate 21 after wet etching of the high dielectric constant insulating film 27, except under the high dielectric constant insulating film 27 and the sidewall 29, The silicon oxide film 26 is removed when the sidewall 29 is formed.

  According to the present embodiment, since the cross-sectional shape of the high dielectric constant insulating film 7 is processed to be tapered, the normal direction 39 of the silicon substrate 21 and the ion incident direction 38 at the time of halo implantation. The angle θ formed with 38 ′ can be reduced to 0 degree. By doing so, it is possible to reduce the reverse short channel effect by minimizing the region where impurities overlap in the channel portion. In addition, the leakage current at the off time can be reduced.

  In the present embodiment, the sidewalls 9 may be formed after the halo implantation is performed following the formation of the extension regions 5 and 5 '. In addition, in the formation of the extension regions 5 and 5 ′ and the halo implantation process, it is preferable to set the ion incident energy high in consideration of the stopping power by the high dielectric constant insulating film 7.

  Next, as in the first embodiment, impurities are ion-implanted into the diffusion layer 22 in the silicon substrate 21. Subsequently, activation by heat treatment is performed to form the source / drain diffusion regions 24, 24 ', and then the interlayer insulating film 30, the contact 31, and the wiring 32 are formed, whereby the structure shown in FIG. 14 can be obtained. .

  According to the present embodiment, the distance between the gate electrode and the extension region can be increased by making the cross-sectional shape of the high dielectric constant insulating film a tapered shape. Further, in the halo implantation step, the angle formed by the ion incident direction and the normal direction of the silicon substrate can be reduced to 0 degrees. As a result, it is possible to reduce the leakage current at the off time, and to reduce the overlap of the halo layers in the channel portion and suppress the reverse short channel effect. Further, it is possible to eliminate the formation of the offset spacer which has been conventionally required.

  Further, according to the present embodiment, the high dielectric constant insulating film is changed into a damaged layer in the dry etching process when forming the gate electrode, and the high dielectric constant insulating film is processed into a desired pattern by wet etching. To do. As a result, the high dielectric constant insulating film can be etched without damaging the silicon substrate.

  In Embodiments 1 and 2, the example in which the high dielectric constant insulating film is used as the gate insulating film of the transistor has been described. However, the present invention is not limited to this. For example, the present invention can be applied to a case where a high dielectric constant insulating film is used as a capacitor film as a passive element.

FIG. 3 is a cross-sectional view of the semiconductor device in the first embodiment. 6 is a diagram showing electrical characteristics of the semiconductor device in Embodiment 1. FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device in the first embodiment. FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device in the first embodiment. FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device in the first embodiment. FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device in the first embodiment. FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device in the first embodiment. FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device in the first embodiment. FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device in the first embodiment. FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device in the first embodiment. FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device in the first embodiment. FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device in the first embodiment. FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device in the first embodiment. FIG. FIG. 10 is a cross-sectional view of the semiconductor device in the second embodiment. FIG. 10 is a diagram showing a relationship between a gate length and a threshold voltage of the semiconductor device in the second embodiment. FIG. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device in the second embodiment. FIG. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device in the second embodiment. FIG. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device in the second embodiment. FIG. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device in the second embodiment. It is sectional drawing which shows the manufacturing process of the conventional semiconductor device. It is sectional drawing which shows the manufacturing process of the conventional semiconductor device. It is sectional drawing which shows the manufacturing process of the conventional semiconductor device. It is sectional drawing which shows the manufacturing process of the conventional semiconductor device.

Explanation of symbols

1, 21, 41 Silicon substrate 2, 22, 42 Diffusion layer 3, 3 ', 23, 23', 43, 43 'Element isolation region 4, 4', 24, 24 ', 43, 43' Source / drain region 5 , 5 ', 25, 25', 51, 51 'Extension regions 6, 26, 44 Silicon oxide films 7, 27, 45 High dielectric constant insulating films 8, 28, 50 Gate electrodes 9, 29, 53 Side walls 10, 30 Interlayer insulating film 11, 31 Contact 12, 32 Wiring layer 17, 17 ', 37, 37', 52, 52 'Hello layer

Claims (12)

An oxide film containing silicon formed on a semiconductor substrate;
A high dielectric constant insulating film formed on the oxide film containing silicon;
A semiconductor device having a gate electrode formed on the high dielectric constant insulating film,
2. A semiconductor device according to claim 1, wherein a dimension in the width direction of the high dielectric constant insulating film is larger than a dimension in the width direction of the gate electrode.   The semiconductor device according to claim 1, wherein a difference between a dimension in the width direction of the high dielectric constant insulating film and a dimension in the width direction of the gate electrode is in a range of 5 nm to 60 nm. An oxide film containing silicon formed on a semiconductor substrate;
A high dielectric constant insulating film formed on the oxide film containing silicon;
A semiconductor device having a gate electrode formed on the high dielectric constant insulating film,
The cross-sectional shape of the high dielectric constant insulating film has a tapered shape in which the dimension in the width direction increases as it approaches the oxide film containing silicon, and the portion where the high dielectric constant insulating film is in contact with the oxide film containing silicon The semiconductor device according to claim 1, wherein a dimension in the width direction of the high dielectric constant insulating film is larger than a dimension in the width direction of the gate electrode.   2. The high dielectric constant insulating film is a film made of at least one material selected from the group consisting of hafnium oxide, titanium oxide, zirconium oxide, lanthanum oxide, tantalum oxide, and aluminum oxide. The semiconductor device according to any one of 1 to 3.   5. The semiconductor device according to claim 1, wherein the oxide film containing silicon is one film selected from the group consisting of a silicon oxide film, a silicon oxynitride film, and a silicate film. Forming an oxide film containing silicon on a semiconductor substrate on which a diffusion layer and an element isolation region are formed;
Forming a high dielectric constant insulating film on the oxide film containing silicon;
Forming a gate electrode material on the high dielectric constant insulating film;
Forming a hard mask on the gate electrode material;
Forming a gate electrode by dry etching the gate electrode material using the hard mask, and changing the whole of the high dielectric constant insulating film into a damaged layer by the dry etching;
Removing the damaged layer by wet etching;
Injecting impurities into the semiconductor substrate using the high dielectric constant insulating film as a mask to form extension regions;
Using the high dielectric constant insulating film as a mask, injecting an impurity of a type opposite to the extension region into the semiconductor substrate to form a halo layer,
Etching in the direction of the side wall of the gate electrode in the step of forming the gate electrode makes the dimension in the width direction of the gate electrode smaller than the dimension in the width direction of the high dielectric constant insulating film. A method for manufacturing a semiconductor device. Forming an oxide film containing silicon on a semiconductor substrate on which a diffusion layer and an element isolation region are formed;
Forming a high dielectric constant insulating film on the oxide film containing silicon;
Forming a gate electrode material on the high dielectric constant insulating film;
Forming a hard mask on the gate electrode material;
Forming a gate electrode by dry etching of the gate electrode material using the hard mask;
Dry etching the high dielectric constant insulating film using the hard mask, removing the high dielectric constant insulating film leaving only a damaged layer formed on the high dielectric constant insulating film by the dry etching;
Removing the damaged layer by wet etching;
Injecting impurities into the semiconductor substrate using the high dielectric constant insulating film as a mask to form extension regions;
Using the high dielectric constant insulating film as a mask, injecting an impurity of a type opposite to the extension region into the semiconductor substrate to form a halo layer,
Etching in the direction of the side wall of the gate electrode in the step of forming the gate electrode makes the dimension in the width direction of the gate electrode smaller than the dimension in the width direction of the high dielectric constant insulating film. A method for manufacturing a semiconductor device. Forming an oxide film containing silicon on a semiconductor substrate on which a diffusion layer and an element isolation region are formed;
Forming a high dielectric constant insulating film on the oxide film containing silicon;
Forming a gate electrode material on the high dielectric constant insulating film;
Forming a hard mask on the gate electrode material;
Forming a gate electrode by dry etching the gate electrode material using the hard mask, and changing the whole of the high dielectric constant insulating film into a damaged layer by the dry etching;
Removing the damaged layer by wet etching;
Injecting impurities into the semiconductor substrate using the high dielectric constant insulating film as a mask to form extension regions;
Using the high dielectric constant insulating film as a mask, injecting an impurity of a type opposite to the extension region into the semiconductor substrate to form a halo layer,
The cross-sectional shape of the high dielectric constant insulating film is obtained by performing etching in the direction of the side wall of the gate electrode in the step of forming the gate electrode and changing the amount of damage in the film thickness direction of the high dielectric constant insulating film. Has a taper shape in which the dimension in the width direction increases as it approaches the oxide film containing silicon, and in the width direction of the high dielectric constant insulation film in a portion where the high dielectric constant insulation film is in contact with the oxide film containing silicon A method for manufacturing a semiconductor device, characterized in that a dimension is larger than a dimension in a width direction of the gate electrode.   9. The method of manufacturing a semiconductor device according to claim 8, wherein the amount of damage given in the film thickness direction of the high dielectric constant insulating film is changed by adjusting at least one of an etching time and a plasma power density in the step of forming the gate electrode. . Forming an oxide film containing silicon on a semiconductor substrate on which a diffusion layer and an element isolation region are formed;
Forming a high dielectric constant insulating film on the oxide film containing silicon;
Forming a gate electrode material on the high dielectric constant insulating film;
Forming a hard mask on the gate electrode material;
Forming a gate electrode by dry etching of the gate electrode material using the hard mask;
Dry etching the high dielectric constant insulating film using the hard mask, removing the high dielectric constant insulating film leaving only a damaged layer formed on the high dielectric constant insulating film by the dry etching;
Removing the damaged layer by wet etching;
Injecting impurities into the semiconductor substrate using the high dielectric constant insulating film as a mask to form extension regions;
Using the high dielectric constant insulating film as a mask, injecting an impurity of a type opposite to the extension region into the semiconductor substrate to form a halo layer,
In the step of forming the gate electrode, etching is performed in the direction of the side wall of the gate electrode, and in the step of dry etching the high dielectric constant insulating film, the cross-sectional shape of the high dielectric constant insulating film is oxidized with silicon. By forming a taper shape in which the dimension in the width direction increases as approaching the film, the dimension in the width direction of the high dielectric constant insulating film in the portion where the high dielectric constant insulating film is in contact with the oxide film containing silicon is the gate electrode. A method of manufacturing a semiconductor device, wherein the size is larger than the dimension in the width direction. The dry etching is performed using at least one gas selected from the group consisting of BCl ₃ , Cl ₂ , HBr, CF ₄ , O ₂ , Ar, N ₂ and He. The manufacturing method of the semiconductor device as described in 2. above.   The method of manufacturing a semiconductor device according to claim 6, wherein the wet etching is performed using a DHF solution or a BHF solution.

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