JP2001274384A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device with high reliability for preventing breakdown of a gate insulating film. SOLUTION: A semiconductor device includes at least a first main electrode region 3 of a second electric conductivity type located on an upper part of a main semiconductor region 2 of a first electric conductivity type, a second main electrode region 4, a channel region 5, a gate oxide film 6 located on the channel region 5, a high-permittivity gate insulating layer 7 located on the gate oxide film 6 and having a relative permitting of 10 or more, and a control electrode 8 located on the high permittivity gate insulating layer 7. The control electrode 8 has a side face 12 located substantially vertical to the main semiconductor region 2, a lower side face 11 including a central part 9 located substantially vertical to the side face 12, and a corner 10 intersecting with the side face 12 having a given upward inclination to the central part 9. The thickness of film of the gate oxide film 6 located under the corner 10 of the control electrode 8 is thicker than that of the gate oxide film 6 located under the central part 9 of the gate electrode 8.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a MIS (metal-insulating film semiconductor structure) transistor and a method of manufacturing the same. More particularly, in a damascene gate transistor, a thin gate oxide film with a gate bird's beak is formed and used as a buffer film between a semiconductor and a high dielectric constant film without peeling,
The present invention relates to a technique for preventing a transistor from deteriorating in reliability due to concentration of an electric field at a gate end.

[0002]

2. Description of the Related Art In recent years, gate insulating films have been converted to oxide films.
In a high-performance transistor having a thickness of 0 nm or less, application of a high-dielectric-constant gate insulating film such as tantalum oxide (Ta ₂ O ₅ ) is being studied in order to reduce a gate (tunnel) leakage current. However, since a high dielectric constant gate insulating film is generally vulnerable to heat, a damascene gate process for avoiding this is disclosed in Japanese Patent Application Laid-Open No. H11-74508.

FIG. 5 is a sectional view showing a structure of a transistor having a high dielectric constant gate insulating film manufactured by a damascene gate process according to the prior art. As shown in FIG. 5, a p-type well region 52 separated by a trench isolation region (STI) 70 is formed above a semiconductor substrate 51.
Is arranged. Above the well region 52, an n-type source region 53 and an n-type drain region 54 are arranged apart from each other, and a channel region 55 is arranged therebetween. A gate oxide film 56 on the channel region 55;
A high dielectric constant gate insulating film 57 is sequentially disposed, and a gate electrode 58 is disposed thereon. The gate electrode has a lower surface 6
1 and titanium nitride (TiN) disposed on side surface 62
And a tungsten film 58a embedded in the barrier gate electrode 58b. On the main semiconductor region 52 other than the channel region 55, a dummy gate thermal oxide film 64 and a silicon oxide film 71 are sequentially arranged. On the silicon oxide film 71, a silicon nitride film 72 is disposed on the outer periphery of the gate electrode 58, and a first interlayer insulating film 73 is disposed on the outer periphery thereof. These (58, 72, 7
3) A second interlayer insulating film 74 is disposed on the upper surface, and a wiring 75 is disposed thereon. The wiring 75 is in contact with the source region 53, the drain region 54, and the gate electrode 58, respectively.

FIGS. 6A to 7F are main process cross-sectional views showing a method of manufacturing the transistor shown in FIG. First, as shown in FIG. 6A, a well region 52 separated by STI 70 is formed on a semiconductor substrate 51, and a dummy gate oxide film 64 is formed on the well region 52.
To form Next, as shown in FIG. 6B, a dummy gate electrode 65 having the same planar shape as the gate electrode 58 is formed, and a silicon oxide film 71 is deposited on the entire surface. Using the residue of the dummy gate electrode 65 and the silicon nitride film 72, the source region 53 and the drain region 54 having the LDD structure are formed. A first interlayer insulating film 73 is deposited on the entire surface. Next, as shown in FIG.
nical Polishing: chemical mechanical polishing) to expose the dummy gate electrode 65. Next, as shown in FIG. 7D, the dummy gate electrode 6 is wet-etched.
5 is removed, and boron is diffused above the well region 52 to form a p-type channel region 55. Next, FIG.
As shown in (1), the silicon oxide film 71 and the dummy gate oxide film 64 are selectively removed by wet etching to form a trench exposing the channel region 55. Next, as shown in FIG. 7F, a gate oxide film 56 serving as a buffer film is formed on the channel region 55 by thermal oxidation, and a high dielectric constant gate insulating film 57 made of tantalum oxide is formed thereon. accumulate. TiN 58b is deposited on the entire surface, and a tungsten film 58a is further deposited. An etch bag is performed to form a gate electrode 58. Then, by forming the second interlayer insulating film 74 and the wiring 75 by an existing method, the transistor shown in FIG. 5 can be formed.

[0005]

As shown in FIG. 7E, a silicon oxide film 71 and a dummy gate oxide film 64 are provided.
Is removed by wet etching, the etching proceeds isotropically. Therefore, the dummy gate oxide film 71 and the silicon oxide film 64 are side-etched at the bottom of the groove, and a depression is formed below the silicon nitride film 72. When the combined thickness of the gate oxide film 56 and the high dielectric constant gate insulating film 57 is smaller than the combined thickness of the dummy gate oxide film 64 and the silicon oxide film 71, the barrier gate electrode 23 enters this recess, Barrier gate electrode 2
Needle-like projections are formed on 3. Since the radius of curvature of the projection is small, an electric field concentrates on the projection during the operation of the transistor. Therefore, the gate oxide film around the protrusion may be destroyed, and the reliability of the device may be reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art, and an object of the present invention is to provide a semiconductor device having high reliability, which prevents a gate insulating film from being destroyed, and a method of manufacturing the same. It is to be.

It is another object of the present invention to provide a semiconductor device in which an electric field is not concentrated on a corner portion of a gate electrode, and a method of manufacturing the same.

Another object of the present invention is to prevent the gate insulating film from being destroyed, to have high reliability, and to increase the drive current.
An object of the present invention is to provide a semiconductor device having a small off-leak current and a method for manufacturing the same.

[0009]

In order to achieve the above object, a first feature of the present invention is a semiconductor substrate, a first conductive type main semiconductor region disposed on the semiconductor substrate, and a main semiconductor region. A first main electrode region of a second conductivity type disposed above the main semiconductor region; a second main electrode region of a second conductivity type disposed above the main semiconductor region so as to be separated from the first main electrode region; A channel region disposed adjacent to the first main electrode region and the second main electrode region above the region; a gate oxide film disposed over the channel region; A high-permittivity gate insulating film having a dielectric constant of 10 or more, and being disposed on the high-permittivity gate insulating film and being applied with a voltage different from that of the channel region, between the first main electrode region and the second main electrode region; And a control electrode for controlling the flow of carriers of the semiconductor device. It is when. The control electrode has a side surface arranged substantially perpendicular to the semiconductor substrate, a central portion arranged substantially perpendicular to the side surface, and a predetermined upward inclination with respect to the central portion, and the side surface has And a lower surface composed of intersecting corner portions.

[0010] Here, the first conductivity type and the second conductivity type indicate differences in the types of impurities contained in the semiconductor. For example,
Silicon containing impurities such as phosphorus, arsenic, and antimony is n-type (conductive type) silicon, and silicon containing impurities such as boron and indium is p-type (conductive type) silicon. In a semiconductor substrate having a plurality of transistors, a transistor type arranged in the “main semiconductor region” is determined by the conductivity type of the “main semiconductor region”. For example, when the first conductivity type is n-type / p-type, the MIS transistors arranged in the main semiconductor region are p-channel type / n-channel type transistors, respectively. Further, if the conductivity type of the channel region is the first conductivity type / second conductivity type, the MIS transistors are enhanced type / depletion type transistors, respectively. The “high dielectric constant gate insulating film having a relative dielectric constant of 10 or more” is intended to exclude insulating films such as an oxide film, a nitride film, and an oxynitride film having a relative dielectric constant of 10 or less.

According to a first feature of the present invention, the side surface and the lower surface of the control electrode intersect via a corner portion having an upward slope with respect to the central portion. Therefore, the corner portion does not have a sharp shape. If the angle of inclination of the corner is not constant, the corner has a large radius of curvature. Therefore, when a voltage different from that of the channel region is applied to the control electrode, the electric field does not concentrate on the corners of the control electrode. Since the gate oxide film or the high dielectric constant gate insulating film located below the corner portion can be prevented from being broken, the reliability of the device is improved.

In the first feature of the present invention, the outer peripheral portion of the lower surface of the gate oxide film located below the corner portion of the control electrode is located at a lower portion than the central portion of the lower surface of the gate oxide film located below the central portion of the control electrode. It is desirable to have a predetermined downward slope. The thickness of the gate oxide film located below the corner portion of the control electrode can be formed larger than the thickness of the gate oxide film located below the central portion of the control electrode. Since the distance until the lines of electric force emitted from the corners reach the channel can be increased, the electric field concentration on the corners can be further reduced.

The high dielectric constant gate insulating film is made of one or more of a high dielectric constant oxide selected from hafnium oxide, titanium oxide, tantalum oxide, zirconium oxide, and zirconium silicon oxide. It is desirable. Since the dielectric constant of the gate insulating film can be increased, the physical thickness of the gate insulating film can be increased while keeping the electrical insulating film constant. That is, leakage current between the gate electrode and the channel region of the transistor can be reduced.

Furthermore, the channel region is preferably an impurity semiconductor region containing indium or antimony. By adding a heavy element such as indium or antimony, a channel region having a sharp impurity profile which is less affected by heat treatment can be obtained.

A second feature of the present invention is that (1) a first step of forming a first conductivity type main semiconductor region on a semiconductor substrate, and (2) formation of a gate oxide film on the main semiconductor region. (3) a side surface disposed substantially perpendicular to the semiconductor substrate on the gate oxide film, and a lower surface substantially perpendicular to the side surface and in contact with the gate oxide film. And (4) performing a thermal oxidation process to selectively oxidize a corner portion of the lower surface of the dummy gate electrode, which intersects the side surface, among the side surfaces and the lower surface of the dummy gate electrode. And (5) a fifth step of diffusing an impurity of the second conductivity type above the main semiconductor region using the dummy gate electrode as a mask to form a first main electrode region;
(6) Using the dummy gate electrode as a mask, the second gate electrode is located above the main semiconductor region and separated from the first main electrode region.
A sixth step of diffusing conductivity type impurities to form a second main electrode region, (7) a seventh step of depositing an interlayer insulating film on the main semiconductor region around the dummy gate electrode, and (8) An eighth step of selectively removing the dummy gate electrode to form a trench in which the gate oxide film is exposed, and (9) a dielectric constant of 10
A semiconductor having at least a ninth step of uniformly depositing the above-described high dielectric constant gate insulating film on a gate oxide film and (10) a tenth step of forming a gate electrode on the high dielectric constant gate insulating film This is a method of manufacturing the device. Here, the seventh step may include a step of depositing an interlayer insulating film on the entire surface and a step of performing a planarization process by CMP (chemical mechanical polishing) until the dummy gate electrode is exposed.

According to the second feature of the present invention, the corner portion of the dummy gate electrode is selectively thermally oxidized to make the oxidized corner portion a part of the gate oxide film. The corner portions that have been substantially perpendicular to each other can have an upward slope with respect to the central portion of the lower surface. Therefore, the corner portion does not have a sharp shape. If the angle of inclination of the corner portion is not constant, the corner portion will have a large radius of curvature. The trench formed by selectively removing the dummy gate electrode has a side surface substantially perpendicular to the semiconductor substrate and a bottom surface on which the gate oxide film is exposed. The bottom surface also has a central portion disposed substantially perpendicular to the side surface, and a corner portion having an upward inclination with respect to the central portion and intersecting the side surface. By uniformly forming the high dielectric constant gate insulating film on the bottom surface (gate oxide film) of the groove, the upper surface of the high dielectric constant gate oxide film can have the same shape as the shape of the bottom surface of the groove. . By forming a control electrode on the high dielectric constant gate insulating film and filling back the groove, the control electrode has a lower surface having the same shape as the bottom surface of the groove, and a side surface having the same shape as the side surface of the groove. Will have. That is, the control electrode has a side surface arranged substantially perpendicular to the semiconductor substrate, a central portion arranged substantially perpendicular to the side surface, and a predetermined upward inclination with respect to the central portion. , And a lower surface composed of a corner portion intersecting with the side surface.

According to a second feature of the present invention, between the first step and the second step, (1) a first step of forming a sacrificial oxide film on the main semiconductor region; It is preferable that the method further includes a second step of implanting the upper part of the semiconductor region and (3) a third step of removing the sacrificial oxide film. Here, the conductivity type of the impurity ions may be either the first conductivity type or the second conductivity type. Furthermore, the second
Preferably, the step is a step of implanting indium ions or antimony ions into the upper portion of the main semiconductor region a plurality of times under different implantation conditions. By adding a heavy element such as indium or antimony, a channel layer in which a change in impurity concentration is small due to a heat treatment accompanying the formation of the first main electrode region and the second main electrode region thereafter can be formed. Therefore, since the profile of the channel impurity can be kept steep, a transistor with a large drive current and a small off-leakage current can be obtained.

Further, between the third step and the fourth step, isotropic etching is performed to selectively expose the exposed gate oxide film and the gate oxide film located under the corner of the dummy gate electrode. The method further includes a step of exposing the semiconductor substrate by removing the semiconductor substrate. In the fourth step, not only the corner portion of the dummy gate electrode but also the exposed semiconductor substrate is oxidized by the thermal oxidation treatment, so that the semiconductor substrate is exposed from the gate oxide film. It is desirable to form a thick post-oxide film. The corner portion is exposed by removing the gate oxide film located below the corner portion. By performing the thermal oxidation with the corners exposed, the corners can be easily thermally oxidized. Further, since the post-oxide film thicker than the gate oxide film is formed under the corner portion, the post-oxide film formed under the corner portion of the control electrode is formed under the central portion of the control electrode. It is thicker than an oxide film. Therefore, it is possible to increase the distance until the electric lines of force emitted from the corner reach the channel part,
It is possible to further reduce the electric field concentration on the corner portion.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. In the description of the drawings, parts similar to those of the related art are denoted by similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the width of the layers, the ratio of the thickness of each layer, and the like are different from actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. In addition, it goes without saying that the drawings include portions having different dimensional relationships and ratios.

FIG. 1 is a sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention. As shown in FIG. 1, a semiconductor device according to an embodiment of the present invention includes a semiconductor substrate 1.
And a first conductive type main semiconductor region 2 disposed on the semiconductor substrate 1 and a second conductive type main semiconductor region 2 disposed on the main semiconductor region 2.
A first main electrode region 3 of a conductivity type, a second main electrode region 4 of a second conductivity type disposed above the main semiconductor region 2 and separated from the first main electrode region 3, and an upper portion of the main semiconductor region 2 A channel region 5 disposed adjacent to the first main electrode region 3 and the second main electrode region 4, a gate oxide film 6 disposed on the channel region 5, and disposed on the gate oxide film 6. A high dielectric constant gate insulating film 7 having a relative dielectric constant of 10 or more; and a first main electrode region 3 which is disposed on the high dielectric constant gate insulating film 7 and is applied with a potential different from that of the channel region 5. MIS (Metal Insula) having at least a control electrode (gate electrode) 8 for controlling the flow of carriers between the second main electrode regions 4
torSemiconductor type field effect transistor (MISF)
ET). The gate electrode 8 has a side surface 12 disposed substantially perpendicular to the semiconductor substrate 1, a central portion 9 disposed substantially perpendicular to the side surface 12, and a predetermined upward inclination with respect to the central portion 9. And a lower surface 11 composed of a corner portion 10 intersecting with the side surface 12. Gate oxide film 6 located below corner portion 10 of gate electrode 8
Has a predetermined downward inclination with respect to the central portion of the lower surface of gate oxide film 6 located below central portion 9 of gate electrode 8. Therefore, the thickness of gate oxide film 6 located below corner portion 10 of gate electrode 8 is larger than the thickness of gate oxide film 6 located below central portion 9 of gate electrode 8.

Here, the first conductivity type / second conductivity type are p-type / n-type, respectively, and the semiconductor substrate 1 is a single crystal silicon substrate. Therefore, the MISFET is an n-channel type transistor arranged on the p-type main semiconductor region 2. The MISFET has a first conductivity type (p
(Type) channel region 5. Further, a high dielectric constant gate insulating film having a relative dielectric constant of 10 or more is an insulating film other than an insulating film such as an oxide film, a nitride film, and an oxynitride film having a relative dielectric constant of 10 or less.
Hereinafter, the main semiconductor region 2 is defined as a well region. The first main electrode region 3 and the second main electrode region are referred to as a source region 3 and a drain region 4, respectively.

In the well region 2, 4 × 10 ¹⁵ / c
m- ³ boron (B) is impregnated. Also, wel
The l region 2 is separated from other elements on the silicon substrate 1 by a trench isolation region (STI: Shallow Trench Isolation) 20 formed in the silicon substrate 1.
The STI 20 is made of an insulator buried in a trench. The channel region 5 is a p-type impurity semiconductor region impregnated with indium (In) for controlling the threshold voltage of the transistor. The concentration distribution of indium in the depth direction is as steep as the conventional one or more. The source region 3 and the drain region 4 are n-type impurity semiconductor regions impregnated with arsenic (As).
The source region 3 and the drain region 4 have an LDD structure. That is, the n ⁻ source region 3 a and the n ⁻ drain region 4 a having a low impurity concentration are arranged in a region adjacent to the channel region 5, and the n ⁺ source region 3 b having a high impurity concentration is adjacent to the n ⁻ regions (3 a, 4 a). And n ⁺ drain region 4b.

The gate oxide film 6 disposed on the channel region 5 is also disposed on the source region 3 and the drain region 4. The thickness of the gate oxide film 6 is
1. In the thinnest part located below the central part 9 of 1.
It is about 0 nm and about 3 nm at the thickest part. The high dielectric constant gate insulating film 7 is made of tantalum oxide (Ta ₂ O ₅ ) having a thickness of 5 nm. Here, when the high dielectric constant gate insulating film 8 is directly disposed on the channel region 5, a level is formed at the interface between the high dielectric constant gate insulating film 7 and the channel region 5. By arranging the gate oxide film 6 at this interface, the formation of this interface state can be avoided. That is, the gate oxide film 6 plays the role of a buffer film. The gate electrode 8 includes a U-shaped barrier gate electrode 8b disposed on the lower surface 11 and the side surface 12, and
And a tungsten film 8a disposed inside the barrier gate electrode 8b. The barrier gate electrode 8b has a thickness of 10
nm of a titanium nitride film (TiN film). On the source region 3 and the drain region 4, a 5-nm-thick silicon oxide film 21 is arranged via a gate oxide film 6. The silicon oxide film 21 is also disposed on the side surface 12 of the barrier gate electrode 8b and the side surface of the high dielectric constant gate insulating film 7. On the outer periphery of the silicon oxide film 6, a silicon nitride film 22 is arranged. On the outer periphery of the silicon nitride film 22, a first interlayer insulating film 23 made of a SiO ₂ film is arranged. On the gate electrode 8, the silicon oxide film 21, the silicon nitride film 22, and the first interlayer insulating film 23,
_{A second} interlayer insulating film 24 made of two films is arranged. On the second interlayer insulating film 24, wirings 25 having a predetermined pattern are arranged for the source region 3, the drain region 4, and the gate electrode 8, respectively. Wiring 25
Are also arranged in contact holes penetrating the insulating films (24, 23, 21, 6) and are connected to the respective regions (3, 4) and the gate electrode 8.

When a predetermined positive voltage is applied to the gate electrode 8 with respect to the channel region 5, an electric field is generated from the gate electrode 8 toward the upper portion of the channel region 5. Then, a depletion layer is formed above p-type channel region 5. When the applied voltage is further increased, an n-type inversion channel layer is formed above the channel region 5, and the source region 3 and the drain region 4 become conductive. That is, the MISFET is turned on. At this time, lines of electric force are emitted from the gate electrode 8, pass through the high dielectric constant gate insulating film 7 and the gate oxide film 6, and terminate in the channel region 5.

A method of manufacturing a MISFET having such a configuration will be described with reference to FIGS. 2 (a) to 4 (i). 2A to 4I are main process cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

(1) First, a silicon substrate 1 impregnated with boron (B) at 4 × 10 ¹⁵ / cm ⁻³ is prepared.
Instead of the silicon substrate 1, a so-called epitaxial silicon substrate having a p-type epitaxial silicon layer grown on an insulating substrate such as a silicon substrate or sapphire may be prepared. A resist pattern is selectively formed on the element formation region 2, and RIE (reactive ion etching) is performed using the resist pattern as a mask. A trench is formed in the element isolation region of the substrate 1. An insulator such as SiO ₂ is buried in the trench to form the STI 20. Then, a thermal oxidation process is performed to form a sacrificial oxide film 14 having a thickness of about 3 nm on the surface of the element formation region 2. A resist pattern having a window in the element formation region 2 is formed by PEP, and B ions are selectively ion-implanted twice using the resist pattern as a mask. The ion acceleration energy and ion implantation surface density are 500 KeV, respectively.
3 × 10 ¹³ / cm ⁻² and 300 KeV, 1.5 ×
It is 10 ¹² pieces / cm ⁻² . Further, using the same resist pattern as a mask, the ion acceleration energy and the ion implantation surface density are 10 KeV and 3 × 10 ¹² / cm.
^Under the condition of ⁻² , B ions are selectively implanted. RTA (Rapid Therma) at 1000 ° C. for about 10 seconds.
l Aneal) to activate the implanted B ions.
A p-type well region 2 is formed in the element formation region, and we
A channel region 5 is formed above the II region 2. FIG. 2A shows a state in which the above steps have been completed.

(2) Next, as shown in FIG. 2B, the sacrificial oxide film 14 damaged by the ion implantation is removed by wet etching.

(3) Next, RTO (Rapid Thermal Oxid
), and a film thickness of 1.0 n is formed on the well region 2.
A gate oxide film 5 of about m is formed. An amorphous silicon film is deposited to a thickness of about 300 nm, and a resist pattern is selectively formed in a region where the dummy gate electrode 15 is to be formed by PEP. Using this resist pattern as a mask, RIE is performed to selectively remove the amorphous silicon film. The resist is removed to form a dummy gate electrode 15 as shown in FIG. Here, the dummy gate electrode 15 is formed of an amorphous silicon film, but may be formed of a single crystal silicon film or a polycrystalline silicon film. Dummy gate electrode 15 has lower surface 16 in contact with gate oxide film 6 and side surface 17 intersecting the lower surface 16 almost perpendicularly.

(4) Next, wet etching is performed.
The gate oxide film 6 damaged by RIE of the amorphous silicon film is removed. However, as shown in FIG. 3D, since the etching is isotropic, not only the exposed gate oxide film 6 is removed, but also the dummy gate electrode 1 is removed.
The gate oxide film 6 under 5 is also side-etched. A corner portion 10 where the lower surface 16 and the side surface 17 of the dummy gate electrode 15 intersect is exposed.

(5) Next, thermal oxidation is performed again in an oxygen atmosphere at 850 ° C., for example, to thermally oxidize the exposed silicon substrate 1 by about 3 nm. At the same time, the corner portion 10 of the dummy gate electrode 15 is also thermally oxidized. FIG.
As shown in (e), a post-oxide film 6 ′ is formed on the corner portion 10 and the exposed silicon substrate 1 following the gate oxide film 6 left under the central portion 16 of the dummy gate electrode 15. Is done. The post-oxide film 6 'is formed thicker than the gate oxide film 6, and the corner portion 10 of the dummy gate electrode 15 is also thermally oxidized.
The lower surface 16 has a central portion 9 arranged substantially perpendicular to the side surface 17 and a corner portion 10 inclined upwardly with respect to the central portion 9 and intersecting the side surface 17.

(6) Next, the well region formed of PEP
Resist pattern having window in region 2 and dummy gate electrode
Arsenic (As) ions can be selectively removed using pole 15 as a mask.
Ions are implanted into the upper part of the well region 2. Ion acceleration
Energy and ion implantation area density are 10 KeV, 3x
10¹⁴Pieces / cm^-2It is. 850 ° C, about 15 seconds
RTA is performed to activate the implanted As ions. n⁻
Source regions 3a and n ⁻Drain region 4a is formed simultaneously
Is done. Then, the silicon oxide film 21 is formed by CVD.
Is deposited to about 5 nm, and the silicon nitride film 22 is deposited to about 40 nm.
Deposits every time. R using the silicon oxide film 21 as a stopper
The IE is performed, and the silicon nitride film 22 is etched back.
Silicon nitride disposed on the periphery of dummy gate electrode 15
A residue of the film 22 is formed. Again, window in well area 2
Resist pattern, dummy gate electrode 15, and
Arsenic (A) using the residue of the silicon nitride film 22 as a mask
s) Ions are selectively added to the top of the well region 2
inject. Ion acceleration energy and ion implantation surface density
The degree is 30 KeV, 5x10^FifteenPieces / cm^-2It is.
Perform RTA at 900 ° C. for about 10 seconds, and
Activate ON. By CVD method, SiO₂40 membranes
The first interlayer insulating film 23 is formed by depositing about 0 nm. 7
Densification for about 30 minutes in a nitrogen atmosphere at 50 ° C
I do. n⁺Source regions 3b and n⁺Drain region 4b
Are simultaneously formed. FIG. 3 shows a state in which the above steps are completed.
(F).

(7) Next, a flattening process is performed by CMP to expose the dummy gate electrode 15 at the same time as shown in FIG.

(8) Next, as shown in FIG.
The trench part 26 is formed by selectively removing the dummy gate electrode 15 by a DE (chemical dry etching) method or a wet etching method using a KOH solution. The gate oxide film 6 and the post-oxide film 6 'are exposed on the bottom surface of the groove 26. Here, the exposed gate oxide film 6 and post-oxide film 6 'do not need to be peeled off since they are not damaged by RIE or the like as in the conventional example. In addition, in FIG. 2A, since indium for adjusting the channel threshold voltage is already diffused above the well region 2, the gate insulating film 6 and the post-oxide film 6 'are exposed to ion implantation. There is no.

(9) Next, tantalum oxide (Ta ₂ O ₅ ) is uniformly deposited on the bottom surface of the trench 26 to form a high dielectric constant gate insulating film 7 having a uniform thickness of about 5 nm. Form. Using a long sputtering method, a titanium nitride film 8b having a thickness of about 10 nm is deposited on the entire surface. A tungsten film 8a is deposited on the entire surface. Then, CMP using the first interlayer insulating film 23 as a stopper is performed to etch back the titanium nitride film 8b and the tungsten film 8a. As shown in FIG. 4I, the tungsten film 8a and the barrier gate electrode 8
A gate electrode 8 to be b is formed.

(10) Finally, a second interlayer insulating film 24 made of a silicon oxide film is deposited on the entire surface by using the CVD method. By PEP, a resist pattern having openings on the n ⁺ source region 3b, the n ⁺ drain region 4b, and the gate electrode 8 is formed. RIE of the insulating film is performed using the resist pattern as a mask. Insulating film (24, 23, 2
1, 6 ′) to form contact holes in which the n ⁺ source region 3b, the n ⁺ drain region 4b, and the gate electrode 8 are exposed. A part of the wiring 25 (contact plug) is buried in the contact hole by the existing contact plug forming method. A wiring 25 made of aluminum is deposited on the entire surface by a sputter method. RIE of aluminum is performed using the resist pattern formed by PEP. On the second interlayer insulating film 24, the wiring 2 connected to the source region 3, the drain region 4, and the gate electrode 8
5 are formed. Through the above steps, the MI shown in FIG.
An SFET can be manufactured.

According to the embodiment of the present invention, the gate electrode 8
Side surface 12 and lower surface 11 intersect via a corner portion 10 having an upward slope with respect to central portion 9. Therefore, the corner portion 10 does not have a sharp shape. If the angle of inclination of the corner portion 10 is not constant, the corner portion 10 has a large radius of curvature. Therefore, when a voltage different from that of the channel region 5 is applied to the gate electrode 8, the electric field does not concentrate on the corner portion 10 of the gate electrode 8. Also, the corner portion 1 of the gate electrode 8
0, the thickness of the post-oxide film 6 ′ is smaller than that of the gate electrode 8.
Is thicker than the thickness of the gate oxide film 6 located below the central portion 9, the electric field applied to the corner portion 10 can be reduced. Therefore, it is possible to avoid destruction of the gate insulating films (6, 7) located below the corner portions 10, so that the reliability of the device is improved.

The presence of the high dielectric constant gate insulating film 7 having a relative dielectric constant of 10 or more can increase the dielectric constant between the channel region 5 and the gate electrode 8. Therefore, on / off control of the transistor can be performed with a low gate voltage. That is, the current driving capability of the transistor can be improved.

Further, by adding a heavy element such as indium or antimony to the channel region 5, it is possible to form a channel layer in which a change in impurity concentration due to a heat treatment accompanying the formation of the source region 3 and the drain region 4 is small. it can. Therefore, since the profile of the channel impurity can be kept steep, the drive current is large,
A transistor with small off-leakage current can be obtained.

(Other Embodiments) As described above, the present invention has been described with reference to one embodiment. However, it should be understood that the description and drawings constituting a part of this disclosure limit the present invention. Absent. From this disclosure, various alternative embodiments, examples, and operation techniques will be apparent to those skilled in the art.

In the embodiment of the present invention, the gate oxide film 6
The post-oxidation film 6 'is subjected to a thermal oxidation treatment in an oxygen atmosphere.
This is a silicon oxide film formed by
It is not specified. For example, RTP (Rppid Ther
mal Process) ₃Silicon based in gas atmosphere
A silicon nitride film formed by direct thermal nitriding
You may.

The high dielectric constant gate insulating film 7 is made of tantalum oxide (tantalum pentoxide: Ta ₂ O ₅ ), but is not limited to this. The high dielectric constant gate insulating film 7 having a relative dielectric constant of 10 or more is formed of hafnium oxide (hafnium oxide: HfO), titanium oxide (titanium dioxide: TiO ₂ ), zirconium oxide (zirconium oxide: ZrO ₂ ), or zirconium silicon oxide (ZrSiO ₄₎ a high dielectric constant oxides such as lead zirconium titanate (PZT), barium strontium titanate (BST), calcium oxide (CaO), beryllium oxide (BeO), or magnesium oxide (MgO) Among them, any one or a plurality of high dielectric constant materials may be used.

Further, the gate electrode 8 is formed of a titanium nitride film (T
iN) formed of a laminated film of 8b and tungsten film 8a, but is not limited thereto. The gate electrode may be formed of a ruthenium (Ru) film. Further, it may be formed of a polycrystalline silicon film to which impurities are added at a high concentration.

Further, although the MISFET having the LDD structure has been described in the embodiment, the impurity is not limited to the low concentration near the channel in the second main electrode region. Further, the silicon nitride film 22 is not formed,
An n ⁻ or n ⁺ single source / single drain structure may be used.

Further, the conductivity type of the impurity added to the channel region 5 is the conductivity type of the source / drain, ie, the second conductivity type.
It may be a conductive type. In this case, a depression-type transistor can be formed. It is desirable that the n-type impurity added to the channel region 5 be antimony (Sb).

As described above, it should be understood that the present invention includes various embodiments and the like not described herein. Accordingly, the present invention is limited only by the matters specifying the invention according to the claims that are reasonable from this disclosure.

[0046]

As described above, according to the present invention, it is possible to provide a highly reliable semiconductor device and a method of manufacturing the same, which prevent the gate insulating film from being destroyed.

Further, according to the present invention, it is possible to provide a semiconductor device in which an electric field is not concentrated at a corner portion of a gate electrode, and a method of manufacturing the same.

Further, according to the present invention, it is possible to provide a semiconductor device which prevents gate insulating film breakdown, has high reliability, has a large drive current, and has a small off-leakage current, and a method for manufacturing the same.

[Brief description of the drawings]

FIG. 1 shows a semiconductor device (MIS) according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view illustrating a configuration of the FET.

FIGS. 2A to 2C are main process cross-sectional views illustrating a method of manufacturing the semiconductor device (MISFET) illustrated in FIG. 1 (part 1).

3 (d) to 3 (f) are main process cross-sectional views illustrating a method of manufacturing the semiconductor device (MISFET) illustrated in FIG. 1 (part 2).

FIGS. 4G to 4I are main process cross-sectional views illustrating a method of manufacturing the semiconductor device (MISFET) illustrated in FIG. 1 (part 3).

FIG. 5 shows a semiconductor device (MISFET) according to the related art.
It is sectional drawing which shows a structure of.

FIGS. 6A to 6C are main process cross-sectional views each showing a method of manufacturing the transistor (MISFET) shown in FIG. 5 (part 1).

7 (d) to 7 (f) are main process cross-sectional views illustrating a method of manufacturing the transistor (MISFET) illustrated in FIG. 5 (part 2).

[Explanation of symbols]

1, 51 semiconductor substrate (silicon substrate) 2, 52 main semiconductor region (well region) 3a, 53a first main electrode region (n ⁻ source region) 3b, 53b first main electrode region (n ⁺ source region) 4a, 54a Second main electrode region (n ^- drain region) 4b, 54b Second main electrode region (n ⁺ drain region) 5, 55 Channel region 6, 56 Gate oxide film 6 'Post oxide film 7, 57 High dielectric constant gate insulating film 8a, 58a Gate electrode (tungsten film) 8b, 58b Gate electrode (barrier gate electrode) 9 Central portion 10 Corner portion 11, 16, 61 Lower surface 12, 17, 62 Side surface 14, 64 Sacrificial oxide film 15, 65 Dummy gate electrode 20 , 70 STI 21, 71 silicon oxide film 22, 72 silicon nitride film 23, 73 first interlayer insulating film 24, 74 second interlayer insulating film 25, 75, wiring 26 groove

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Claims (8)

[Claims] A first conductive type main semiconductor region disposed above the semiconductor substrate; a second conductive type first semiconductor region disposed above the main semiconductor region;
A main electrode region, a second main electrode region of a second conductivity type disposed above the main semiconductor region and spaced apart from the first main electrode region, and a first main electrode region above the main semiconductor region A channel region disposed adjacent to the second main electrode region; a gate oxide film disposed on the channel region; and a relative dielectric constant of 10 or more disposed on the gate oxide film. A high dielectric constant gate insulating film, a side surface disposed on the high dielectric constant gate insulating film, disposed substantially perpendicular to the semiconductor substrate, and disposed substantially perpendicular to the side surface. A central portion and a lower surface having a predetermined upward inclination with respect to the central portion and a corner portion intersecting with the side surface, and the first main electrode is provided by applying a voltage different from that of the channel region. Between the region and the second main electrode region Wherein a and a control electrode for controlling the flow of carriers. 2. A lower peripheral portion of the lower surface of the gate oxide film located below the corner portion of the control electrode, relative to a lower central portion of the gate oxide film located below the central portion of the control electrode. 2. The semiconductor device according to claim 1, wherein the semiconductor device has a predetermined downward inclination. 3. The high dielectric constant gate insulating film is formed of one or more of high dielectric constant oxides selected from hafnium oxide, titanium oxide, tantalum oxide, zirconium oxide, and zirconium silicon oxide. The semiconductor device according to claim 1, wherein: 4. The semiconductor device according to claim 1, wherein said channel region is an impurity semiconductor region containing indium or antimony. 5. A first step of forming a main semiconductor region of a first conductivity type on an upper part of a semiconductor substrate; a second step of forming a gate oxide film on the main semiconductor region; And selectively forming a dummy gate electrode having a side surface substantially perpendicular to the semiconductor substrate and a lower surface substantially perpendicular to the side surface and in contact with the gate oxide film. A third step of performing a thermal oxidation process to selectively oxidize a corner portion of the lower surface that intersects with the side surface, of the side surface and the lower surface of the dummy gate electrode, and masking the dummy gate electrode A fifth step of diffusing impurities of a second conductivity type over the main semiconductor region to form a first main electrode region; and using the dummy gate electrode as a mask, over the main semiconductor region, Previous A sixth step of diffusing an impurity of the second conductivity type at a position separated from the first main electrode region to form a second main electrode region, and an interlayer insulating film on the main semiconductor region around the dummy gate electrode An eighth step of selectively removing the dummy gate electrode to form a groove in which the gate oxide film is exposed, and a high dielectric constant gate insulating film having a relative dielectric constant of 10 or more. A method for manufacturing a semiconductor device, comprising: a ninth step of uniformly depositing a gate electrode on the gate oxide film; and a tenth step of forming a gate electrode on the high dielectric constant gate insulating film. 6. A first step of forming a sacrificial oxide film on the main semiconductor region between the first step and the second step, and a second step of implanting impurity ions into an upper portion of the main semiconductor region.
6. The method according to claim 5, further comprising: a step of removing the sacrificial oxide film. 7. The method according to claim 7, wherein in the second step, indium ions or antimony ions are implanted a plurality of times under different implantation conditions.
7. The method of manufacturing a semiconductor device according to claim 6, wherein the step of implanting the semiconductor device is performed above the main semiconductor region. 8. The method according to claim 8, wherein isotropic etching is performed between the third step and the fourth step to form the gate oxide film located below the exposed gate oxide film and the corner portion of the dummy gate electrode. The method further comprises the step of selectively removing a film and exposing the semiconductor substrate, wherein the fourth step includes exposing not only the corners of the dummy gate electrode but also the thermal gate by a thermal oxidation process. 6. The method of manufacturing a semiconductor device according to claim 5, further comprising the step of oxidizing a semiconductor substrate to form a post-oxide film thicker than the gate oxide film.