JPH0374878A - Manufacturing method of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain an IGFET using a transition metal oxide film especially for a gate insulation film by penetrating the gate insulation film without performing light oxidation and by implanting ion. CONSTITUTION:An SiO2 is provided on the surface of a p-type Si substrate 1 for implanting a channel of BF2. The SiO2 film is eliminated and a tantalum pentoxide 2 is sputtered. Treatment is performed within dry O2 at 800 deg.C and an SiO2 film 3 is formed between the substrate 1 and the tantalum pentoxide 2. Then, a W film 4 is sputtered and a PSG 5 is superposed. The PSG 5 is subjected to patterning and the W film 4 is machined with the PSG 5 as a mask. Then, As ion is implanted, thermal treatment is performed within N2 for producing an n<+> layer 6, and a drain layer is provided in self-aligned manner to a W gate pattern. Further, an interlayer insulation film 7 is superposed and a wiring metal film 8 is provided for completing an FET. With this method, it is possible to form an IGFET without performing light oxidation even if a material with an extremely rapid diffusion of an oxidation seed such as tantalum pentoxide is used as a gate insulation film.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly to a field effect transistor using a transition metal oxide film as a gate insulating film and a method for manufacturing the same. It is.

[Conventional technology]

When manufacturing a field effect transistor using a transition metal oxide film as a gate insulating film, in conventional technology, after processing the gate electrode and gate insulating film.

Immediate oxidation of the substrate or polycrystalline silicon gate surface has been practiced.

[Problem to be solved by the invention]

However, when a material such as tantalum pentoxide, which has extremely fast diffusion of oxidizing species, is applied to the gate insulating film,
) and (b), during the oxidation, the oxidizing species diffuses inward from the exposed part of the gate insulating film at the edge of the gate, oxidizing the semiconductor substrate and gate electrode on that side of the image. A wedge-shaped oxidation is created at the edge of the gate region. This phenomenon is significant when the oxidizing atmosphere contains water vapor. As a result, a problem arises in that the inversion voltage of the channel region of the field effect transistor in the wedge-shaped oxidized portion increases, and the threshold voltage increases. As shown in FIG. 3C, this phenomenon is difficult to completely suppress even when a sidewall oxide film is formed on the sidewall of the gate.

Furthermore, it has been found that when the transition metal oxide that is the gate insulating film is processed at the same time as the gate electrode is processed, leakage current tends to flow through the processed edges. Also, the fourth
As shown in the figure, during the oxidation, the oxidizing species diffuses inward from the exposed part of the gate insulating film at the gate end, oxidizing the semiconductor substrate and gate electrode on the opposite side, and oxidizing the gate region. Produces wedge-shaped oxidation at the ends. This phenomenon is remarkable when water vapor is included in the oxidizing atmosphere, and as a result, problems arise in that the channel region of the field effect transistor where the wedge-shaped oxidation occurs has a high inversion voltage and a high threshold voltage.

[Means to solve the problem]

To solve this problem, implants can be performed by penetrating the gate insulating film without performing so-called light oxidation, or alternatively, after forming the sidewalls, another insulating film can be deposited, and the implant can be performed by penetrating this deposited film. It is appropriate to do so. In this case, the processed edges of the gate electrode and the gate insulating film should never coincide in any process.

Furthermore, in order to solve the above-mentioned problem, oxidation is performed after depositing an insulating film on the side wall in which the diffusion of oxidizing species is slower than that of the insulating film so that the gate insulating film is not exposed during the above-mentioned oxidation.

[Effect]

By leaving the gate insulating film during gate processing, light oxidation becomes unnecessary. Furthermore, when side walls are formed, light oxidation becomes unnecessary by forming a deposited film for implantation. Also, if the leakage current at the processed end is through the gate insulating film.

Since the gate insulating film remains, there is no problem. Furthermore, if the sidewalls are formed, the gate insulating film is processed at the same time as the sidewalls are processed, so the gate structure becomes an offset type and an increase in leakage current can be suppressed.

In addition, by covering the gate insulating film with an insulating film in which the diffusion of oxidizing species is slower than that of the gate insulating film, the concentration of oxidizing species that reach the insulating film when exposed to an oxidizing atmosphere is reduced. Oxidation becomes difficult to progress.

〔Example〕

(Example 1) An example of the method for manufacturing a semiconductor device of the present invention is shown in FIG. 1 using a cross-sectional structure.

After forming 10 nm of silicon dioxide on the surface of the p-type silicon substrate 1, 40 kev, 2. OX 10"Qa-"
After that, this silicon dioxide film is removed and a 20 nm thick film is formed as a gate insulating film.
A tantalum pentoxide film 2 is formed by reactive sputtering.

In this embodiment, reactive sputtering was used to form tantalum pentoxide, but it can also be formed by chemical vapor deposition using a tantalum halide such as tantalum alkoxylate or tantalum chloride or tantalum fluoride as a source gas. Thereafter, heat treatment is performed at 800° C. in a dry oxygen atmosphere. This storm,
Between the silicon substrate 1 and tantalum pentoxide 2, about 2 nm of 5
Ift film 3 is formed. A 300 nm thick tungsten film 4 was formed thereon by sputtering. Furthermore, PSGM 5 was formed on tungsten 4. After this, after patterning the gate electrode and processing the PSG,
Figure 1 (a)
) to obtain the cross-sectional shape shown in 0th order, 5.0X with 40 keys
Arsenic ion implantation of 10"a""! and heat treatment in a nitrogen atmosphere at 900° C. were performed to form an n-type high concentration diffusion layer 6, which became the source and drain regions (b), self-aligned with respect to the tungsten gate batten. was able to form.

Further, an interlayer insulating film 7 was formed, a contact hole was opened, and a wiring metal film 8 was formed to manufacture a field effect transistor (C).

FIG. 2 shows the threshold value (vth) of the device obtained in this example.
) Voltage shift amount and transfer conductance deterioration ΔG m
The stress voltage application time dependence of /G m o is compared with that of a conventional MOSFET with a channel length of 0.3 μm and a gate insulating film of 5 nm silicon dioxide.

When a laminated film of tantalum oxide and silicon dioxide was used, the amount of variation could be suppressed by more than one order of magnitude. As a result, it was found that the characteristics of the device using the present invention were extremely reliable in a device having a channel length of 0.3 μm or less.

(Example 2) FIG. 5 shows a schematic diagram of Example 2.

After forming 10 nm of silicon dioxide in the surface on a p-type silicon substrate, 40 kev, 2. OXIO"am-
After that, this silicon dioxide film is removed, and 20 nm of tantalum pentoxide [2] is formed by reactive sputtering as a gate insulating film within this table. Although reactive sputtering was used to form tantalum oxide, it can also be formed by chemical vapor deposition using tantalum alkoxylate or a tantalum halide such as tantalum chloride or tantalum fluoride as a source gas.After that, it is deposited in a dry oxygen atmosphere at 800°C. After that, a 5ins film 3 of about 2 nm is formed between the silicon substrate 1 and the tantalum pentoxide 2. On top of that, a 5ins film 3 is formed.
A tungsten film 4 of Onm was formed by sputtering. Furthermore, a PSG film 5 was formed on the tungsten 4. After this, the gate electrode is patterned and the PSG is processed, and then the tungsten is processed using the PSG as a mask to obtain the cross-sectional shape shown in Figure 5(a).Next, a PSG film is deposited and the entire surface is etched. and leave the side wall 9 (Fig. 4 (b)
)) At this time, when processing the PSG film, tantalum oxide 2
/0th order to simultaneously process the laminated film of silicon dioxide 3,
Deposit silicon dioxide film 10, 5.0 with 40 keys
Arsenic ion implantation of 1015 cm-'' and heat treatment in a nitrogen atmosphere at 900° C. were performed to form n-type high concentration diffusion N6, forming source and drain regions (FIG. 5(Q)). A field effect transistor was manufactured by forming contact holes, opening contact holes, and forming a wiring metal film 8 (FIG. 5(d)). Comparing the stress voltage application time dependence of the transfer conductance deterioration ΔGm/Gmo with that of a conventional MOSFET with a channel length of 0.3 μm and a gate insulating film of 5 nm silicon dioxide,
As in Example 1, it was found that when a laminated film of tantalum oxide and silicon dioxide was used, the amount of variation could be suppressed by more than an order of magnitude, and the device had excellent reliability. .

(Example 3) By carrying out the manufacturing method shown in the above-mentioned Example 1.2 in two steps, LDD (lightly do
MOS transistors with a peddrain structure can be manufactured.

The am diagram of Example 3 is shown in the 6th rM.

The cross-sectional structure shown in FIG. 6(a) is obtained by the process shown in Example 1. Here, the first diffusion layer 11 is 2, OX l
□ta,,""! Arsenic ions are implanted into the gate pattern using a self-line method. Next, by the method shown in Example 2, a sidewall insulating film 12 is formed on the side border of the gate electrode.
form. At this time, the first step is to simultaneously process the laminated film of tantalum oxide 2/silicon dioxide 3, and then the PSG film 3 is deposited, and arsenic ions are implanted at 5.0XIQ "am-", and the second step is the diffusion layer 14. was formed.

At this time, the amount of ion implantation for forming the diffusion layer in the first stage and the amount of ion implantation in the second stage are LDD (Light
ly Doped Drain) to obtain sufficient characteristics.

(Example 4) Similarly to Example 3, an LDD structure MOSFET can also be manufactured by carrying out the method shown in Example 2 in two steps. This manufacturing process is shown in FIG. 7, and by the manufacturing method shown in Example 2, a new song shape shown in FIG. 7(a) is obtained. The n-type diffusion layer 16 is formed by penetrating the PSG film 15 and implanting arsenic ions of 2.0.times.10.sup.18 x 2 in a self-alignment line along the gate pattern.

Furthermore, a second sidewall insulating film 17 is formed by depositing a PSG film and etching the entire surface. Furthermore, P.S.G.
After 8 stacks of 1 membrane, 5. Arsenic ion implantation is performed at OX 10"■-2. Since this ion implantation amount is set to a higher concentration than the first stage implantation, it is possible to form an LDD structure MOSFET.
By performing heat treatment at 0° C., the diffusion layer profile was optimized as shown in Figure 7(c).

(Example 5) FIG. 8 shows a schematic diagram of Example 5.

After forming an element isolation region 22 on a p-type silicon substrate 21, a 10 nm tantalum pentoxide film 23 is formed as a gate insulating film on the surface of the substrate by reactive sputtering. Although reactive sputtering was used to form tantalum pentoxide in this embodiment, it can also be formed by a chemical vapor deposition method using tantalum alkoxylate or a tantalum halide such as tantalum chloride or tantalum fluoride as a source gas. After that, 80
Silicon substrate 21 is heat-treated in a dry oxygen atmosphere at 0°C.
and tantalum pentoxide 23 with a red meat oxide film 23 of about 5 nm.
' was formed. A silicon dioxide film 10 is placed thereon to prevent the reaction between polycrystalline silicon and tantalum pentoxide 23.
nm 23' was deposited by chemical vapor deposition. A 300 nm thick polycrystalline silicon 24 was formed thereon by a chemical vapor deposition method, and phosphorous treatment was performed to dope the polycrystalline silicon with phosphorus to form a gate electrode. Then, the polycrystalline silicon 24 and tantalum pentoxide 23 were processed to form a gate pattern. The polycrystalline silicon 24 was processed by microwave plasma etching using SF8 gas, and the tantalum pentoxide 23 was processed by reactive sputter etching using CHFs gas.

Then, as the first insulating film.

A silicon dioxide film 25 was formed on the 1100n surface by chemical vapor deposition. The substrate on which the first insulating film is formed is subjected to anisotropic dry etching to remove the insulating film 25 leaving only the side surfaces of the gate. In this structure, when the silicon substrate 21 is oxidized, the gate insulating film is covered with the insulating film formed on the side surfaces, so that no wedge-shaped abnormal oxidation occurs at the end of the gate.

Thereafter, arsenic ion implantation and heat treatment at 950° C. in a nitrogen atmosphere were performed to form an n-type high concentration diffusion layer 27, which was used as a source and drain region. Ion implantation was performed at an accelerating voltage of 80 keV, and could be formed in a self-aligned manner with respect to the polycrystalline silicon pattern.

Further, an interlayer insulating film 30 was formed, a contact hole was opened, and a wiring metal film 31 was formed to manufacture a field effect transistor.

As a result, the threshold voltage of the field effect transistor is 1
．． OV, and other electrical characteristics were also good.

(Example 6) FIG. 9 shows a schematic diagram of Example 2.

In the embodiment of FIG. 5, the oxidation of the sidewall insulating film 17 and the substrate can be replaced by formation of the insulating film by chemical vapor deposition. That is, after the gate is formed, a 30 nm silicon dioxide film 25 is deposited over the entire surface of the substrate by chemical vapor deposition, and ions are implanted to form a diffusion layer in the same manner as in the first embodiment.

(Example 7) By performing the gate sidewall forming process twice in the above-mentioned Example 5, LDD (lightly dop
edrain ) structure can be achieved.

FIG. IO shows a schematic diagram of Example 7.

That is, after processing the gate, first silicon dioxide 29 is deposited and anisotropic dry etching is performed to remove it except for the side surfaces of the gate. After thermally oxidizing the silicon substrate 21, first ion implantation is performed to form a first-stage diffusion layer 211.

Alternatively, as in Example 2, ions may be implanted through the deposited silicon dioxide film.

Further, the deposition of the silicon dioxide film and the anisotropic dry etching are performed again to form a second sidewall silicon dioxide 210 on the side surface of the gate, and after oxidizing the silicon substrate 21,
A second stage diffusion layer 212 is formed by ion implantation. At this time, the first stage diffusion layer 211 is replaced with the second stage diffusion #
By lowering the concentration than 212, an LDL) structure could be formed.

(Embodiment 8) An example in which the gate is replaced with tungsten in the fifth embodiment is schematically shown in FIG.

After forming tantalum pentoxide 23 and performing interfacial oxidation, tungsten 2 and 3 for the gate electrode were formed by sputtering. Tungsten can also be formed by chemical vapor deposition using tungsten fluoride and hydrogen instead of sputtering. Furthermore, a silicon dioxide film 214 was deposited on the surface of the tungsten 213. A gate pattern was formed, and silicon dioxide [214] on tungsten 213, tungsten 213, and tantalum pentoxide 23 were processed. Is silicon dioxide processed with CF4 gas, tungsten with SFe gas, tantalum pentoxide with OH? Processing was performed by reactive sputter etching using cogas, respectively.

Thereafter, a silicon dioxide film 25 was formed on the surface to a thickness of 200 nm. The silicon dioxide formed on the tungsten and the silicon dioxide formed on the sides of the gate were formed by chemical vapor deposition, but in order to prevent oxidation of the tungsten,
Great care must be taken to prevent atmospheric oxygen from entering the reaction vessel. Alternatively, it can be formed by a chemical vapor deposition method using plasma instead of the chemical vapor deposition method.

The substrate on which the insulating film is formed is subjected to anisotropic dry etching to remove the tIA edge film except for the side surfaces of the gate. With this structure, the silicon substrate was oxidized in a mixed gas atmosphere of hydrogen gas and water vapor at 900°C. At this time, since the gate insulating film is covered with the insulating film 25 formed on the side surfaces, no wedge-shaped abnormal oxidation occurs at the end of the gate.

Thereafter, arsenic ions were implanted through the oxide film 26 to form source and drain regions 27. (Embodiment 9) This embodiment is an embodiment in which the transistor of the present invention is applied to a dynamic random access memory consisting of one transistor and l capacitors. FIG. 12 shows the electrical wiring method for the memory array. 324 is one of the transistors shown in Examples 1 to 4, and tungsten is used for the gate electrode. Also,
325 is a capacitor. The gate electrode is connected to one of the word lines 321. Further, one electrode of the transistor is connected to the bit line 322, and the other electrode is connected to one electrode of the capacitor 325. Also, the opposite electrode of the capacitor has a plate potential of 23
Connected to 2.

FIG. 13 schematically shows a cross-sectional structure of an example of this memory cell. Reference numeral 330 indicates a gate insulating film formed by the method shown in Example 1 of the present invention. 326
is one electrode of the capacitor 325 and is connected to the high concentration diffusion layer 27.

The opposite electrode 329 of the capacitor is connected to plate potential 323. Further, the high concentration diffusion layer 328 is connected to the bit line 322. It has been found that the dynamic random access memory configured as described above has extremely excellent functionality. This will be explained below.

As shown in Examples 1 to 8, it was found that the performance of the transistor of the present invention was extremely excellent in the region where the channel length was 0.3 μm or less. Furthermore, the performance of semiconductor memories that use a large amount of these transistors is significantly improved. Figure 14 shows the word line delay time of a memory element formed using the transistors of the present invention and the access time using conventional polycrystalline silicon as a word line. In order to avoid time delays, aluminum wires are wired on word lines, and the signal delay times of word lines of a fixed length of memory elements are compared at constant intervals. It has been found that a delay time of about 1 fold can be obtained when the knee level is 0.2 μm, compared to the conventional technique. This is because the resistance of tungsten can be reduced to less than 1/20th that of polycrystalline silicon, and tungsten has a longer lifespan than aluminum even when a large current density is applied, so access speed can be increased. . Furthermore, the two masks required for connecting the aluminum and word lines can be eliminated. Therefore, if the transistor of the present invention is used in a highly integrated memory device, it will not only increase the reliability of the device, but also increase the access speed by reducing the word line delay, and reduce the number of steps by reducing the number of masks. Effects also occur.

The effects shown below can be obtained not only when applied to dynamic random access memory (DRAM), but also when used as transistors in memory cells such as static random access memory (SRAM), read-only memory (ROM), and nonvolatile memory. This can also be obtained when a transistor is applied.

[Effects of the Invention] By the method of the present invention, in a field effect transistor using a transition metal oxide film as a gate insulating film, a structure in which a wedge-shaped oxide film is not formed at the end of the gate region can be obtained, and the electrical characteristics are improved. We were able to manufacture a good transistor.

In particular, it was possible to manufacture a MOSFET with superior long-term reliability compared to conventional MOSFETs using silicon dioxide as a gate insulating film.

W is a comparison of the long-term reliability of the device shown in Example 1 with a conventional device using silicon dioxide as the gate insulating film.
. Figures 3 and 4 4 pieces l...p-type Si substrate, 2...
...Tantalum pentoxide, 3...Silicon dioxide (interface oxide film), 4...Tungsten electrode, 5...PSG film, 5...Side wall protection insulating film, 6...N-type high concentration diffusion Layer, 7... Interlayer insulating film, 8... Metal wiring, 9... Sidewall insulating film, 10.15... First PSA film, 11.1
6... First n-type high concentration diffusion layer, 12... First sidewall insulating film, 13.18... Second PSG[,14,1
9... Second n-type high concentration diffusion layer, 17... Second side wall insulating film, 21... Si substrate, 22... Element portion iI
'l Insulating film, 23... Tantalum pentoxide, 23'...
Silicon dioxide (interface oxide film), 23'... Silicon dioxide film, 24... Gate electrode, 24'... Polycrystalline Si gate electrode, 25... Sidewall protection insulating film, 26...
・Si oxide film, 26'...polycrystalline silicon oxide film, 2
7... N+ diffusion layer region, 28... Wedge-shaped oxide film grown on silicon substrate, 28'... Wedge-shaped oxide film grown on polycrystalline silicon, 29... First insulating film, 30...・
Interlayer insulating film, 31... Metal wiring, 210... Second insulating film, 211... First diffusion layer region, second diffusion M
Region, 212...Tungsten electrode, 213...Silicon dioxide film.

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Claims (1)

[Claims] 1. Two regions of a second conductivity type provided on a semiconductor substrate of a first conductivity type constitute a source region and a drain region, and a gate insulating film is made of at least tantalum oxide, niobium oxide,
A method for manufacturing an insulated gate field effect transistor comprising a gate insulating film made of yttrium oxide, hafnium oxide, zirconium oxide, titanium oxide, a laminated film, or a mixture thereof, and a gate electrode provided through the gate insulating film. After processing the gate electrode on the gate insulating film, ions are implanted through the gate insulating film exposed on the surface of the semiconductor substrate to form at least one of a source region and a drain region of a second conductivity type. An insulated gate field effect transistor and a method for manufacturing the same. 2. In the method for manufacturing a semiconductor device according to claim 1, after performing the ion implantation to form a region of the second conductivity type, a sidewall insulating layer is formed on the gate insulating film so as to cover the side surface of the gate electrode. forming a film, further depositing a first insulating film, and performing ion implantation through the first insulating film,
A method for manufacturing an insulated gate field effect transistor, characterized in that a second region of the second conductivity type is formed on the semiconductor substrate with a higher concentration than the region of the second conductivity type that becomes the source and drain regions. . 3. Two regions of a second conductivity type provided on a semiconductor substrate of a first conductivity type constitute a source region and a drain region, and a gate insulating film of at least tantalum oxide, niobium oxide,
A method for manufacturing an insulated gate field effect transistor comprising a gate insulating film made of yttrium oxide, hafnium oxide, zirconium oxide, titanium oxide, a laminated film thereof, or a mixture thereof, and a gate electrode provided through the gate insulating film. After processing the gate electrode on the gate insulating film, forming a sidewall insulating film on the gate insulating film so as to cover a side surface of the gate electrode,
Further, a first insulating film is deposited, ions are implanted through the first insulating film to form a first second conductivity type region on the semiconductor substrate, and further, the sidewall insulating film is deposited. forming a second sidewall insulating film so as to cover the second sidewall insulating film, depositing a second insulating film, and performing ion implantation through the second insulating film;
A second region of the second conductivity type having a higher concentration than the first region of the second conductivity type is formed on the semiconductor substrate, and at least one of a source region and a drain region is formed. An insulated gate field effect transistor and its manufacturing method. 4. Two regions of a second conductivity type provided on a semiconductor substrate of a first conductivity type constitute a source region and a drain region, and a gate insulating film of at least tantalum oxide, niobium oxide,
A method for manufacturing an insulated gate field effect transistor comprising a gate insulating film made of yttrium oxide, hafnium oxide, zirconium oxide, titanium oxide, a laminated film thereof, or a mixture thereof, and a gate electrode provided through the gate insulating film. After processing the gate electrode on the gate insulating film, ions are implanted through the gate insulating film exposed on the surface of the semiconductor substrate to form a first region of the second conductivity type; A sidewall insulating film is formed on the gate insulating film so as to cover the side surfaces of the gate electrode, and a second insulating film is further deposited, and ions are implanted through the second insulating film to form the semiconductor. An insulated gate characterized in that a second region of a second conductivity type is formed on a substrate with a higher concentration than the first region of a second conductivity type, and at least one of a source region and a drain region is formed. type field effect transistor and its manufacturing method. 5. The gate insulating film is made of tantalum oxide, niobium oxide,
Claims 1, 2, and 2 are characterized in that the invention is a laminate film of yttrium oxide, hafnium oxide, zirconium oxide, titanium oxide, a laminate film thereof, or a mixture thereof, and silicon dioxide. The insulated gate field effect transistor and the manufacturing method thereof according to item 3 or 4. 6. At least one of tantalum oxide, niobium oxide, yttrium oxide, hafnium oxide, zirconium oxide, titanium oxide, or In a method for manufacturing a field effect transistor comprising a gate insulating film containing the mixture and a gate electrode provided through the gate insulating film, after processing the gate electrode and the gate insulating film, depositing a first insulating film, An insulating film is formed on the side walls of the gate electrode by anisotropic etching, and the substrate is heat-treated in an oxidizing atmosphere to oxidize the surface of the substrate, and then impurities of the opposite conductivity type to the semiconductor substrate are implanted to form an insulating film on the side walls of the gate electrode. A method of manufacturing a semiconductor device, characterized in that a drain region is formed. 7. In the method for manufacturing a semiconductor device according to claim 6, after processing the gate electrode and the gate insulating film, a first insulating film is deposited, and the first insulating film is penetrated and the gate insulating film is deposited. 1. A method of manufacturing a semiconductor device, characterized in that the source and drain regions are formed by implanting impurities of a conductivity type opposite to that of the semiconductor substrate. 8. In the method for manufacturing a semiconductor device according to claim 6, after processing the gate electrode and the gate insulating film, depositing a first insulating film and penetrating the insulating film onto the substrate. After forming the low concentration impurity region, a second insulating film is further formed on the sidewall, and the substrate is heat-treated in an oxidizing atmosphere to oxidize the substrate surface, and then impurities of the opposite conductivity type to the semiconductor substrate are implanted. 1. A method of manufacturing a semiconductor device, characterized in that the source and drain regions are formed by forming the source and drain regions. 9. In the method for manufacturing a semiconductor device according to claim 6, 7, or 8, the gate electrode is made of tantalum oxide, niobium oxide, yttrium trioxide, hafnium oxide, zirconium oxide, or titanium oxide. or a mixture thereof, and a mixture of silicon dioxide.