JPH0374878A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device

Info

Publication number
JPH0374878A
JPH0374878A JP1210071A JP21007189A JPH0374878A JP H0374878 A JPH0374878 A JP H0374878A JP 1210071 A JP1210071 A JP 1210071A JP 21007189 A JP21007189 A JP 21007189A JP H0374878 A JPH0374878 A JP H0374878A
Authority
JP
Japan
Prior art keywords
film
psg
sio
insulation film
provided
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1210071A
Other versions
JP2816192B2 (en
Inventor
Hiroshi Jinriki
Kiichiro Mukai
Masayuki Nakada
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP1210071A priority Critical patent/JP2816192B2/en
Publication of JPH0374878A publication Critical patent/JPH0374878A/en
Priority claimed from US07/883,531 external-priority patent/US5292673A/en
Application granted granted Critical
Publication of JP2816192B2 publication Critical patent/JP2816192B2/en
Anticipated expiration legal-status Critical
Application status is Expired - Fee Related legal-status Critical

Links

Abstract

PURPOSE: To obtain an IGFET using a transition metal oxide film especially for a gate insulation film by penetrating the gate insulation film without performing light oxidation and by implanting ion.
CONSTITUTION: An SiO2 is provided on the surface of a p-type Si substrate 1 for implanting a channel of BF2. The SiO2 film is eliminated and a tantalum pentoxide 2 is sputtered. Treatment is performed within dry O2 at 800°C and an SiO2 film 3 is formed between the substrate 1 and the tantalum pentoxide 2. Then, a W film 4 is sputtered and a PSG 5 is superposed. The PSG 5 is subjected to patterning and the W film 4 is machined with the PSG 5 as a mask. Then, As ion is implanted, thermal treatment is performed within N2 for producing an n+ layer 6, and a drain layer is provided in self-aligned manner to a W gate pattern. Further, an interlayer insulation film 7 is superposed and a wiring metal film 8 is provided for completing an FET. With this method, it is possible to form an IGFET without performing light oxidation even if a material with an extremely rapid diffusion of an oxidation seed such as tantalum pentoxide is used as a gate insulation film.
COPYRIGHT: (C)1991,JPO&Japio
JP1210071A 1989-08-16 1989-08-16 A method of manufacturing a semiconductor device Expired - Fee Related JP2816192B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1210071A JP2816192B2 (en) 1989-08-16 1989-08-16 A method of manufacturing a semiconductor device

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP1210071A JP2816192B2 (en) 1989-08-16 1989-08-16 A method of manufacturing a semiconductor device
KR1019900012509A KR0172116B1 (en) 1989-08-16 1990-08-14 Method of manufacturing a semiconductor device
US07/883,531 US5292673A (en) 1989-08-16 1992-05-15 Method of manufacturing a semiconductor device

Publications (2)

Publication Number Publication Date
JPH0374878A true JPH0374878A (en) 1991-03-29
JP2816192B2 JP2816192B2 (en) 1998-10-27

Family

ID=16583339

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1210071A Expired - Fee Related JP2816192B2 (en) 1989-08-16 1989-08-16 A method of manufacturing a semiconductor device

Country Status (2)

Country Link
JP (1) JP2816192B2 (en)
KR (1) KR0172116B1 (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1993023878A1 (en) * 1992-05-13 1993-11-25 Tadahiro Ohmi Semiconductor device
JP2002519865A (en) * 1998-06-30 2002-07-02 ラム リサーチ コーポレーション ulsimos having a high dielectric constant gate insulator
US6784508B2 (en) 2000-03-10 2004-08-31 Kabushiki Kaisha Toshiba Semiconductor device having a gate insulating film structure including an insulating film containing metal, silicon and oxygen and manufacturing method thereof
US6927435B2 (en) 2001-01-16 2005-08-09 Renesas Technology Corp. Semiconductor device and its production process
JPWO2004114390A1 (en) * 2003-06-20 2006-08-03 日本電気株式会社 Semiconductor device and manufacturing method thereof
JP2008135765A (en) * 2007-12-21 2008-06-12 Seiko Epson Corp Semiconductor device
US7605064B2 (en) 2000-02-29 2009-10-20 Agere Systems Inc. Selective laser annealing of semiconductor material
US7833865B2 (en) 2004-09-13 2010-11-16 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device including a LaAIO3 layer

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1993023878A1 (en) * 1992-05-13 1993-11-25 Tadahiro Ohmi Semiconductor device
US5528068A (en) * 1992-05-13 1996-06-18 Ohmi; Tadahiro Semiconductor device
JP2002519865A (en) * 1998-06-30 2002-07-02 ラム リサーチ コーポレーション ulsimos having a high dielectric constant gate insulator
US7605064B2 (en) 2000-02-29 2009-10-20 Agere Systems Inc. Selective laser annealing of semiconductor material
US6784508B2 (en) 2000-03-10 2004-08-31 Kabushiki Kaisha Toshiba Semiconductor device having a gate insulating film structure including an insulating film containing metal, silicon and oxygen and manufacturing method thereof
US7947610B2 (en) 2000-03-10 2011-05-24 Kabushiki Kaisha Toshiba Semiconductor device having a gate insulating film structure including an insulating film containing metal, silicon and oxygen and manufacturing method thereof
US7544593B2 (en) 2000-03-10 2009-06-09 Kabushiki Kaisha Toshiba Semiconductor device having a gate insulating film structure including an insulating film containing metal, silicon and oxygen and manufacturing method thereof
US7306994B2 (en) 2000-03-10 2007-12-11 Kabushiki Kaisha Toshiba Semiconductor device having a gate insulating film structure including an insulating film containing metal, silicon and oxygen and manufacturing method thereof
US6927435B2 (en) 2001-01-16 2005-08-09 Renesas Technology Corp. Semiconductor device and its production process
JPWO2004114390A1 (en) * 2003-06-20 2006-08-03 日本電気株式会社 Semiconductor device and manufacturing method thereof
JP4747840B2 (en) * 2003-06-20 2011-08-17 日本電気株式会社 A method of manufacturing a semiconductor device
US7833865B2 (en) 2004-09-13 2010-11-16 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device including a LaAIO3 layer
JP2008135765A (en) * 2007-12-21 2008-06-12 Seiko Epson Corp Semiconductor device

Also Published As

Publication number Publication date
JP2816192B2 (en) 1998-10-27
KR0172116B1 (en) 1999-02-01

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees