JPH02270335A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce the running current on the position deep from the surface of drain/source diffused layers thereby enabling the punch-through phenomenon to be restrained by a method wherein nitrogen led-in layers are provided underneath the drain/source diffused layers. CONSTITUTION:The title semiconductor device is provided with a gate electrode 4 formed on a semiconductor substrate 1, drain/source diffused layers 6 provided on the semiconductor substrate 1 holding the said gate electrode 4 and nitrogen led-in layers 7 provided underneath the drain/source diffused layers 6. For example, a gate oxide film 3 is formed on a specific position in an element formation region on the n type silicon substrate 1 and then the gate electrode 4 is formed on the gate oxide film 3 while sidewall insulating films 5 are formed on both sides thereof. Furthermore, the boron nitride added layers 7 formed of boron nitride using sputter type ion implantation process are provided on the positions in contact with the lower part of the prospective drain/source diffused regions 6 in the n type silicon substrate 1 and then the drain/source diffused layers 6 are formed by ion implanting the boron.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Prior to Industrial Use) The present invention relates to the structure and manufacturing method of a MOS transistor, and particularly relates to a MOS transistor with reduced punch-through phenomenon.

(Prior Art) FIG. 3 shows the structure of a conventional MOS transistor. An element isolation region 22 is formed on the n-type silicon substrate 21 by a selective oxidation method or the like.

Further, a gate oxide film 23 is formed at a predetermined position in the element formation region on the n-type silicon substrate 21, and a conductor film, such as phosphorus, is diffused at a high concentration on the gate oxide film 23. A gate electrode 24 made of polycrystalline silicon is formed. On the side surface of this gate electrode 24, for example, LP
-A sidewall insulating film 25 made of a CVD Si02 film is formed. In addition, a P-type drain/drain in which boron or boron fluoride is implanted from the end of the gate electrode 24 in the n-type silicon substrate 21 to the element/isolation region 22 is used.
A source diffusion layer 26 is formed. On the drain/source diffusion layer 26 and the gate electrode 24, an SiO2 film containing a large amount of boron and phosphorus, that is, a BPSG film 27 is formed to planarize the device. Further, a contact hole is provided at a predetermined position on the drain/source diffusion layer 26, and an electrode 28 made of 8 ρ is formed.

In a MOS transistor with such a structure, since the diffusion coefficient of boron is large, the drain/source diffusion layer 26
A diffusion layer is formed from the surface to a deep position by heat treatment after boron ion implantation.

Therefore, a punch-through phenomenon in which current flows even at a deep position in the drain/source diffusion layer 26 becomes noticeable. In addition, with the miniaturization of devices, the depth of the drain/source region 26 must be made shallow, and in order to form the shallow drain/source diffusion layer 26 by ion implantation, the energy of ion implantation must be set to a low value. must be held down. However, reducing the energy of ion implantation is related to the implantation dose, and if implantation is performed at too low an energy, ion reflection will occur, resulting in a problem that the implantation dose will not be accurate.

(Problems to be Solved by the Invention) As described above, in the conventional MOS transistor structure, a punch-through phenomenon occurs in which current flows deep in the diffusion layer, and in the case of boron in particular, this phenomenon occurs because the diffusion coefficient is large. becomes noticeable. This punch-through phenomenon has a problem in that it causes deterioration of device characteristics, such as drain current-gate voltage characteristics. Further, as elements become finer, it is necessary to make the diffusion layer shallower, and in order to form this by ion implantation, the energy of ion implantation must be kept to a low value. However, when implantation is performed at too low energy, ion reflection occurs, resulting in an inaccurate implantation amount.

An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that solves these problems.

[Structure of the Invention] (Means for Solving the Problems) The present invention has been made in view of the above circumstances, and the first invention is a gate electrode formed on a semiconductor substrate and a gate electrode formed on a semiconductor substrate. A semiconductor device is provided, comprising a drain/source diffusion layer provided on the semiconductor substrate with the semiconductor substrate sandwiched therebetween, and a nitrogen-introduced layer provided below the drain/source diffusion layer.

Further, a second invention provides a semiconductor device, wherein the layer into which nitrogen is introduced is a layer to which nitride, an impurity forming the drain/source diffusion layer, is added.

Further, in a third aspect of the invention, the semiconductor device is a P-channel MOS.
A semiconductor device characterized in that it is a transistor is provided.

Further, the fourth invention includes a step of forming a gate electrode on a semiconductor substrate and a drain/source diffusion layer on the semiconductor substrate with the gate electrode sandwiched therebetween, and adding nitrogen to a corresponding region under the drain/source diffusion layer. Provided is a method for manufacturing a semiconductor device characterized by comprising the steps of:

A fifth aspect of the present invention provides the method of manufacturing a semiconductor device according to claim 3, wherein the nitrogen is added by sputtering type ion implantation of nitride impurity forming the drain/source diffusion layer. .

(Function) As described above, in the present invention, by using a sputtered solid ion source in the semiconductor substrate located below the drain/source diffusion layer, the impurity nitride forming the drain/source diffusion layer is removed. form a layer containing Nitrogen in this additive layer traps carriers more easily than other elements, so this trapping action can reduce the flow of current deep from the surface of the drain/source diffusion layer and suppress the punch-through phenomenon.

In addition, it has a structure in which nitrides enter the semiconductor lattice,
Since the diffusion of impurities from the drain/source diffusion layer can be blocked in this part, the diffusion layer can be made shallow without having to suppress the ion implantation energy to a considerably low level, making it possible to respond to miniaturization of devices.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention. An element isolation region 2 is formed on an n-type silicon substrate 1 by a selective oxidation method or the like.

Further, a gate oxide film 3 is formed at a predetermined position in the element formation region on the n-type silicon substrate 1, and a conductor film, for example, made of polycrystalline silicon in which phosphorus is diffused at a high concentration, is formed on the gate oxide film 3. A gate electrode 4 is formed. The side surface of this gate electrode 4, for example LPGV
A sidewall insulating film 5 made of a D S t O2 film is formed. In addition, boron nitride (BN) is placed in contact with the lower part of the planned region of the drain/source diffusion layer 6 in the n-type silicon substrate 1.
A boron nitride doped layer 7 formed using a sputtering ion implantation method is provided. Furthermore, a drain/source diffusion layer 6 is formed on the boron nitride doped layer 7 by boron ion implantation. Also, this drain/
An SiO2 film containing large amounts of boron and phosphorus, ie, a BPSG film 8, is formed on the source diffusion layer 6 and the gate electrode 4 to planarize the device. Further, a contact hole is provided at a predetermined position on the drain/source diffusion layer 6, and an electrode 9 made of AI) is formed.

FIG. 2 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.

An element isolation region is formed on an n-type silicon substrate 1 (or an n-type well) by, for example, selective oxidation.

Next, a thickness of 200 mm is applied to the element formation region of the n-type silicon substrate 1.
A gate oxide film 3 having a thickness of about A is then formed on the entire surface of polycrystalline silicon for a gate electrode. Next, after diffusing phosphorus to lower the sheet resistance of this polycrystalline silicon to several tens of [Ω/C-], the gate electrode 4 is processed to a width of 1.0 μm using a photoresist as a mask. Next, by CVD method, S i
An O2 film of 150 OA is deposited over the entire surface of the wafer, and the entire surface is etched using a reactive ion etching method, thereby leaving the sidewall insulating film 5 only on the sidewalls of the gate electrodes 4.

(Figure 2 (a)) Next, the boron nitride target was heated to 1000°C to 1200°C.
, After sputtering in a cesium gas atmosphere to generate boron nitride, the drain/source diffusion layer 6 is extracted and accelerated and ion-implanted.
A boron nitride doped layer 7 is formed in the n-type silicon substrate 1 in contact with the lower part of the region to be formed. Next, add boron to 40 keys
The drain/
A source diffusion layer 6 is formed. During this annealing process, an S layer with a thickness of about 400A is placed on the drain/source/gate.
An IO2 film 10 is also formed.

(Figure 2(b)) Next, 5i0 formed on the drain/source/gate
2 film 10 is removed by etching with a dilute HF solution. Next, Si containing a large amount of boron and phosphorus was prepared using the CVD method.
A BPSG film 8, ie, a BPSG film 8, is deposited on the entire surface to a thickness of about 1 μm, and annealed at 900° C. for 60 minutes in a 206g3 atmosphere to planarize the surface of the BPSG film 8. (FIG. 2(C)) Next, a contact hole is opened in this BPSG film 8, and an AI film, for example, is deposited on the entire surface by 8000A sputtering method, and then patterned to form an electrode 9. (FIG. 2(d)) In the structure and manufacturing method of the MOS l-transistor as described above, a nitrogen-doped layer is provided below and in contact with the drain/source diffusion layer. Since nitrogen is more likely to trap carriers than other elements, this trapping action can reduce the flow of current deep from the surface of the drain/source diffusion layer and control the punch-through phenomenon.

In addition, the structure is such that boron nitride enters the lattice of silicon atoms, and boron or boron fluoride can be diffused in this part by annealing, so the diffusion layer can be made shallow without having to keep the ion implantation energy to a very low level. It is also possible to respond to miniaturization of elements.

Note that by controlling the amount of boron nitride ions to be implanted, it is also possible to omit the subsequent boron ion implantation step. That is, by implanting boron nitride ions at a predetermined depth and diffusing boron from this ion implantation layer to the surface, a structure similar to that of the previous embodiment can be realized.

Furthermore, although the above embodiments have been described with respect to a P-channel MOS transistor, they can be similarly applied to an N-channel MOS transistor or even a CMOS transistor. n
In a channel MOS transistor, a P-type silicon substrate may be used and arsenic or phosphorus may be used as drain/source impurities. In this case, arsenic or phosphorus nitride may be provided below and in contact with the drain/source diffusion layer.

Further, in the above embodiments, nitride impurities were ion-implanted, but if desired, only nitrogen ions may be implanted.

[Effects of the Invention] As described above, according to the present invention, nitrogen has a stronger carrier trapping effect than other elements, so it is possible to prevent current from flowing deep from the surface of the drain/source diffusion layer. The through phenomenon can be suppressed. Therefore, deterioration of the characteristics of the element can be prevented, leading to improved reliability.

Further, it is possible to obtain a semiconductor device in which a shallow diffusion layer can be formed without suppressing the energy of ion implantation to a considerably low level.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention, and FIG.
The figures are cross-sectional views showing the method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps, and FIG. 3 is a cross-sectional view showing a conventional semiconductor device. In the figure, 1... n-type silicon substrate, 2... element isolation region, 3
... Gate oxide film, 4... Gate electrode, 5... Sidewall insulating film, 6... Drain/source diffusion layer, 7...
Boron nitride added layer, 8... BPSG film, 9... Electrode, 1o... SiO2 film, 21... N-type silicon substrate, 22... Element isolation region, 23... Gate oxide film , 24... Gate electrode, 25... Sidewall insulating film, 26
...Drain/source diffusion layer, 27...BPSG film, 28... Electrode.

Claims (5)

[Claims] (1) A gate electrode formed on a semiconductor substrate, a drain/source diffusion layer provided on the semiconductor substrate with the gate electrode in between, and a nitrogen-introduced layer provided below the drain/source diffusion layer. A semiconductor device characterized by comprising: (2) The semiconductor device according to claim 1, wherein the layer into which nitrogen is introduced is a layer into which nitride, an impurity forming the drain/source diffusion layer, is added. (3) The semiconductor device according to claim 1 or 2, wherein the semiconductor device is a P-channel MOS transistor. (4) A step of forming a gate electrode on a semiconductor substrate and a drain/source diffusion layer on the semiconductor substrate with the gate electrode sandwiched therebetween, and a step of adding nitrogen to a corresponding region under the drain/source diffusion layer. A method for manufacturing a semiconductor device, characterized in that: (5) The method of manufacturing a semiconductor device according to claim 4, wherein the nitrogen is added by a sputter type ion implantation method of nitride impurity forming the drain/source diffusion layer.