JPS6341063A - Manufacture of mos integrated circuit - Google Patents

Abstract

PURPOSE:To easily obtain two types of silicon gate MOS transistors having different threshold value voltages by forming passivation films on the transistors, forming silicon nitride films partly thereon, and heat treating them. CONSTITUTION:Silicon dioxides are formed by a chemical vapor growing method on a plurality of silicon gate MOS transistors on a sole silicon substrate on which aluminum gates are formed by an electron beam depositing method to form passivation films 11, nitride silicons are further formed by a plasma chemical vapor growing method on the whole surface, and silicon nitride films 12 remain only on predetermined silicon gates of the transistors by a photoetching method. Thereafter, when it is heat treated, for example, at 410 deg.C for 30 min. in a nitrogen gas atmosphere partly including hydrogen gas, the threshold value voltages of the transistors leaving the films 12 can be set to a predetermined high voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing an MO8 integrated circuit, the purpose of which is to obtain silicon gate MOS transistors with different threshold voltages on a single silicon substrate.

2. Description of the Related Art Conventional methods for obtaining two types of MOS transistors with different threshold voltages on a single silicon substrate include the following.

■Method of making the impurity concentration on the silicon surface directly under the gate oxide film different values by adding impurities ■Method of making the pattern of the gate oxide film have different values ■Method of using different substances as gate electrode materials Problems In all of these conventional methods, process conditions must be additionally set in the middle of the manufacturing process of the MO8 integrated circuit in order to set the threshold voltage to a different value.

In order to solve the above-mentioned problems, the present invention provides a method for setting threshold voltages to different values in the manufacturing process of an MO8 integrated circuit for obtaining silicon gate MO8 transistors with different threshold voltages on a single silicon substrate. By adding a simple process to the manufacturing process of a normal MO8 integrated circuit made of silicon gate MoS transistors with the same threshold voltage without setting any additional process conditions, MO3 of silicon gate MOS transistors with different threshold voltages can be manufactured.
The object is to provide a manufacturing method for obtaining integrated circuits.

Means for Solving the Problems In order to solve the above problems, the present invention provides silicon dioxide as a passivation film on a plurality of silicon gate MOS transistors on a 111-silicon substrate in which aluminum electrodes are formed by an electron beam vapor method. form,
Furthermore, a silicon nitride layer is partially formed on a passivation film on a predetermined MOS transistor, and then heat treatment is performed to form two types of MOS transistors having different threshold voltages on a single silicon substrate.

Effect: By using the manufacturing method according to the present invention described above, the threshold voltage of a silicon gate MoS transistor formed on the gate portion through a silicon nitride passivation film can be changed to the threshold voltage of a silicon gate MOS transistor on which no silicon nitride film is formed. It can be made different.

Example Hereinafter, one embodiment of the present invention will be described based on the drawings.

In FIG. 1, 1 is a P-type silicon substrate, and this P
First, a thick field insulator rtA2 made of silicon dioxide is formed on a silicon substrate 1, and windows for active regions 3a and 3b in which transistors are to be formed are formed (FIG. 1(a)). On top of that, silicon dioxide is formed to a thickness of approximately 1,000 layers using thermal oxidation, and then polycrystalline silicon is formed on the entire surface using a chemical vapor deposition method to a thickness of 3,000 to 50 nm.
After forming to a thickness of 00A, patterning is performed using a photoetching method to form gate insulators n 4 a and 4 b made of silicon dioxide as silicon gate portions and silicon gates 5 a and 5 b made of polycrystalline silicon. , source regions 5 a, 5 b and drain regions 7 a, 7 b are formed from the surface of P-type silicon substrate 1 by self-alignment method by impurity diffusion using known gas diffusion method, ion implantation method, etc. Figure 1 (b)). Furthermore, a silicon dioxide film 8 is formed on the entire surface by chemical vapor deposition, and the silicon dioxide rfA 8 is removed by etching only at the source and drain electrode extraction portions to form a contact window, and then electron beam evaporation is performed on the entire surface. Aluminum is milled using a method and patterned using a photoetching method to form source m#19a, 9b, drain electrode 10a,
10b (FIG. 1(C)). Next, by applying heat treatment (hemo sintering) at a temperature of 450°C for 20 minutes in a nitrogen gas atmosphere containing a portion of hydrogen gas, it is possible to obtain two silicon gate MOS transistors with equal threshold voltages. can.

Next, silicon dioxide is formed on the entire surface by chemical vapor deposition to form a passivation film 11, and silicon nitride is further formed on the entire surface by plasma chemical vapor deposition, and predetermined transistors are formed by photoetching. The silicon nitride film 12 is left only on the silicon gate portion (FIG. 1(d)). Thereafter, for example, heat treatment is applied at a temperature of 410° C. for 30 minutes in a nitrogen gas atmosphere containing a portion of hydrogen gas. As described above, the threshold voltage of the silicon gate MOS transistor in which the silicon nitride film 12 remains can be set to a predetermined high voltage.

Next, its effect will be explained.

The source electrodes 9a, 9b and the drain electrode 10 of the MoS transistor are coated with aluminum using an electron beam evaporation method.
a, 10b, the gate insulating film 4a, 4 of the silicon gate portion is damaged due to radiation damage during vapor deposition.
The interfacial unit density in b increases. That is, the threshold voltage vth of the MOS transistor has a value lower than the threshold voltage of an ideal MOS transistor with N SS = O due to the increased interfacial unit density NSS. Even if this can be recovered by patterning aluminum electrode heat treatment (Aρ sintering), heat treatment at 450℃ for 20 minutes (Aρ sintering)
sinter), the value is about 0.5 V lower than the ideal threshold voltage. In a silicon gate MOS transistor in which the silicon nitride film 12 is not left, the final step 41 is performed.
Even with heat treatment at 0°C for 30 minutes, the voltage increases by only about 0.1V, as shown by the solid line in FIG. After heat treatment for 30 minutes, the voltage rises by about 0.5 V to near the ideal threshold voltage and becomes stable, as shown by I5a in FIG. 2(b).

In other words, the threshold voltage differs by about 0.4V depending on the presence or absence of silicon nitride pus 12! Similar MOS transistors can be realized. The two types of silicon gate MOS transistors formed in this manner exhibit completely stable characteristics in actual use.

Although this embodiment has been described using an N-channel MOS transistor, it goes without saying that the same implementation can be achieved using a P-channel MOS transistor. In the case of a P-channel type MOS transistor, the change in the threshold (absolute value of ia lightning voltage) due to the heat treatment in the R final step is similarly shown by broken lines in FIGS. 2(a) and 2(b).

Effects of the Invention As described above, according to the present invention, the steps of forming a passivation film, partially forming a silicon nitride film thereon, and performing heat treatment are added to the manufacturing process of a silicon gate MO8 transistor. , two types of silicon gate, ~10S transistors with different threshold voltages can be easily obtained.

[Brief explanation of drawings]

FIGS. 1(a) to 1(d) are cross-sectional structural diagrams of silicon gate MOS transistors arranged in the order of manufacturing steps showing one embodiment of the present invention, and FIG. 2(a) is a silicon gate MOS transistor without a silicon nitride film. FIG. 2(b) is a characteristic diagram of a silicon gate MOS transistor having a silicon nitride film, without showing changes in threshold Fi lightning voltage due to heat treatment in the R final step. DESCRIPTION OF SYMBOLS 1...P-type silicon substrate, 2...Field insulating film, 3...Active region of MOS transistor, 4...Goo 1-Zetsun control, 5...Gate, 6...Source region ,
7... Drain region, 8... Silicon dioxide film, 9
...Source electrode, 10...Drain electrode, 11...
- Passivation film, 12... silicon nitride model.

Claims (1)

[Claims] 1. Multiple silicon gate MOSs on a single silicon substrate with aluminum electrodes formed by electron beam vaporization
Silicon dioxide is formed as a passivation film on the transistor, and then a silicon nitride film is partially formed on the passivation film on a predetermined MOS transistor, and then heat treatment is performed to create two types of MOS transistors with different threshold voltages. M formed on a single silicon substrate
A method for manufacturing an OS integrated circuit.