JPS5892268A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To manufacture an extremely high density MOSIC, by making a polycrystalline silicon film an insulating material as an oxide (SiO2), thereby excluding leaking currents between cells and enhancing the insulating effect between layers. CONSTITUTION:A part of a second gate polycrystalline silicon film remains in a concave part 14 at the lower part of a first gate polycrystalline silicon film 5. This part acts as a source of the leaking currents. The remaining polycrystalline silicon material is all made to be SiO2, by performing the first oxidation treatment, in which heat treatment is performed for ten minutes in an dried oxygen at 900 deg.C, and further performing the second oxidation treatment for thirty minutes in steam atmosphere at 900 deg.C. At the same time, an oxide film is grown on the second gate polycrystalline silicon film, and the insulating property is enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an MO8 type semiconductor integrated circuit having a multilayer polycrystalline structure.

Semiconductor integrated circuits (hereinafter referred to as MO8IC) formed using MO8 type transistors, such as dynamic RAM or charge-coupled devices (COD), have an extremely high degree of integration < 6.2 or 3 layer polycrystalline silicon gates. An MO8 type transistor structure is used. In addition, the design rule for design failures has been changed from a design rule based on 6 μm to a design rule based on 2 to 3 μm, and the thickness of the gate oxide film of MO8 type transistors has also changed from about 1000 to 0. 40
The thickness is decreasing to about 0 to 600 people, and the trend is toward higher integration.

Figure 1 shows a conventional MO5IC, for example, a dynamic RAM.
In the figure, 1 is a silicon substrate, 2 is a field oxide film, 3 is a first gate oxide film, 4 is a second gate oxide film, and 6 is a first gate oxide film. Polycrystalline silicon film, 6 is a second gate polycrystalline silicon film, 7 is a 5in2 film for insulation and surface protection, 8, 9
．． 10 is an aluminum (A1) electrode, 11 is a source and drain diffusion region, 12 is a channel stopper region, and 1
3 is a surface layer whose density is controlled.

With the structure described above, a basic cell formed by the equivalent circuit shown in FIG. 2 can be obtained.

By the way, due to the design rule based on 6μm,
For example, when manufacturing a 16-bit dynamic RAM with a gate oxide film thickness of 1oOO, the conventional method was as shown in Figure 3 (a).
) to (0) were manufactured under the manufacturing processes indicated by 0. Specific examples will be shown and explained below.

First, using a P-type (1oO) silicon substrate 1 with a resistivity of 15Ω as a starting material, a 1000Ω
A field oxide film 2 with a thickness of 0 and a depth of 1 below this
．． A P+ type channel stopper region 12 of 5 μm is formed [FIG. 3(a)]. Next, as shown in FIG. 3(b), a first gate oxide film 3 with a thickness of 100 mm is formed on the exposed silicon substrate without being covered with the field oxide film 2, and the threshold of the MO8 transistor is Boron ions (B+) are implanted to control the value (vT).

Next, 4000 ml of polycrystalline silicon doped with phosphorus
After being vapor-deposited to a human thickness, a predetermined etching process is performed, and the first
Forming gate polycrystalline silicon film 6 [Fig. 3(C)]
. Note that below the first gate polycrystalline silicon film 6 there are nine layers 13 whose concentration is controlled to obtain an appropriate threshold voltage.

Next, as shown in FIG. 3(d), a second gate oxide film 4 having a thickness of 100 mm is formed. Thereafter, a second gate polycrystalline silicon film 6 doped with (P) and having a thickness of 4000 nm is formed in a predetermined portion in the same manner as described above, and then the source and
Arsenic ions (As'') to form the drain diffusion region are implanted as shown in the arrows [Fig. 3(e)].Finally, a phosphorus glass film 7 is added as an insulating and protective film.
The main part of the basic cell is completed by depositing 8,000 wafers thick and drilling a window for electrode wiring (Figure 3).

Next, an A1 layer with a thickness of about 1 μm is provided, and this is applied to the electrodes 8 to 8.
By making it independent as 1o, the structure shown in FIG. 1 can be obtained.

However, by making full use of the above basic cell manufacturing method,
Gate oxide thickness: 400-600 mm, field oxide thickness: 60 mm, based on design rules based on 2-3 μm
When manufacturing a bit dynamic RAM with 64 bits of 00 people, most of the wafers have memory cells (bits)
A large leakage current reaching 500 μA to 1 mA was observed between the cells, and it was found that the second gate polycrystalline silicon film of the cell was the source of the leakage current. Further, as a result of observation using a scanning electron microscope, as shown in FIG. 4, a portion of the second gate polycrystalline silicon film remains in the recess 14 under the first gate polycrystalline silicon film 6.
It became clear that this was the source of leakage current. Furthermore, the remaining part of the second gate polycrystalline silicon film shown in the figure is a field formed by etching to improve the control accuracy of the threshold voltage when forming the first gate polycrystalline silicon film 5. It has also been found that this is because the second gate polycrystalline silicon film enters the recess 14 formed under the eaves-like portion of the oxide film 2 and remains without being removed by etching. In order to eliminate this inconvenience, it would be possible to perform an etching process to cause over-etching when etching the second gate polycrystalline silicon film, but in this case, the gate width would be reduced due to side etching, and this problem would occur. As a result, the control accuracy of the threshold voltage is significantly impaired.

The present invention was made with the intention of eliminating the above-mentioned disadvantages, and it eliminates leakage current between cells, improves the insulation effect between each layer, and improves ultra-high density MO3IC.
For example, the present invention provides a method for manufacturing a 64-bit dynamic RAM with high yield.

In the present invention, the polycrystalline silicon film in the portion that causes leakage current is turned into an insulator using oxide (S102) to eliminate leakage current. When oxidizing the crystalline silicon residue, it is preferable to oxidize the crystalline silicon residue for 1 hour in a water vapor atmosphere so as not to cause a large change in the depth of the drain and source diffusion regions.
The feature is that the heat treatment conditions are set at 000°C or less.

Incidentally, in a 2-3μ standard process with a gate oxide film thickness of 600 μm, the size of the polycrystalline silicon residue in the recess 14 is less than 600 Å, but if the 600 μm polycrystalline silicon is When heat treatment is performed at 1000°C in a dry 02 atmosphere, the treatment time is about 10 minutes, and when heat treatment is performed at 1000°C in a steam atmosphere, the treatment time is about 13 minutes. be done. When these heat treatments are added, the source and drain diffusion regions become approximately 0.
．． The depth becomes 2 to 0.4 μm, and the short channel effect is promoted. By the way, the oxidation rate of polycrystalline silicon doped with P or boron (B) in a water vapor atmosphere is 2.0.8 at 900°C for undoped polycrystalline silicon.
It is also known that at 50°C, it becomes 2.6, which increases at temperatures lower than 1000°C.

In the present invention, the polycrystalline silicon residue in the recess is effectively converted into oxide by actively utilizing the selectivity of oxidation and the low influence on the diffusion length due to such low-temperature treatment in a steam atmosphere. At the same time, an oxide film is also grown on the second gate polycrystalline silicon film to improve insulation.

The manufacturing method of the present invention will be described below with reference to Examples. A basic cell structure having the same structure is obtained through the conventional manufacturing process shown in FIGS. 3(a) to 3(el). Furthermore, the conventional basic cell is
The thickness of the field oxide film 2 is 6000, and the first. There are four differences: the thickness of the second gate oxide films 3 and 4 is 600 mm, the depth of the P+ type channel stopper region 12 is 0.8 μm, and the depth of the source and drain diffusion portions is 0.4 μm. There is. By going through this manufacturing process, the fourth
Polycrystalline silicon residue remains in the recess 14 as shown.

Then, in dry oxygen with a flow rate of s l/f + 900
A first oxidation treatment was carried out by heat treatment at 10°C for 10 minutes, followed by a steam atmosphere (bubbler temperature 90'C).

The second oxidation treatment at 90Q°C was carried out at a flow rate of 41/% for 30 minutes.
Apply for minutes. Through such oxidation treatment, polycrystalline silicon becomes 6
The polycrystalline silicon residue in the recess 14 was all oxidized to 5102. Further, an oxide film of approximately 13000 μm was formed on the second gate polycrystalline silicon film. Fifth
The figure (&) shows the cross-sectional structure of a basic cell that has gone through the above process. Note that the above oxidation treatment in dry oxygen was performed on polycrystalline crystals, but the oxidation conditions in a steam atmosphere were to shorten the oxidation time as much as possible and to increase the diffusion length of the source and drain diffusion regions. Decisions need to be taken into consideration to avoid. For this purpose, the temperature at which the oxidation rate ratio of impurity-doped polycrystalline silicon and non-impurity-doped polycrystalline silicon is large is required, that is, 1000°C or less, preferably 8°C.
It is preferable to set the treatment temperature to 900'C. 8oO~9
As mentioned above, at 00°C, the oxidation rate ratio is as large as 2.0 to 3.0, and the oxidation time is only about 40 minutes at maximum.

Furthermore, the oxide film breakdown voltage can be guaranteed to be at least soV. When the diffusion length of the source and drain diffusion portions was measured after the oxidation treatment under these conditions, it was found to be 0.4 μm, which confirmed that the diffusion length was maintained at the same value as before the oxidation treatment.

Next, as shown in FIG. 5(b), S is applied to form a surface protective film.
After forming the iO2 film 7, contact windows are formed in predetermined portions. Finally, an A1 film is deposited to a thickness of 1 μm to form a M1 wiring layer, thereby completing the basic cell formation according to the method of the present invention. The results of a comparative study of leakage defects between cells of the formed MO3IC and leakage defects between M1 wiring and polycrystalline silicon are shown.

The criteria for determining defectiveness is that the leakage current of the measurement system is 100%.
The chip had a leakage current exceeding nA or more. As is clear from this table, according to the manufacturing method of the present invention, which performs oxidation treatment to insulate the polycrystalline silicon residue,
．． It is clear that leak defects on both sides have been drastically reduced. Note that the number of measurement chips in the above table includes those located in the wafer and surrounding areas, so if these are excluded, it can be considered that leak defects are almost zero in the manufacturing method of the present invention.

As explained above, according to the present invention, leakage defects caused by polycrystalline silicon residue can be eliminated, and MO8ICs with ultra-high integration multilayer polycrystalline gates can be manufactured with high yield. 0

[Brief explanation of the drawing]

Figure 1 is a diagram showing the cross-sectional structure of a basic cell of a two-transistor type dynamic RAM, Figure 2 is its equivalent circuit diagram, and Figures 3 (&) to (f) are the manufacturing process of the basic cell using the conventional manufacturing method. FIG. 4 is an enlarged view of the cell portion where polycrystalline silicon residue, which causes leakage defects, is present. FIG. 5 (IL) and ('b) are characteristics of the method of the present invention. FIG. 2 is an enlarged cross-sectional view of a cell after oxidation treatment and an enlarged cross-sectional view showing the cell structure after formation of a surface insulating film. DESCRIPTION OF SYMBOLS 1... Silicon substrate, 2... Field oxide film, 3... First gate oxide film, 4...
...Second gate oxidized rattan, 5...First gate polycrystalline silicon film, 6...Second gate polycrystalline silicon film, 7...5i02 film , 8.9.10...
... Aluminum electrode, 11 ... Source,
Drain diffusion section, 12...Channel stopper region, 13...Surface layer, 14...Recess. □ Name of agent: Patent attorney Toshio Nakao and one other person t#14 Figure 5

Claims (1)

[Scope of Claims] (1) A step of selectively forming a first oxide film on one main surface side of a semiconductor substrate; forming a thin second oxide film;
selectively forming a first polycrystalline silicon film doped with impurities on the second oxide film; a step of removing the second oxide film, a step of forming a third oxide film thinner than the first oxide film on the main surface of the semiconductor substrate exposed in the removed portion of the second oxide film, and a third oxide film formed in the same step. A step of forming a second polycrystalline silicon film doped with impurities on the film, a step of subjecting the semiconductor substrate that has undergone the same step to a thermal oxidation treatment at 100° C. or less in a water vapor atmosphere, and a semiconductor substrate subjected to the same treatment. 1. A method of manufacturing a semiconductor device, comprising the step of forming an oxide film thereon. (to) The method for manufacturing a semiconductor device according to claim 1, wherein the heating oxidation treatment temperature is 8oO to 900°C. (3) The method for manufacturing a semiconductor device according to claim 1, characterized in that an oxidation treatment in a dry atmosphere is provided before the heating oxidation treatment in a steam atmosphere.