JPS60133755A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the accuracy of the width of a low concentration impurity layer by a method wherein an oxide film is formed by low-temperature thermal oxidation to a low-concentration-doped semiconductor substrate and a gate electrode made of high-concentration-doped polycrystalline Si, thus making the gate electrode as a mask. CONSTITUTION:A field oxide film 22 is formed on the Si substrate 21. Next, a thermal oxide film 23 is formed on the surface of an element region on the substrate 21. Then, a high-concentration-doped polycrystalline Si film 24 is deposited. The film 24 is formed by etching into the gate electrode 25 trapezoidal in cross-section. Low concentration impurity layers 271 and 272 are formed with the electrode 25 and the oxide film 22 as a mask. Oxide films 28 and 29 are formed by low-temperature thermal oxidation. At this time, a thick oxide film 29 is formed on the electrode 25. Finally, high concentration impurity layers 301 and 302 are formed with the electrode 25 and the oxide film 22 as a mask.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a MoS type semiconductor device in which the structure of a drain region is improved.

[Technical background of the invention]

As is well known, rapid miniaturization technology has been established in MoS type semiconductor devices (particularly LSI), and along with this, higher performance and higher integration have been achieved. In recent years, MO8LSIs with a channel length of 1 μm are being developed. In such minute MoS type semiconductor devices, the electric field between the source and drain regions becomes extremely large, and problems arise due to the large amount of electrons and holes generated in this high electric field. One of these is a fluctuation in threshold voltage (vth) due to charges injected into the dirt insulating film, and an abnormal increase in drain current caused by charges injected into the semiconductor substrate.

For this reason, an MO8fi semiconductor device (n-channel MO8) has been proposed that is manufactured by an excitation method and has a structure in which the high electric field between the source and drain regions is alleviated.

Next, this will be explained with reference to FIG.

First, a field oxide film 2 is formed on a p-type silicon substrate 1, and then a thermal oxide film is formed on the surface of the island-shaped element regions separated by the field oxide film 2. After that, a lindozo polycrystalline silicon film, for example, is deposited on the entire surface. do. Next, the polycrystalline silicon film is t'? turning to form a dart electrode 3;
Furthermore, after ff-) selectively etching the thermal oxide film using the electrode 3 as a mask to form a dirt oxide film 4, using the dirt electrode 3 as a mask, n-type impurities are ion-implanted into the element region to form a low-concentration n-type impurity. Form an impurity layer 51t5m (first
Figure (4) (illustrated).

Next, as shown in FIG. 1(B), a film 6 of CVD-Sin as a mask material is deposited on the entire surface. Continuing,
CVD-810, the film 6 is subjected to reactive ion etching, and the side walls of the dirt electrode 3 and dirt oxide film 4 are coated with CVD.
-8101 remains to form the wall 7 (Fig. 1 (
0 shown). Subsequently, using the dirt electrode 3 and wall 7 as a mask, n-type impurity ions are implanted into the element region to form a highly concentrated n-type impurity layer 8158m. Through these steps, the n-type impurity layer 51 located near the r-electrode 3
and a highly concentrated meter-shaped impurity layer 81 located in a portion far from the electrode 3, and the electrode 3.
A drain region 1O is formed, which consists of a low concentration n-type impurity layer 52 located nearby and a high concentration layered impurity layer 8 □ located away from the electrode 3 (FIG. 1(D)).
(Illustrated).

Next, after removing the wall 7 and depositing an interlayer insulating film 11 on the entire surface, contact holes 12 and - and source and drain lead-out wirings 13 and 14 are formed.
Channel MO8) Manufacture transistors (Figure 1 (E)
).

[Problems with background technology]

In the MOS transistor manufactured by the conventional method described above, source and drain regions 9 and 10 are located near the dirt electrode 3.
A low concentration n-type impurity layer 51.5□ constituting a part of is formed, but these impurity layers 5Lp52 have a large resistance, resulting in a decrease in conductance. The length of the n-type impurity layer 51952 is the same as the wall 70 surrounding the dart electrode 3.
Determined by width. However, since the width of the wall 7 largely depends on the thickness of the CVD-Sin film 6 and the conditions of reactive ion etching, it is difficult to precisely control the width of the wall 7, and even the n-type Impurity layer 51,5. It becomes difficult to control the width of the semiconductor device, resulting in variations in device characteristics. Furthermore, since the wall 7 is formed by reactive ion etching, the surface of the silicon substrate constituting most of the source and drain regions is damaged by ions during its formation, significantly degrading device characteristics.

[Purpose of the invention]

The present invention aims to provide a method for manufacturing a high-performance semiconductor device in which the width of a low-concentration impurity layer constituting a part of the source and drain regions can be precisely controlled and damage caused by ions on the surface of a semiconductor substrate can be eliminated. It is something to do.

[Summary of the invention]

The present invention utilizes the fact that when a lightly doped semiconductor substrate and a highly doped polycrystalline silicon are thermally oxidized at low temperature, an oxide film is formed on the polycrystalline silicon that is much thicker than that on the substrate. A dirt electrode made of highly doped polycrystalline silicon and having a trapezoidal cross section is formed in the element region through a dirt insulating film, and using this r-) electrode as a mask, impurity ions are implanted into the element region to form a lightly doped impurity layer. After forming, low-temperature thermal oxidation is performed to form an oxide film that is sufficiently thicker than the substrate surface around the dirt electrode, and then impurities are removed from the element region using the f-) electrode with the oxide film formed around it as a mask. The main idea is to manufacture a semiconductor device having the above-mentioned effects by forming a highly concentrated impurity layer by ion implantation.

[Embodiments of the invention]

Next, an example in which the present invention is applied to the manufacture of an n-channel MO8) transistor will be described with reference to FIGS. 2(4) to 2(g).

First, a field oxide film (element isolation region) 6 - 22 is formed on the p-type silicon substrate 21 by selective oxidation method or the like, and thermal oxidation is performed to form a diagonal element region of the substrate 21 separated by the field oxide film 22. 300~ on the surface
After forming a thermal oxide film 23 of 500X, a thickness of 50X is formed on the entire surface.
A polycrystalline silicon film 24 doped with a large amount of phosphorus (approximately 0.001) is deposited 7'c (as shown in FIG. 2).

(1i) Next, the polycrystalline silicon film 24 is subjected to nof turning by a photoetching technique using plasma etching to form a dart electrode 25 having a trapezoidal cross section.
Using the dirt electrode 25 as a mask, the thermal oxide film 23 was selectively etched to form a dirt oxide film 26. Next, using the dirt electrode 25 and the field oxide film 22 as a mask, an n-type impurity such as phosphorus is applied at an accelerating voltage of 25 K@
After ions were implanted into the element region of the substrate 21 under the following conditions: 'V% dose: 2×10''7 cm'', the ions were activated by heat treatment. As a result, low temperature n-type impurity layers 271, 27 . was formed.

Further, since the dart electrode 25 has a trapezoidal cross section, the n-type impurity layers 271, 21 . was formed to partially extend into the element region under the dart electrode 25 (as shown in FIG. 2(B)).

■ Next, heat containing hydrogen at 850°C or lower (e.g. 800°C
) was subjected to low temperature thermal oxidation. At this time, as shown in the characteristic diagram showing the relationship between oxidation temperature and oxide film thickness in Figure 3, an oxide film formed on a large amount of phosphorous-doped polycrystalline silicon (curve a in the diagram) is formed on a lightly doped silicon substrate (curve a in the diagram). It is significantly thicker than that of curve b). As a result, as shown in FIG. 2(C), an oxide film 28 with a thickness of about 400X is formed on the exposed surface of the substrate 21, and an oxide film 29 with a thickness of about 2000X is formed around the dirt electrode 25 made of phosphorus-doped polycrystalline silicon. Been formed. Next, using the dirt electrode 25 and the field oxide film 22 around which the thick oxide film 29 is formed as a mask, an n-type impurity, for example, arsenic, is applied to the element region at an accelerating voltage of 40 K@vs. Ions were implanted into the substrate and activated by heat treatment to form highly concentrated n+ type impurity layers 301, 301. Through these processes,
C-) Low concentration n-type impurity layer 2 located near the electrode 25
71 and a highly concentrated n-type impurity layer 31) located in a portion far from the electrode 25,
In addition, drain regions 32 each consisting of a low linearity n-type impurity layer 27s located near the electrode 25 and a high-concentration meter-shaped impurity layer 308 located away from the electrode 25 were formed (second Figure (c) (Illustrated).

Qψ Next, after depositing the CVD-sto film S3 on the entire surface, contact holes 34... are opened to take out the source and drain A! An n-channel MO8) transistor is manufactured by forming wirings 35 and 36 in the holes (as shown in FIG. 2(G)).

According to the present invention, the highly concentrated layered impurity layer so1
, so are formed using the dirt electrode 25 around which the thick oxide film 29 is formed as a mask, the low concentration n-type impurity layers 271, 27 . The width of the MOS transistor can be controlled with high accuracy, and as a result, a MOS transistor with stable electrical performance can be obtained.

9- Also, how about a wall like the conventional method? -) Reactive ion etching to remain around the electrode t = - Since the stump is not used, damage by ions to the surfaces of the source and drain regions 31 and 32 can be avoided, and a highly reliable MOS transistor can be obtained.

Furthermore, if a thick oxide film 29 is formed around the dirt electrode 25 by low-temperature thermal oxidation treatment, the dirt electrode 25 may become thinner and thinner, and its width may decrease, resulting in an offset, as shown in FIG. 2 (0). As shown in FIG. 2(B), the dart electrode 25 is formed to have a trapezoidal cross section,
When forming the low concentration n-type impurity layers 211 and 272, a portion thereof extends to the element region below the r-) electrode 25, thereby preventing offset due to thinning of the r-) electrode.

The present invention is not limited to the manufacture of n-channel MOB transistors, but is equally applicable to the manufacture of p-channel MOB transistors, complementary MOB transistors, and the like.

10- [Effects of the Invention] As detailed above, according to the present invention, the width of the low concentration impurity layer constituting a part of the source and drain regions can be precisely controlled, and the width of the low concentration impurity layer constituting a part of the source and drain regions can be controlled accurately. It is possible to provide a method for easily manufacturing a semiconductor device such as a high-performance MOS (Lanzostar) that eliminates damage caused by ions.

[Brief explanation of drawings]

Figures 1-(g) are cross-sectional views showing the manufacturing process of a conventional n-channel MOS transistor, and Figures 2(4)-(g)
3 is a cross-sectional view showing the manufacturing process of an n-channel MOS transistor in an embodiment of the present invention, and FIG. 3 shows the relationship between the oxidation rate and the oxide film thickness of a highly doped polycrystalline silicon substrate and a lightly doped single crystal silicon substrate. FIG. 21...p-type silicon substrate, 22...field oxide film, 25...dirt electrode, 26...dirt oxide film, 211.27. ...Low concentration n-type impurity layer, 28.
...Thin oxide film, 29...Thick oxide film, J'l+30
2... High concentration nu impurity layer, 31... Source region, 32... Drain region, 35.36... Al wiring. Applicant's representative Patent attorney Takehiko Suzue - The taste of - The υ of one sip

Claims (1)

[Claims] After forming an element isolation region on a semiconductor substrate of a first conductivity type and forming an insulating film on the surface of the element region of the semiconductor substrate separated by the element isolation region, a polycrystalline silicon film containing impurities is deposited. a process of leaning this polycrystalline silicon film to form a dart electrode with a trapezoidal cross section; a process of doping the surface of the element region with a second conductivity type impurity using the dirt electrode as a mask; It is characterized by comprising the step of performing oxidation treatment to form an oxide film around the dirt electrode, and then doping the element region with a second conductivity type impurity using the dirt electrode around which the oxide film is formed as a mask. A method for manufacturing a semiconductor device.