JPS60134469A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce ion implantation processes, and to simplify processes by forming a film containing an impurity to the surface of a substrate and diffusing the impurity into the film through heat treatment under predetermined conditions when an MOS transistor with a drain region in low impurity concentration is prepared. CONSTITUTION:A thick field oxide film 12 is formed to the peripheral section of a P type Si substrate 11, a thin oxide film 13 is applied on the surface of the substrate 11 surrounded by the oxide film 12, and B ions for controlling threshold voltage are implanted to the surface layer of the substrate 11 through the oxide film 13. A gate electrode 15 is formed at the centrat section of the surface of the substrate 11 through a gate insulating film 16 consisting of the film 13, and an SiO2 film 17 containing a P impurity is applied on the whole surface. The impurity in the film 17 is diffused through heat treatment for 20min at 900 deg.C in N2 gas to form N<-> type regions 18 and 19 to the surface layer section of the substrate 11 on both sides of the electrode 15. The films 17 are left only on both side surfaces of the electrode 15 as 17', and As ions are implanted to the regions 18 and 19 again to form N<+> type source and drain regions 20, 21 connected to the regions 18 and 19.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device.
(Liahtly cloped dran+) f
The present invention relates to a method of manufacturing a MOS h-ran disk having an i-structure.

[Komyo's technical contradictions and their problems]

(, n America, semiconductor devices such as N ditonel type MOSI)
- The transistor is manufactured as shown in FIG.

First, after forming a thermal oxide film on a P-type Si substrate 1,
In order to suppress the channel effect, the channel region 2 is formed by implanting boron ions into the substrate 1. Subsequently, after a gate electrode 3 is formed on the thermal oxide film, the thermal oxide film is selectively removed by using the gate electrode 3 as a mask to form layers 1 to 4. Furthermore, using the mask 1 to electrode 3, ions of, for example, arsenic are implanted into the substrate 1 to form N4 type source and drain regions 5 and 6. Thereafter, an interlayer insulating film, contacts 1 to holes, etc. are sequentially formed by a conventional method to manufacture a semiconductor device. However, according to the I', II OS +- transistors manufactured in this way:
The electric field concentrates near the drain region 6, and the substrate current increases to generate hole-electron pairs, which causes the electrons to become
1~ The transistor characteristics become unstable due to reasons such as injection into the electrode. For this reason, as shown in FIG. 2, the source and drain regions 5.6 near the electrodes 1 to 3 are separated from these regions 5.6 by 'fAr! MOS with L D D lfi structure with low N type impurity region of 7.8
An l-transistor has been proposed. According to such a transistor, an N-type impurity region 7.8 with a low tlr of 1 degree is provided in the source and train regions 5.6 near the goo 1-electrode 3. Electric field concentration can be alleviated. However, such 1
- According to the transistor, two ion implantations are required to form the source and drain regions 5.6, which complicates the process.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and the present invention has been made in view of the above circumstances.
It is an object of the present invention to provide a method for manufacturing a semiconductor device that can omit one ion implantation and simplify the process compared to manufacturing a semiconductor device with a DD structure.

[Summary of the invention]

In the present invention, after forming a film containing impurities on the entire surface, heat treatment is performed under predetermined conditions to diffuse the impurities from the film to the surface of the semiconductor substrate.
D be.

[Embodiments of the invention]

Hereinafter, a case where the present invention is applied to an N channel type MOS transistor will be explained with reference to FIGS. 3(a) to 3(f).

First, by a well-known technique, a field oxide film 12 with a thickness of 1.2 μrn was formed on a P-type silicon substrate 11, and an oxide film 11!13 with a thickness of 300 μm was formed. Next, in order to control the threshold voltage, boron was accelerated at a voltage of 30
The substrate 11 was heated under the conditions of f<eV and a dose of 2×10 cm−2.
Ions were implanted into the wafer (as shown in FIG. 3(a)). Next, after depositing a polycrystalline silicon film (not shown) with ρB=30Ω/hole and a thickness of 0.4 μm on the entire surface, a resist (pattern 14
The polycrystalline silicon film is removed using a reactive gas as a mask.
The oxide film 13 was sequentially etched to form a gate electrode 15 with a length of 1.5 μm, and insulating films 1 to 16 (see FIG. 3).
b) As shown). Furthermore, after removing the resist pattern 14, a 0.3 μm thick silicon oxide film (film) 17 containing phosphorus was deposited by CVD.
Heat treatment was performed at 900°C for 20 minutes in nitrogen gas, and the first
In order to form N-type impurity regions 18 and 19 of FIG.
C) As shown).

Next, the silicon oxide film 17 is removed by a reactive etching method to leave the silicon oxide film 17' only on the side walls of the electrode 15 in the gate 1 (as shown in FIG. 3(d)). Next, the goo 1 to the electrode 15 and the silicon oxide film 17
′ as a mask, arsenic is accelerated at a voltage of 40 K e ′V,
Ions were implanted into the substrate 11 at a dose of 1u5×10cm'. Next, after etching the remaining silicon oxide film 17-, heat treatment is performed at 900°C for 40 minutes in oxygen gas, so that ρs50Ω/-1 depth=0.2μ■
A second N+ type impurity region 20.21 was formed. As a result, the source region 22 is formed by the first and second impurity regions 18.20 on one side, and the drain region 23 is formed by the first and second impurity regions 19.21 on the other side. e) As shown).

Furthermore, after depositing a CVD oxide film 24 with a thickness of 0.2μ711 over the entire surface, contact holes 25.25 are formed in the CVD oxide film 24 corresponding to parts of the source and train regions 22.23, respectively, and A+/ '3 + distribution f! 1i26.2
6 was formed to manufacture a MOS l-transistor (3rd
Figure (f) shown).

According to the present invention, as shown in FIG. 3(C), after the silicon oxide film 17 containing phosphorus is deposited on the entire surface, the inside of the silicon oxide film 17 is heated under predetermined conditions. The conventional L
Compared to a D D iM MoS transistor, one ion implantation can be omitted. Therefore, the process can be simplified. Furthermore, for the same reason, damage to the surface of the substrate 11 can be avoided and the transistor characteristics can be improved.

In the above embodiment, a silicon oxide film containing phosphorus was used as the impurity-containing film, but the present invention is not limited thereto.

In the above embodiment, phosphorus was used as an impurity contained in the silicon oxide film, and arsenic was used as an impurity for forming the second impurity region, but other impurities may be used.

In the above embodiment, the case where the present invention is applied to an N-channel type x+ os t-transistor has been described, but similar effects can be expected when applied to a p-channel type most t-transistor.

〔Effect of the invention〕

As detailed above, according to the present invention, the number of ion implantations can be reduced to 1.
The process can be simplified by omitting the steps, and a method for manufacturing a semiconductor device with good characteristics can be provided.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of a conventional N-channel type MOS l-transistor, and Figure 2 is a cross-sectional view of a conventional N-channel type MOS transistor.
11. Cross-sectional views of the OS1-transistor and FIGS. 3(a) to 3(f) are cross-sectional views showing a method for manufacturing an N-channel type MO8l transistor according to an embodiment of the present invention in the order of steps. 11. ...P-type silicon substrate, 12...Field oxide film, 15...Ge-1 electrode, 1G...Ge-1
Insulating film, 17.17″...Silicon oxide film, 18.1
9... N- type impurity region, 2O12]... N+ type impurity region, 22... Source region, 23 Drain region, 24... CV D 1ffff conversion, 25...
・"Ntak 1~Hall, 26...AI/Si wiring. Applicant's agent Patent attorney Takehiko Suzue Figure 3

Claims (2)

[Claims] (1) Step 1: Forming electrodes on the # conductivity type semiconductor substrate via an insulating film, forming a film containing impurities of the second conductivity type on the entire surface, and heat treatment. a step of diffusing the impurity from the coating onto the surface of the semiconductor substrate; 19j by reactive etching to leave the film only on the side walls of the electrodes; and using the gate electrode and the remaining film as a mask, a second conductivity type with a higher degree of impurity II than the second impurity is removed. 1. A method for manufacturing a semiconductor device, comprising the step of introducing impurities into the substrate. (2) The method for manufacturing a semiconductor device according to claim 1, characterized in that phosphorus or arsenic is used as the impurity of the 21st #electrode type.