JPH0590254A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a method of manufacturing a semiconductor device, where thermal oxide films different in thickness can be formed on a semiconductor substrate or a semiconductor film without increasing manufacturing processes in number. CONSTITUTION:A first process where a nitriding preventive film 9 is formed on a silicon substrate 1 in a cell region A, a second process where the surface of a silicon substrate in a peripheral circuit region B is nitrided in an atmosphere of ammonia, a third process where the nitriding preventive film 9 is removed, and a fourth process where thermal oxide films 12a and 12 are formed on the silicon substrate in both the cell region A and the peripheral circuit region B are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a step of forming thermal oxide films having different thicknesses.

[0002]

2. Description of the Related Art In the manufacture of semiconductor devices, it is sometimes desired to form thermal oxide films having different thicknesses on different regions of a semiconductor substrate or semiconductor film for the purpose of improving reliability and performance. For example, in the case of DRAM, it is desired to make the gate oxide film of the MOS transistor in the cell region for storing information thicker than that of the MOS transistor in the peripheral circuit for processing information. This is because the cell region is mostly occupied by the MOS transistors that make up the DRAM, so it is better for the gate oxide film to be thicker from the viewpoint of reliability. On the other hand, the peripheral circuit does not have many MOS transistors. It is not necessary to make the gate oxide film thick to ensure reliability, but rather the gate oxide film is preferably thin in order to improve performance, that is, to increase the processing speed.

However, in practice, the thickness of the gate oxide film is not so changed between the cell region and the peripheral circuit. That is, the thickness of the gate insulating film is set to M in the cell region.
In many cases, reliability was ensured according to the OS transistor, and performance was sacrificed. This is because it is difficult to form gate insulating films having different film thicknesses in the same thermal oxidation process in the channel regions having a small difference in impurity concentration. Therefore, the thermal oxidation process is performed for each film thickness. This is because the oxide film must be formed, which causes an increase in the number of manufacturing steps. D
Due to the higher integration of RAM, it is expected that the number of DRAM manufacturing steps will increase in the future, and the cost will increase accordingly. Therefore, from the viewpoint of suppressing the increase in the number of steps, the number of steps by the thermal oxidation step increases. Is unacceptable.

[0004]

As described above, the DRAM
It is desirable that the thickness of the gate oxide film in the cell region and the thickness in the peripheral circuit are different from each other.
Since the DRAM is formed according to the thickness of the oxide film, there is a problem that performance such as processing speed is sacrificed.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a thermal oxide film having a different film thickness on a semiconductor substrate or a semiconductor film without increasing the number of manufacturing steps. It is an object of the present invention to provide a method for manufacturing a semiconductor device, the method including the step of forming a semiconductor.

[0006]

The essence of the present invention is to control the deposition rate of a thermal oxide film to form thermal oxide films having different thicknesses in the same thermal oxidation process.

In other words, in order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises a step of selectively nitriding a desired surface of a semiconductor substrate and a heat treatment for forming a film on the semiconductor substrate. And a step of forming different thermal oxide films.

Another method of manufacturing a semiconductor device according to the present invention comprises a step of selectively implanting ions on a surface of a semiconductor substrate or a desired region on the surface of the semiconductor substrate, and a heat treatment with different thicknesses on the semiconductor substrate. And a step of forming an oxide film.

[0009]

In the method of manufacturing a semiconductor device of the present invention, for example,
By providing the nitriding prevention film, the desired surface of the semiconductor substrate or the semiconductor film is nitrided. The present inventors have found that when nitriding is performed, almost no thermal oxide film is formed in the initial stage of thermal oxidation. On the other hand, when nitriding is not performed, a thermal oxide film is monotonically formed from the start of thermal oxidation. Therefore, if the nitrided portion and the non-nitrided portion are subjected to thermal oxidation at the same time, the thermal oxide film in the nitrided portion becomes thicker, and a different film is obtained by one thermal oxidation. A thick thermal oxide film can be formed.

According to another method of manufacturing a semiconductor device of the present invention,
For example, ions are implanted into a desired region of the semiconductor substrate or the semiconductor film by providing an ion implantation prevention film. Point defects are formed in the ion-implanted part, and some of these point defects diffuse to the surface during heat treatment, and the oxidation rate of the ion-implanted part is higher than that of the non-ion-implanted part. Get faster Therefore, if the ion-implanted portion and the non-implanted portion are thermally oxidized at the same time, the film thickness of the thermally-oxidized film at the ion-implanted portion becomes thicker, and the film thickness is different by one thermal oxidation. The thermal oxide film can be formed. In the present invention, the semiconductor substrate also includes a substrate having a semiconductor film provided on the surface thereof.

[0011]

Embodiments will be described below with reference to the drawings. 1 to 7 are cross-sectional views of manufacturing steps of a CMOS integrated circuit according to an embodiment of the present invention.

First, as shown in FIG. 1, the specific resistance is 10Ω.
cm, and the surface is a (100) plane p-type silicon substrate 1,
The p well 2 and the n well 3 are formed by a known method, and then the element formation region (cell region A, peripheral circuit region B) is divided by the silicon oxide film 4. Then cell area A
A trench is formed in the p-well 2 to form a trench capacitor. That is, n ^{− is formed on} the bottom and side walls of this groove. After the layer 5 and the capacitor insulating film 6 are sequentially formed, the groove is filled with a conductive material, and the conductive material is patterned into an electrode shape to form a capacitor electrode 7.

Next, as shown in FIG. 2, a thermal oxide film 8 having a thickness of 15 nm is formed on the exposed surface of the silicon substrate 1. Then, in order to prevent the surface of the silicon substrate 1 in the cell region A from being nitrided in the subsequent nitriding step, a silicon nitride film (Si ₃ N ₄ ) 9 having a thickness of 50 nm is formed on the entire surface as a nitriding prevention film. .. The silicon nitride film 9 can be formed, for example, by the LPCVD method using dichlorosilane (SiH ₂ Cl ₂ ) and ammonia (NH ₃ ) as source gases.
Next, a photoresist 10 is applied on the silicon nitride film 9, and then the photoresist 10 is processed by a photolithography process and a photoetching process to leave the photoresist 10 only in the cell region A.

Next, as shown in FIG. 3, the remaining photoresist 10 is used as a mask to selectively remove the silicon nitride film 9 in the peripheral circuit region B by wet etching using a heated phosphoric acid solution. Next, after removing the photoresist 10, the surface 11 of the silicon substrate 1 in the peripheral circuit region B is selected via the thermal oxide film 8 by exposing the silicon substrate 1 to an ammonia atmosphere at 900 ° C. and 1 atm for 1 minute, for example. Nitriding.

Next, as shown in FIG. 4, the silicon nitride film 9 in the cell region A is removed by etching with a heated phosphoric acid solution, and then the thermal oxide film 8 is removed by etching with a diluted hydrofluoric acid solution. .

Next, as shown in FIG. 5, oxidation is performed for 10 minutes at 950 ° C. in a gas atmosphere having a flow ratio of hydrogen and oxygen of 1:10 to form thermal oxide films 12a and 12b. At this time, the film thickness of the thermal oxide film 12a on the cell region A is 15 nm.
Then, the film thickness of the thermal oxide film 12b on the peripheral circuit region B is 8 nm.
Met. That is, thermal oxide films having different film thicknesses could be formed on different regions by one thermal oxidation.

The thermal oxide films having different thicknesses are formed in this step because the time until the oxidation starts is longer in the silicon nitride film than in the silicon film. Therefore, since the film formation start time of the thermal oxide film 12b is delayed on the peripheral circuit region B where the substrate surface 11 is nitrided and the silicon nitride film is formed, the surface of the silicon substrate 1 in the cell region A and the peripheral circuit region B is delayed. On the other hand, if the oxidation is performed for the same time, the film thickness of the thermal oxide film 12b in the peripheral circuit region B becomes smaller than that of the thermal oxide film 12a in the cell region A.

FIG. 8 is a characteristic diagram showing the difference in the process of forming the thermal oxide film depending on the presence or absence of nitriding on the surface of the silicon substrate. Figure 8
(A) is a characteristic diagram showing the relationship between the oxidation time and the oxide film thickness when wet-oxidizing a silicon substrate whose surface is not nitrided, and the H ₂ / O ₂ flow rate ratio is 0.5, 0.22,
It is shown for three cases of 0.11. Figure 8 (b)
Forms a 14 nm-thick thermal oxide film on the surface of a silicon substrate, heat-treats it in an ammonia atmosphere at 1000 ° C. for 1 minute to nitrid the silicon substrate surface through the thermal oxide film, and then waits for oxidation. It is a characteristic view showing the relationship with the oxide film thickness, H ₂ / O ₂ flow ratio of 0.5,0.2
Two cases of 2 and 0.11 are shown.

From FIG. 8A, when the surface of the silicon substrate is not nitrided, the oxide film thickness is proportional to the oxidation time and monotonically increases regardless of the H ₂ / O ₂ flow rate ratio. I understand. On the other hand, when nitriding the surface of the silicon substrate from FIG. 8 (b), the first two are given for a certain period from the oxidation start time, for example, when the H ₂ / O ₂ flow rate ratio is 0.11.
It can be seen that the oxidation hardly progresses for 6.5 minutes and the oxide film thickness becomes almost constant, and thereafter, the oxide film thickness increases in proportion to the oxidation time as in the case where the surface of the silicon substrate is not nitrided. After the above steps, the same CM as before
The process of forming the OS integrated circuit is started.

That is, as shown in FIG. 6, silane (Si
The H ₄₎ a LPCVD method using a raw material gas, thickness 4
After depositing a polycrystalline silicon film 13 of 00 nm on the entire surface,
BF ₂ ions are applied to the polycrystalline silicon film 13 at an accelerating voltage of 4
Implantation is performed under the conditions of 0 keV and a dose amount of 1 × 10 ¹⁵ nm ^-2 . Next, after depositing an SOG film (coating type silicon oxide film) 14 on the polycrystalline silicon film 13, the SOG film 14 is deposited.
A photoresist (not shown) is applied on top, and then a photolithography process and a photoetching process are performed to leave the photoresist only in the region on the p channel. Then, using the remaining photoresist as a mask, the SOG film 14 is etched by reactive ion etching (RIE). As a result, the polycrystalline silicon film 13 on the p well 2 is exposed. Next, the temperature of the silicon substrate 1 containing phosphorus oxychloride (POCl ₃ ) and oxygen is 850 ° C.
The phosphorus concentration in the exposed polycrystalline silicon film 13 is made higher than that of boron to form the n-type polycrystalline silicon film 13 by heat treatment in the gas atmosphere of S.
Boron in the polycrystalline silicon film 13 below the OG film 14 is activated to form the n-type polycrystalline silicon film 13.

Next, as shown in FIG. 7, S using a hydrofluoric acid solution.
After removing the OG film 14, the polycrystalline silicon film 13 is gated.
The electrode is patterned like an electrode. Next, after forming the n-type source and drain 16 and the p-type source and drain 17,
The insulating film 15 is deposited on the entire surface. Then, after opening a contact hole in the insulating film 15 on the source / drain region,
The extraction electrode 18 is formed.

As described above, according to this embodiment, by utilizing the difference in the film formation start time of the thermal oxide film depending on the presence or absence of nitriding on the surface of the silicon substrate 1, the cell region can be formed by one thermal oxidation process. A, the thermal oxide film 12a having a thick film thickness and the thermal oxide film 12b having a thin film thickness on the peripheral circuit B region B, that is,
A gate insulating film having a film thickness suitable for each MOS transistor can be formed, so that a highly reliable and high performance CMOS integrated circuit can be formed without increasing the number of manufacturing steps.

In this embodiment, the surface 11 of the silicon substrate 1 is nitrided by utilizing the thermal nitriding reaction using ammonia, but a nitriding agent other than ammonia may be used. Further, the silicon substrate 1 may be nitrided by another method instead of the thermal nitriding reaction. For example, the silicon substrate 1 may be nitrided by a plasma nitriding method in which activated species are generated by plasma and this is used as a nitriding agent. Further, although the silicon nitride film (Si ₃ N ₄ ) 9 is used as the nitriding prevention film in this embodiment, another film, for example, a film made of polycrystalline silicon may be used. 9 and 10 are sectional views of a manufacturing process of a CMOS integrated circuit according to another embodiment of the present invention.

The manufacturing method of this embodiment is different from that of the previous embodiment in that the oxidation start time is controlled by implanting ions into the silicon substrate instead of nitriding the silicon substrate.

That is, as shown in FIG. 9, after forming a trench capacitor in the same manner as in the previous embodiment (FIG. 1), a photoresist 19 is applied on the entire surface and patterned to form only the peripheral circuit region B. Leave on. Then, using the photoresist 19 as a mask, an acceleration voltage of 40 keV and a dose amount of 1 × 10
^Under the conditions of ¹⁶ , Si ions 20 are implanted into the silicon substrate 1 where the surface of the cell region A is exposed. As a result, the cell area A
A large number of interstitial atoms and point defects 22 such as vacancies are formed in the silicon substrate 1.

Next, as shown in FIG. 10, photoresist 1
After removing 9, the silicon substrate 1 is thermally oxidized for 5 minutes at 950 ° C. under the condition that the flow rate ratio of hydrogen and oxygen is 1:10. Thermal oxide film 21 having a thickness of 15 nm and 10 nm
a and 21b are formed. The thermal oxide film 21a in the cell region A is thicker than the thermal oxide film 21b in the peripheral circuit region B because the silicon substrate 1 in the cell region A is formed in the thermal oxidation process.
This is because the point defect 22 therein diffuses to the substrate surface and the oxidation rate increases. Thereafter, the gate electrode, the source / drain diffused region, and the lead electrode are formed by the same steps as in the previous embodiment to complete the CMOS integrated circuit.

Thus, in this embodiment, by controlling the oxidation start time depending on the presence or absence of the point defect 22, the thermal oxide films 21a and 21b having different film thicknesses can be formed, and the same effect as the previous embodiment can be obtained.

The present invention is not limited to the above embodiment. For example, selective nitriding or ion implantation may be performed by implanting ions of nitrogen, silicon or the like with a mask provided separately. Further, although the case of the silicon substrate has been described in the above embodiment, thermal oxide films having different film thicknesses can be similarly formed in different regions in other semiconductor substrates. Furthermore, the present invention can be applied to semiconductor devices other than CMOS integrated circuits. Further, even in the case of a semiconductor substrate in which a semiconductor film is provided on the semiconductor substrate, thermal oxide films having different film thicknesses can be similarly formed in the same thermal oxidation process. Besides, various modifications can be made without departing from the scope of the present invention.

[0029]

As described above in detail, according to the present invention, by controlling the film formation start time of the thermal oxide film, thermal oxide films having different film thicknesses can be formed in the same thermal oxidation process. Therefore, a thermal oxide film having an appropriate film thickness can be formed on each element without increasing the number of manufacturing steps.

[Brief description of drawings]

FIG. 1 is a sectional view of a manufacturing process of a CMOS integrated circuit according to an embodiment of the present invention.

FIG. 2 is a sectional view of a manufacturing process of a CMOS integrated circuit according to an embodiment of the present invention.

FIG. 3 is a sectional view of a manufacturing process of a CMOS integrated circuit according to an embodiment of the present invention.

FIG. 4 is a sectional view of a manufacturing process of a CMOS integrated circuit according to an embodiment of the present invention.

FIG. 5 is a sectional view of a manufacturing process of a CMOS integrated circuit according to an embodiment of the present invention.

FIG. 6 is a sectional view of a manufacturing process of a CMOS integrated circuit according to an embodiment of the present invention.

FIG. 7 is a sectional view of a manufacturing process of a CMOS integrated circuit according to an embodiment of the present invention.

FIG. 8 is a characteristic diagram showing a relationship between an oxidation time and an oxide film.

FIG. 9 is a sectional view of a manufacturing process of a CMOS integrated circuit according to another embodiment of the present invention.

FIG. 10 is a sectional view of a manufacturing process of a CMOS integrated circuit according to another embodiment of the present invention.

[Explanation of symbols]

1 ... Silicon substrate 1, 2 ... P well, 3 ... N well, 4
... silicon oxide film, 5 ... n ^- Layer, 6 ... Capacitor insulating film, 7 ... Capacitor electrode, 8 ... Thermal oxide film, 9 ... Silicon nitride film, 10 ... Photoresist, 11 ... Nitrided surface, 12
a, 12b ... Thermal oxide film, 13 ... Polycrystalline silicon film, 14
... SOG film, 15 ... Insulating film, 16, 17 ... Source / drain region, 18 ... Extraction electrode, 19 ... Photoresist, 20 ... Si ion, 21a, 21b ... Thermal oxide film, 2
2 ... Point defect.

Claims (2)

[Claims] 1. A semiconductor device comprising: a step of selectively nitriding a desired surface of a semiconductor substrate; and a step of forming a thermal oxide film having a different thickness on the semiconductor substrate by heat treatment. Production method. 2. A step of selectively implanting ions on a surface of a semiconductor substrate or a desired region on the surface, and a step of forming a thermal oxide film having a different thickness on the semiconductor substrate by heat treatment. And a method for manufacturing a semiconductor device.