KR100422325B1 - Fabricating method of semiconductor device - Google Patents
Fabricating method of semiconductor device Download PDFInfo
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- KR100422325B1 KR100422325B1 KR10-2002-0032860A KR20020032860A KR100422325B1 KR 100422325 B1 KR100422325 B1 KR 100422325B1 KR 20020032860 A KR20020032860 A KR 20020032860A KR 100422325 B1 KR100422325 B1 KR 100422325B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000000034 method Methods 0.000 title claims description 19
- 239000000758 substrate Substances 0.000 claims abstract description 55
- 239000001301 oxygen Substances 0.000 claims abstract description 46
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 46
- -1 oxygen ions Chemical class 0.000 claims abstract description 46
- 238000002955 isolation Methods 0.000 claims abstract description 36
- 150000002500 ions Chemical class 0.000 claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 claims abstract description 22
- 230000001590 oxidative effect Effects 0.000 claims abstract description 3
- 238000002513 implantation Methods 0.000 claims description 13
- 238000010438 heat treatment Methods 0.000 claims description 9
- 239000012299 nitrogen atmosphere Substances 0.000 claims 3
- 230000003213 activating effect Effects 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 7
- 239000002019 doping agent Substances 0.000 description 6
- 239000012535 impurity Substances 0.000 description 5
- 230000003064 anti-oxidating effect Effects 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical group N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
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Abstract
본 발명은 웰(Well) 하부에 산화막을 형성시켜 누설 전류 및 래치업(Latch up) 현상을 개선시킬 수 있는 반도체 소자의 제조방법에 관한 것으로서, 본 발명의 반도체 소자의 제조방법은 활성 영역과 소자 분리 영역으로 구분되는 절연 기판의 소자 분리 영역에 소자 분리막을 형성하는 단계와, 상기 기판 전면에 산소 이온을 주입하여 기판의 소정 깊이 내에 산소 이온층을 형성하는 단계와, 상기 기판 전면에 웰 이온을 주입하여 상기 산소 이온층의 상부에 웰을 형성하는 단계와, 상기 기판을 열처리하여 웰을 활성화시킴과 동시에 상기 산소 이온층을 산화시켜 소정의 산화막층을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.The present invention relates to a method of manufacturing a semiconductor device capable of improving leakage current and latch-up phenomenon by forming an oxide film under a well, and the method of manufacturing a semiconductor device of the present invention includes an active region and a device. Forming an isolation layer in an isolation region of the insulating substrate divided into isolation regions, implanting oxygen ions into the entire surface of the substrate to form an oxygen ion layer within a predetermined depth of the substrate, and implanting well ions into the entire surface of the substrate; Forming a well on top of the oxygen ion layer, activating the well by heat treating the substrate, and oxidizing the oxygen ion layer to form a predetermined oxide layer.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로서, 특히 웰(Well) 하부에 산화막을 형성시켜 누설 전류 및 래치업(Latch up) 현상을 개선시킬 수 있는 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device capable of improving leakage current and latch-up by forming an oxide film under a well.
N-채널 모스(metal oxide semiconductor; MOS) 트랜지스터와 P-채널 모스 트랜지스터가 동일한 반도체 기판 상에 형성되는 상보형 모스(complementary MOS; CMOS) 소자에서는 상기 N-채널 모스 트랜지스터와 P-채널 모스 트랜지스터를 기판 내부에서 전기적으로 분리하기 위하여 어느 한 소자를 기판과 반대 도전형의 불순물 영역에 형성하여야 하며, 이러한 불순물 영역을 웰(Well)이라 한다.In a complementary MOS (CMOS) device in which an N-channel metal oxide semiconductor (MOS) transistor and a P-channel MOS transistor are formed on the same semiconductor substrate, the N-channel MOS transistor and the P-channel MOS transistor are formed. In order to electrically separate the inside of the substrate, any element must be formed in an impurity region of a conductivity type opposite to that of the substrate, and such an impurity region is called a well.
통상적으로 상기 웰을 도판트(dopant)를 이온 주입한 후, 고온 장시간의 열처리 공정을 거쳐 사기 이온 주입된 도판트를 적절한 깊이까지 확산시킴으로써 형성한다. 이러한 웰을 확산 웰이라 하는데 이 방법에 의하면 확산이 기판의 종방향뿐만 아니라 횡방향으로도 진행되기 때문에 집적도가 떨어지는 문제가 발생한다.Typically, the wells are formed by ion implanting a dopant and then diffusing the dopant implanted with a fraudulent ion implant to a suitable depth through a high temperature and long heat treatment process. Such a well is called a diffusion well, and according to this method, a problem arises in that the density decreases because the diffusion proceeds not only in the longitudinal direction but also in the transverse direction of the substrate.
이에 따라, 소자 분리막을 먼저 형성한 후 도판트가 적절한 깊이에 위치하도록 고에너지 이온 주입에 의해 웰을 형성하는 방법이 개발되었는데, 상기한 웰은 반도체 기판 내의 소정 깊이에서 불순물 농도의 피크(peak)치가 나타나고 기판 표면으로 갈수록 불순물 농도가 감소하기 때문에, 리트로그레이드 웰(retrograde well)이라 한다. 상기 리트로그레이드 웰은 웰 형성시에 종래의 확산 웰에서 사용되는 고온, 장시간의 확산 공정이 생략되어 공정이 단순화되고 공정 원가 절감에 큰 기여를 하며, 래치업 및 소프트 에러율(soft error rate) 등을 억제시켜 소자의 전기적 특성을 향상시키는 장점을 갖는다.Accordingly, a method of forming a well by forming an isolation layer first and then forming a well by high energy ion implantation so that the dopant is positioned at an appropriate depth has been developed. The well has a peak of impurity concentration at a predetermined depth in the semiconductor substrate. Are referred to as retrograde wells because they appear and the impurity concentration decreases toward the substrate surface. The retrolled well simplifies the process and greatly contributes to the process cost by eliminating the high temperature and long diffusion processes used in the conventional diffusion wells when forming the wells, and providing latch up and soft error rates. Suppression has the advantage of improving the electrical characteristics of the device.
그러나, 상술한 리트로그레이드 웰을 적용한 반도체 소자에 있어서 도판트 주입을 실시한 후 모스 트랜지스터를 형성할 때까지 이온 주입에 의한 손상을 큐어링(curing)하기 위한 어닐링 공정 및 고온 산화막과 같은 절연층의 형성 공정 등에서 열처리를 받아 도판트가 확산되는 문제점이 있으며, 도판트의 확산에 따라소스/드레인과 게이트 전극과의 오버랩이 야기되어 누설 전류를 유발하게 된다.However, in the above-described semiconductor device to which the retrode well is applied, an annealing process for curing the damage caused by ion implantation until the MOS transistor is formed after the dopant implantation and the formation of an insulating layer such as a high temperature oxide film There is a problem in that a dopant is diffused by heat treatment in a process or the like, and an overlap of a source / drain and a gate electrode is caused by the diffusion of the dopant, causing leakage current.
이러한 문제점을 해결하기 위해 상기의 리트로그레이드 웰 이외에도 여러 종류의 웰이 개발되었으나 누설 전류 및 래치업의 문제를 완전히 해소하지는 못했다.In order to solve this problem, a number of wells have been developed in addition to the above retrolled wells, but they have not completely solved the problems of leakage current and latchup.
본 발명은 상기와 같은 문제점을 해결하기 위해 안출한 것으로서, 웰(Well) 하부에 산화막을 형성시켜 누설 전류 및 래치업(Latch up) 현상을 개선시킬 수 있는 반도체 소자의 제조방법을 제공하는 것을 목적으로 한다.Disclosure of Invention The present invention has been made to solve the above problems, and an object of the present invention is to provide a method of manufacturing a semiconductor device that can improve leakage current and latch-up phenomenon by forming an oxide film under a well. It is done.
도 1 내지 도 3은 본 발명의 제 1 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정단면도.1 to 3 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.
도 4 내지 도 6은 본 발명의 제 2 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정단면도.4 to 6 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.
도 7 내지 도 9는 본 발명의 제 3 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정단면도.7 through 9 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a third embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
101 : 절연 기판 102 : 소자 분리막101: insulating substrate 102: device isolation film
104 : 웰 105 : 산화막층104: well 105: oxide film layer
상기와 같은 목적을 달성하기 위한 본 발명의 반도체 소자의 제조방법은 활성 영역과 소자 분리 영역으로 구분되는 절연 기판의 소자 분리 영역에 소자 분리막을 형성하는 단계와, 상기 기판 전면에 산소 이온을 주입하여 기판의 소정 깊이 내에 산소 이온층을 형성하는 단계와, 상기 기판 전면에 웰 이온을 주입하여 상기 산소 이온층의 상부에 웰을 형성하는 단계와, 상기 기판을 열처리하여 웰을 활성화시킴과 동시에 상기 산소 이온층을 산화시켜 소정의 산화막층을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.The method of manufacturing a semiconductor device of the present invention for achieving the above object comprises the steps of forming a device isolation film in the device isolation region of the insulating substrate divided into an active region and the device isolation region, by implanting oxygen ions on the entire surface of the substrate Forming an oxygen ion layer within a predetermined depth of the substrate, implanting well ions into the entire surface of the substrate to form a well on top of the oxygen ion layer, and heat treating the substrate to activate the well and simultaneously And oxidizing to form a predetermined oxide film layer.
본 발명의 다른 실시예는 활성 영역과 소자 분리 영역으로 구분되는 절연 기판의 소자 분리 영역에 소자 분리막을 형성하는 단계와, 상기 기판 전면에 산소 이온을 주입하여 기판의 소정 깊이 내에 산소 이온층을 형성하는 단계와, 상기 기판을 열처리하여 상기 산소 이온층을 산화시켜 소정의 산화막층을 형성하는 단계와, 상기 소정의 산화막층이 형성된 기판 상에 웰 이온을 주입하여 상기 산화막층 상부에 웰을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.Another embodiment of the present invention is to form a device isolation layer in the device isolation region of the insulating substrate divided into the active region and the device isolation region, and implanting oxygen ions on the entire surface of the substrate to form an oxygen ion layer within a predetermined depth of the substrate Heat treating the substrate to oxidize the oxygen ion layer to form a predetermined oxide layer, and implanting well ions onto the substrate on which the predetermined oxide layer is formed to form a well on the oxide layer. It is characterized by comprising.
본 발명의 또 다른 실시예는 활성 영역과 소자 분리 영역으로 구분되는 절연 기판의 소자 분리 영역에 소자 분리막을 형성하는 단계와, 상기 기판 전면에 웰 이온을 주입시켜 상기 활성 영역에 웰을 형성하는 단계와, 상기 기판 전면에 산소 이온을 주입시켜 상기 웰의 하부에 산소 이온층을 형성하는 단계와, 상기 기판을 열처리하여 상기 산소 이온층을 산화시켜 소정의 산화막층을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.According to another embodiment of the present invention, forming an isolation layer in an isolation region of an insulating substrate divided into an active region and an isolation region and implanting well ions into the entire surface of the substrate to form a well in the active region And injecting oxygen ions into the entire surface of the substrate to form an oxygen ion layer at the bottom of the well, and heat treating the substrate to oxidize the oxygen ion layer to form a predetermined oxide layer. do.
이하, 도면을 참조하여 본 발명의 반도체 소자의 제조방법을 상세히 설명하기로 한다.Hereinafter, a method of manufacturing a semiconductor device of the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 3은 본 발명의 제 1 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정단면도이다.1 to 3 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.
먼저, 도 1에 도시한 바와 같이, 절연 기판(101)의 상부에 산화방지 마스크(도시하지 않음)를 형성하여 활성 영역(b)과 소자분리 영역(a)이 형성될 부위를 구분한 후 LOCOS(Local Oxidation of Silicon) 또는 STI(Shallow Trench Isolation) 등의 방법을 이용하여 소자 분리막(102)을 형성한다. 그 결과, 상기 산화방지 마스크가 형성되어 있는 부위는 산화가 억제되어 활성 영역이 되며, 상기 소자 분리막(102)이 형성된 부위는 소자 분리 영역이 된다.First, as shown in FIG. 1, an anti-oxidation mask (not shown) is formed on the insulating substrate 101 to classify the region where the active region b and the device isolation region a are to be formed, and then LOCOS. The device isolation layer 102 is formed using a method such as (Local Oxidation of Silicon) or Shallow Trench Isolation (STI). As a result, the site where the anti-oxidation mask is formed is inhibited from oxidation to become an active region, and the site where the device isolation layer 102 is formed becomes a device isolation region.
이어서, 상기 기판(101) 전면 상에 산소 이온을 주입하여 상기 기판의 소정 깊이에 산소 이온층(103)을 형성한다. 상기 산소 이온의 주입시 주입에너지는1∼3MeV, 주입량은 1E15∼5E16 ion/cm2가 적당하다. 상기 산소 이온층(103)의 형성되는 부위는 후술하는 웰의 형성부위의 하부에 해당된다.Subsequently, oxygen ions are implanted on the entire surface of the substrate 101 to form an oxygen ion layer 103 at a predetermined depth of the substrate. When the oxygen ion is implanted, the implantation energy is 1 to 3MeV, and the implantation amount is 1E15 to 5E16 ion / cm 2 . The portion where the oxygen ion layer 103 is formed corresponds to the lower portion of the well portion to be described later.
이어, 도 2에 도시한 바와 같이, 상기 산소 이온층(103)이 형성된 기판(101) 전면에 웰 이온을 주입시켜 상기 활성 영역(b)의 산소 이온층(103)의 상부에 웰(104)을 형성한다. 이 때 주입되는 상기 웰 이온은 모스 트랜지스터의 종류에 따라 P형 또는 N형 불순물이 될 수 있다. 마지막으로, 도 3에 도시한 바와 같이 상기 산소 이온층(103)과 웰(104)이 형성된 기판(101)을 급속 열처리(Rapid Thermal Process)하여 상기 웰 이온을 활성화시킴과 동시에 상기 산소 이온층을 산화시켜 소정의 두께를 갖는 산화막층(105)을 형성한다. 이 때, 열처리시의 조건은 온도는 1000∼1100℃, 시간은 10∼30초, 분위기는 질소(N2) 분위기이다.Subsequently, as illustrated in FIG. 2, well ions are implanted into the entire surface of the substrate 101 on which the oxygen ion layer 103 is formed to form the well 104 on the oxygen ion layer 103 in the active region b. do. The well ions implanted at this time may be P-type or N-type impurities, depending on the type of MOS transistor. Finally, as shown in FIG. 3, a rapid thermal process is performed on the substrate 101 on which the oxygen ion layer 103 and the well 104 are formed to activate the well ions and simultaneously oxidize the oxygen ion layer. An oxide film layer 105 having a predetermined thickness is formed. Conditions in this case, the heat treatment temperature of 1000~1100 ℃, time 10 to 30 seconds, the atmosphere is nitrogen (N 2) atmosphere.
이와 같이 구성되는 본 발명의 반도체 소자의 제조방법은 웰 하부에 산소 이온을 주입시켜 후속 열처리 공정시 상기 산소 이온들을 산화시킴으로써 소정의 산화막층을 형성한다. 웰 하부에 상기와 같이 소정의 산화막층이 형성됨에 따라 웰 이온이 확산되는 것을 방지할 수 있게 되고 래치업 현상을 개선시킬 수 있게 된다.In the method of manufacturing a semiconductor device of the present invention configured as described above, a predetermined oxide layer is formed by injecting oxygen ions into a lower portion of a well to oxidize the oxygen ions during a subsequent heat treatment process. As the predetermined oxide layer is formed in the lower part of the well, diffusion of well ions can be prevented and the latch-up phenomenon can be improved.
이하에서는 본 발명의 제 2 실시예 및 제 3 실시예에 따른 반도체 소자의 제조방법을 상세히 설명하기로 한다.Hereinafter, a method of manufacturing a semiconductor device according to the second and third embodiments of the present invention will be described in detail.
도 4 내지 도 6은 본 발명의 제 2 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정단면도이고, 도 7 내지 도 9는 본 발명의 제 3 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정단면도이다.4 through 6 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention, and FIGS. 7 through 9 illustrate a method of manufacturing a semiconductor device in accordance with a third embodiment of the present invention. It is a process cross section for doing so.
먼저, 본 발명의 제 2 실시예는 도 4에 도시한 바와 같이, 절연 기판(101)의 상부에 산화방지 마스크(도시하지 않음)를 형성하여 활성 영역(b)과 소자분리 영역(a)이 형성될 부위를 구분한 후 LOCOS(Local Oxidation of Silicon) 또는 STI(Shallow Trench Isolation) 등의 방법을 이용하여 소자 분리막(102)을 형성한다. 그 결과, 상기 산화방지 마스크가 형성되어 있는 부위는 산화가 억제되어 활성 영역(b)이 되며, 상기 소자 분리막(102)이 형성된 부위는 소자 분리 영역(a)이 된다.First, as shown in FIG. 4, the anti-oxidation mask (not shown) is formed on the insulating substrate 101 to form the active region b and the device isolation region a. After separating the portions to be formed, the device isolation layer 102 is formed using a method such as LOCOS (Local Oxidation of Silicon) or STI (Shallow Trench Isolation). As a result, the site where the anti-oxidation mask is formed is inhibited from oxidation to become the active region b, and the site where the device isolation layer 102 is formed becomes the device isolation region a.
이어서, 상기 기판(101) 전면 상에 산소 이온을 주입하여 상기 기판의 소정 깊이에 산소 이온층(103)을 형성한다. 상기 산소 이온의 주입시 주입에너지는 1∼3MeV, 주입량은 1E15∼5E16 ion/cm2가 적당하다. 상기 산소 이온층(103)의 형성되는 부위는 후술하는 웰의 형성부위의 하부에 해당된다.Subsequently, oxygen ions are implanted on the entire surface of the substrate 101 to form an oxygen ion layer 103 at a predetermined depth of the substrate. When the oxygen ion is implanted, the implantation energy is 1 to 3MeV, and the implantation amount is 1E15 to 5E16 ion / cm 2 . The portion where the oxygen ion layer 103 is formed corresponds to the lower portion of the well portion to be described later.
이어, 도 5에 도시한 바와 같이, 상기 기판(101)을 급속 열처리하여 상기 산소 이온층(103)을 산화시켜 소정의 산화막층(105)을 형성한다. 이 때, 열처리시의 조건은 온도는 1000∼1100℃, 시간은 10∼30초, 분위기는 질소(N2) 분위기이다. 도 6에 도시한 바와 같이, 상기 기판(101) 전면에 웰 이온을 주입하여 활성 영역에 상기 산화막층(105)의 상부에 상응하는 부위에 웰(104)을 형성한다. 이후, 도면에 도시하지 않았지만 상기 웰이 형성된 기판 상에 게이트 절연막을 형성하고 일반적인 반도체 공정을 진행하면 본 발명의 반도체 소자의 제조방법을 완료하게 된다.Subsequently, as shown in FIG. 5, the substrate 101 is rapidly heat treated to oxidize the oxygen ion layer 103 to form a predetermined oxide film layer 105. Conditions in this case, the heat treatment temperature of 1000~1100 ℃, time 10 to 30 seconds, the atmosphere is nitrogen (N 2) atmosphere. As shown in FIG. 6, well ions are implanted into the entire surface of the substrate 101 to form wells 104 in a region corresponding to the upper portion of the oxide layer 105 in an active region. Subsequently, although not shown in the drawings, a gate insulating film is formed on the substrate on which the well is formed, and a general semiconductor process is performed to complete the manufacturing method of the semiconductor device of the present invention.
본 발명의 제 3 실시예에 따른 반도체 소자의 제조방법을 설명하면 먼저 도7에 도시한 바와 같이, 소자 분리막(102)이 형성되어 있는 절연 기판(101) 전면에 웰 이온을 주입하여 웰(104)을 형성한다. 이어, 도 8에 도시한 바와 같이 절연 기판(101) 전면에 산소 이온을 주입하여 상기 웰(104)이 형성되어 있는 부위의 하부에 소정의 산소 이온층(103)이 형성되도록 한다. 이 때, 상기 산소 이온의 주입시 주입에너지는 1∼3MeV, 주입량은 1E15∼5E16 ion/cm2가 적당하다. 마지막으로 도 9에 도시한 바와 같이, 상기 산소 이온층(103)과 웰(104)이 형성된 기판(101)을 급속 열처리(Rapid Thermal Process)하여 상기 웰 이온을 활성화시킴과 동시에 상기 산소 이온층을 산화시켜 소정의 두께를 갖는 산화막층(105)을 형성한다. 이 때, 열처리시의 조건은 온도는 1000∼1100℃, 시간은 10∼30초, 분위기는 질소(N2) 분위기이다.A method of manufacturing a semiconductor device according to a third exemplary embodiment of the present invention will first be described with reference to FIG. 7, in which well ions are implanted into an entire surface of an insulating substrate 101 on which an isolation layer 102 is formed. ). Subsequently, as illustrated in FIG. 8, oxygen ions are implanted into the entire surface of the insulating substrate 101 so that a predetermined oxygen ion layer 103 is formed below the portion where the well 104 is formed. At this time, the implantation energy of the oxygen ion is 1 to 3MeV, the amount of implantation is 1E15 to 5E16 ion / cm 2 is suitable. Finally, as shown in FIG. 9, a rapid thermal process is performed on the substrate 101 on which the oxygen ion layer 103 and the well 104 are formed to activate the well ions and simultaneously oxidize the oxygen ion layer. An oxide film layer 105 having a predetermined thickness is formed. Conditions in this case, the heat treatment temperature of 1000~1100 ℃, time 10 to 30 seconds, the atmosphere is nitrogen (N 2) atmosphere.
상술한 바와 같은 본 발명의 반도체 소자 제조방법은 다음과 같은 효과가 있다.The semiconductor device manufacturing method of the present invention as described above has the following effects.
웰(Well) 하부에 산화막을 형성시켜 웰 이온이 기판 내부로 확산하는 것을 방지하여 누설 전류 및 래치업(Latch up) 현상을 개선시킬 수 있는 장점이 있다.An oxide film is formed under the well to prevent diffusion of well ions into the substrate, thereby improving leakage current and latch up.
Claims (10)
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0322566A (en) * | 1989-06-20 | 1991-01-30 | Sony Corp | Semiconductor device |
| JPH0645533A (en) * | 1992-07-23 | 1994-02-18 | Nec Corp | Cmos type field effect semiconductor device and its manufacture |
| JPH0774242A (en) * | 1993-09-03 | 1995-03-17 | Fujitsu Ltd | Semiconductor device and fabrication thereof |
| US5795800A (en) * | 1995-06-07 | 1998-08-18 | Sgs-Thomson Microelectronics, Inc. | Integrated circuit fabrication method with buried oxide isolation |
| US5955767A (en) * | 1996-01-24 | 1999-09-21 | Advanced Micro Devices, Inc. | Semiconductor device with self-aligned insulator |
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0322566A (en) * | 1989-06-20 | 1991-01-30 | Sony Corp | Semiconductor device |
| JPH0645533A (en) * | 1992-07-23 | 1994-02-18 | Nec Corp | Cmos type field effect semiconductor device and its manufacture |
| JPH0774242A (en) * | 1993-09-03 | 1995-03-17 | Fujitsu Ltd | Semiconductor device and fabrication thereof |
| US5795800A (en) * | 1995-06-07 | 1998-08-18 | Sgs-Thomson Microelectronics, Inc. | Integrated circuit fabrication method with buried oxide isolation |
| US5795800B1 (en) * | 1995-06-07 | 2000-03-28 | Sgs Thomson Microelectronics | Integrated circuit fabrication method with buried oxide isolation |
| US5955767A (en) * | 1996-01-24 | 1999-09-21 | Advanced Micro Devices, Inc. | Semiconductor device with self-aligned insulator |
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