JPH05226595A - Complementary mis transistor device - Google Patents

Abstract

PURPOSE:To make an element fine by preventing that a characteristic is deteriorated due to a hot carrier effect in an N-ch transistor and that a threshold voltage is dropped due to a short channel effect. CONSTITUTION:A P-type well region 11a formed by being doped with impurities is provided with an impurity distribution in which an effective acceptor impurity concentration is increasd gradually in the depth direction near the surface. N-type diffusion regions 21a, 22a as well as a source 23a and a drain 24a which are formed in the N-type diffusion regions are doped with donor impurities in such a way that an impurity distribution is compensated so as to form an N-conductivity type. Thereby, the depth of the N-type diffusion regions and that of the source or the drain can be constituted to be nearly equal. Thereby, the N-type diffusion regions have a shape which is expanded only in a face direction, and it is possible to restrain a hot carrier effect and a short channel effect.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a complementary insulated gate transistor device having a P-channel and an N-channel at the same time, and particularly to a concentration distribution regarding wells, sources and drains for enabling miniaturization thereof and manufacturing of the device. Regarding the method.

[0002]

2. Description of the Related Art Conventionally, in N-channel (hereinafter abbreviated as "Nch") transistors due to device miniaturization, hot carrier effect, P-channel (hereinafter "Pc")
In a transistor (abbreviated as “h”), the short channel effect is increased. Both of these effects bring about a decrease in the threshold voltage, which hinders the miniaturization of integrated circuits.

Among them, in order to reduce the hot carrier effect in the Nch transistor, an LDD (low impurity density drain) structure in which an N type low impurity density region is formed around an N conductivity type drain is usually adopted. There is. However, in this structure, the mask for forming the drain needs to be longer than the length of the gate electrode. Therefore, it is necessary to form the sidewall oxide film on the side portion of the gate electrode by the CVD method, which complicates the process.

Further, as shown in USP No. 4924277, an electric field relaxation layer for suppressing a hot carrier effect in an Nch transistor and an N-type diffusion layer for simultaneously suppressing a sheet channel effect in a Pch transistor and punch-through stop are provided. A structure formed around the drain and the source has been proposed.

The specific structure is shown in FIG. An N-type well region 51b and a P-type well region 51a are formed on the P-type silicon substrate 50. A Pch transistor is formed in the N-type well region 51b, and the P-type well region 51a is formed.
An Nch transistor is formed in. Each transistor is electrically isolated by an isolation oxide film 56 formed by a local oxidation method (LOCOS). Gate insulating films 57a and 57b are formed on the well regions 51a and 51b, respectively, and gate electrodes 58a and 58b are formed on the gate insulating films 57a and 57b, respectively.

Further, by using the gate electrodes 58a and 58b as a mask, N-type diffusion layers 61a and 62a formed in a self-aligned manner on both sides of each of the gate electrodes 58a and 58b.
And 61b and 62b are formed. The N-type diffusion layers 61a and 62a have high-concentration N-type diffusion layers 63a as sources and high-concentration N as drains, respectively.
The mold diffusion layer 64a is formed. Further, a high-concentration P-type diffusion layer 63b as a source and a high-concentration P-type diffusion layer 64b as a drain are formed in each of the N-type diffusion layers 61b and 62b.

N-type diffusion layers 61a, 62a, 61b, 62
b is deeper in the depth direction and laterally than the high-concentration N-type diffusion layer 63a, the high-concentration N-type diffusion layer 64a, the high-concentration P-type diffusion layer 63b, and the high-concentration P-type diffusion layer 64b. Is formed in a shape that widens. Also, the N-type diffusion layer 6
The impurity concentrations of 1a, 62a and 61b, 62b are P type well region 51a and N type well region 51b, respectively.
Of the high-concentration N-type diffusion layers 63a, 6a
4a and the high-concentration P-type diffusion layers 63b and 64b.

In the above structure, in the Nch transistor, the N-type diffusion layer 62a functions as an electric field relaxation layer in a high electric field generation region due to pinch-off near the drain, and suppresses deterioration of device characteristics due to drain avalanche injection as a hot carrier effect. To be done. Further, in the Pch transistor, since a polycrystalline silicon containing a high concentration of phosphorus is usually used as the material of the gate electrode 58b, it has a buried channel structure. As a result, a PN junction is formed directly under the gate of the channel portion, and punch through easily occurs. Therefore, in the Pch transistor,
Likely short channel effect occurs more than the Nch transistor, this N-type diffusion layer 62b has the effect of suppressing element hypofunction of V _t decreases such to serve as a punch-through stopper.

[0009]

However, in this structure, in order to sufficiently suppress the hot carrier effect of the Nch transistor, the N functioning as the electric field relaxation layer is formed.
In order to sufficiently form the type diffusion layer 62a, the depth becomes deep in the depth direction, and diffusion for a long time is required. Therefore, it becomes difficult to form a drain with good controllability as miniaturization progresses, a short channel effect occurs, and stable threshold value control becomes difficult in the manufacturing process.

The present invention has been made to solve the above problems, and an object thereof is to simultaneously improve the characteristics of the Nch transistor due to the hot carrier effect and to reduce the threshold voltage due to the short channel effect. It is to effectively suppress and achieve miniaturization and speedup of a semiconductor device.

[0011]

The structure of the first invention is P
The P-type well region and the N-type well region are formed at the positions where the source and drain are formed in the N-type well region and the N-type well region.
A complementary MIS having an N-type diffusion region having a higher impurity concentration than the type well region, a lower impurity concentration than the source and drain, and a wider diffusion region than the source and drain.
In the transistor device, the P-type well region formed by the impurity doping has an impurity distribution in the vicinity of the surface such that the effective acceptor impurity concentration gradually increases in the depth direction. The source and drain formed in the type diffusion region are doped with a donor impurity so that the impurity distribution is compensated to be N-conductivity type, so that the N-type diffusion region and the source or drain have substantially the same depth. It is characterized by having done.

A second aspect of the present invention is the method of manufacturing a complementary MIS transistor device described above, wherein a region for forming the P-type well region and the N-type well region of the P-type semiconductor substrate is doped with a donor impurity and then doped. The doped region is made to be N-conductivity type, and the portion forming the N-type well region is masked, and only the portion forming the P-type well region is doped with acceptor impurities to the extent that the already doped donor impurity density is overcompensated. Then, the doped region is made to have a P-conductivity type, and then the semiconductor substrate is heat-treated, so that the effective impurity acceptor impurity concentration gradually increases in the depth direction near the surface of the P-type well region. Formed into
Donor impurities are diffused in the P-type well region and the N-type well region using the gate electrode as a mask to form an N-type diffusion region, and in the N-type diffusion region of the P-type well region and the N-type diffusion region of the N-type well region, The gate electrode is used as a mask to diffuse a donor impurity and an acceptor impurity to form a source and a drain, respectively.

[0013]

Since the P-type well region is formed with an impurity distribution such that the effective acceptor impurity concentration gradually increases in the depth direction near the surface, one of the donor impurities doped when the N-type diffusion region is formed is formed. The parts are used to compensate for the effective acceptor impurities so distributed. Therefore, the effective donor distribution in the depth direction of the N-type diffusion region can be sharply reduced, and the depth of the N-type diffusion region can be reduced. On the other hand, in the P-type well region beyond the N-type diffusion region, the effective acceptor impurity concentration distribution is close to the boundary with the N-type diffusion region because of the compensation by the donor impurities at the time of forming the N-type diffusion region. , The distribution is such that the effective acceptor concentration rapidly increases. As a result, the donor doped at the time of forming the source and the drain is also compensated by the acceptor impurities that sharply increase at the boundary near the boundary with the N-type diffusion region, so that the P-type well region becomes N-conductivity type beyond the boundary. It doesn't change. In other words, it becomes easy to control the impurity doping at the time of forming the N-type diffusion region, the source and the drain. As a result, the depths of the N-type diffusion region, the source and the drain are substantially equal to each other.

On the other hand, the method of the second invention described above was invented as a method of forming the P-type well region in the vicinity of the surface in an impurity distribution in which the effective acceptor impurity concentration gradually increases in the depth direction. .. That is, the portion of the P-type substrate forming the well region is uniformly doped with the donor impurity. As a result, the region is changed to the N conductivity type. Then, acceptor impurities are doped only in the portion forming the P-type well region, and the region is changed to the P-conductivity type. In this way, the N-type well region and the P-type well region are formed. Next, the surface of the substrate is oxidized by heat-treating the substrate thus treated. At this time, the acceptor impurity and the donor impurity have different segregation coefficients between the oxide film and the substrate. That is, since the segregation coefficient of the acceptor impurities in the oxide film is larger than the segregation coefficient in the substrate, the acceptor impurities are taken into the oxide film on the surface, so that a distribution in which the acceptor impurities gradually increase in the depth direction is obtained.
On the other hand, conversely, the donor impurity has a smaller segregation coefficient in the oxide film than that in the substrate, so the donor impurity is taken in from the oxide film side to the substrate side, so that the donor impurity gradually decreases in the depth direction. A distribution is obtained. As a result, the distribution of the acceptor impurities and the donor impurities is combined, and the distribution of the effective acceptor impurity density is obtained such that the distribution gradually increases in the depth direction from the interface with the oxide film near the surface of the substrate.

[0015]

According to the first aspect of the present invention, the P-type well region is formed in the vicinity of the surface so as to have an impurity distribution such that the effective acceptor impurity concentration gradually increases in the depth direction. The depths of the drains were substantially equal, and the N-type diffusion region could be made thinner than in the conventional device. Therefore, the short channel effect could be suppressed.
Further, as a result of suppressing the short channel effect, the element can be made finer.

In a second aspect of the present invention, the above-mentioned effective acceptor impurity concentration distribution in the P-type well region is P
When the N-type well region is formed by replacing the step of masking the formation portion of the type well region and the N-type well region alternately with the donor impurity and the acceptor impurity, the P-type well region is formed. Part with donor impurities, and then mask only the N-type well region to form P
Since the acceptor impurities are doped in the formation portion of the mold well region, the number of steps does not increase as compared with the conventional manufacturing method, and only the mask shape needs to be changed.
Easy to manufacture.

[0017]

EXAMPLES The present invention will be described below based on specific examples. FIG. 1 is a sectional view showing a CMOS transistor portion of an integrated circuit. 2 to 5 are schematic views showing manufacturing steps of the transistor. As shown in (1) of FIG. 2, the surface of the P-type single crystal silicon substrate 10 is covered with an oxide film 30 for protecting the surface from contamination, and then phosphorus ions 31 are ion-implanted over the entire surface. Incidentally, the concentration of boron as an acceptor impurity of the P-type single crystal silicon substrate 10 is appropriately about 1 × 10 ¹⁵ / cm ³ , for example. The implantation amount of phosphorus ions is determined so that the effective donor impurity concentration on the substrate surface is a concentration at which the threshold voltage of the design specifications of the Pch transistor is obtained.

Next, as shown in FIG. 2B, a region other than the region where the Nch transistor is formed is masked with a photoresist 32 by photolithography. Then, the boron ions 33 are selectively implanted only in the region where the Nch transistor is formed. The ion species at this time is not limited to boron, and may be BF or BF ₂ ions or the like. The boron ion implantation amount at this time is determined so that the effective acceptor impurity concentration on the substrate surface is a concentration at which the threshold voltage of the design specification of the Nch transistor is obtained.

Next, the photoresist 32 is removed, and the substrate 10 is heat-treated to diffuse the implanted phosphorus and boron. As a result, as shown in FIG. 3C, the P-type well region 11a and the N-type well region 11b are formed, and the oxide film 30 is newly formed by thermal oxidation. In addition, when N ⁺ polycrystal silicon doped with phosphorus at a high concentration is used for the gate electrode described later and the absolute value of the threshold voltage of both transistors is controlled to about 0.5 to 1.2 V, The impurity concentration on the surface of the P-type well region 11a is higher than the impurity concentration on the surface of the N-type well region 11b, and the diffusion depth of the P-type well region 11a is deeper than that of the N-type well region 11b. Therefore, the P-type well region 11a is electrically connected to the substrate 10.

On the other hand, the N-type well region 11b is electrically isolated from the substrate 10. In the P-type well region 11a thus formed, phosphorus element and boron element exist as impurities. However, since the elemental amount of boron is large, it shows a P-conduction type.

When the segregation coefficient is defined by the following equation, deviation coefficient = (impurity equilibrium concentration in silicon) / (impurity equilibrium concentration in oxide film) The deviation coefficient of phosphorus is larger than 1,
The deviation coefficient of boron is less than 1. Therefore, in the diffusion process by heat treatment, phosphorus moves from the oxide film 30 side to the silicon substrate 10 side, and conversely, boron moves from the silicon substrate 10 side to the oxide film 30 side. Therefore, by adding an oxidation treatment to the heat treatment during the formation of the well, so-called pile-up occurs, in which the concentration of phosphorus becomes high on the surface of the substrate 10. Conversely, for boron,
The concentration becomes low on the surface of the substrate 10.

Therefore, in the P-type well region 11a, the effective acceptor impurity concentration (boron concentration-phosphorus concentration) has a distribution that gradually increases in the depth direction. Figure 6
3 is an impurity concentration profile along the line X1-X1 shown in FIG. 3 in the P-type well region 11a obtained by simulation. In FIG. 6, the curve a shows the concentration distribution of phosphorus, the curve b shows the concentration distribution of boron,
A curve c shows an effective concentration distribution of acceptor impurities. 0.2 μm from the oxide film / silicon interface in the depth direction
Well concentration up to the depth of 6 × 10 ¹⁶ / cm ³ to 1.0
It is calculated that the temperature rises to × 10 ¹⁷ / cm ³ .

After the P-type well 11a and the N-type well 11b are thus formed, the isolation oxide film 16 for element isolation and the gate oxide film 17 are formed as shown in (4) of FIG. In the transistor region formed in this way, as shown in FIG.
As shown in (5), the gate electrode 18 made of polycrystalline silicon is formed. Usually, the photoresist remains immediately after the gate electrode 18 is formed by etching, but the photoresist is removed by ashing or washing with an oxidizing agent such as a mixed solution of concentrated sulfuric acid and hydrogen peroxide.

After that, the gate electrode 18 is covered with an insulating film 19 such as an oxide film, a nitride film, a titanium oxide film, or a titanium nitride film by thermal oxidation, thermal nitriding, sputtering, chemical vapor deposition, vapor deposition, or the like. To do. This insulating film 19 is for preventing the phenomenon that phosphorus ions pass through the gate electrode 18 without being scattered, that is, the channeling. A suitable film thickness is 0.04 μm or more, specifically about 0.1 μm. Then, phosphorus ions 34 are ion-implanted on the entire surface of the substrate. At this time, the ion implantation conditions may be set such that the punch-through stop of the Pch transistor can be performed and the lateral expansion is set so that the relaxation of the electric field of the Nch transistor can satisfy the hot carrier breakdown voltage.

Thereafter, as shown in FIG. 5 (7), the substrate 10 is subjected to an appropriate heat treatment to form the N type diffusion regions 21a and 22a in the P type well region 11a and the N type well region 11b. N-type diffusion regions 21b and 22b are formed.
The N-type diffusion regions 21a and 22a can serve as an electric field relaxation layer for the Nch transistor. Further, the N type diffusion regions 21b and 22b serve as punch through stoppers for the Pch transistor. In addition, this N-type diffusion region 21
The diffusion depth of a, 22a, 21b, 22b is 0.2 μ at most.
m is enough.

Next, as shown in FIG. 5 (7), the Pch transistor portion was masked with the resist 35 by the photolithography method. Then, only in the N-type diffusion regions 21a and 22a of the P-type well region 11a, arsenic was ion-implanted using the gate electrode 18 as a mask and thermally diffused to obtain the source 23a and the drain 24a. At this time, phosphorus may be simultaneously implanted as the implanted ion species.
When phosphorus and arsenic are implanted at the same time, the concentration profile changes continuously in the channel direction and the on-resistance of the transistor can be reduced. By implanting phosphorus, the impurity distribution immediately after ion implantation formed in this way is shallower in the depth direction than in the conventional structure in which it is implanted perpendicularly to the normal to the substrate surface, and the lateral direction immediately below the gate is formed. It is distributed to be long. Therefore, if the subsequent heat treatment is appropriately performed, the N-type diffusion regions 21a and 22a and the source 23a and the drain 24a are thin and have the same thickness in the depth direction, and the N-type diffusion regions 21a and 22a are the same in the direction parallel to the surface of the substrate 10. The diffusion regions 21a and 22a can be enlarged.

Next, as shown in FIG. 5 (8), the P-type well region 11a is masked with the resist 36. Only in the N-type diffusion regions 21b and 22b of the N-type well region 11b, using the gate electrode 18 as a mask, boron ions or BF or BF ₂ ions are ion-implanted and thermally diffused to form the source 23b and drain shown in FIG. 24b was obtained. Next, FIG.
As shown in, a protective film 29 such as an oxide film, a nitride film, phosphorus glass (PSG) or phosphorus boron glass (BPSG) is formed by, for example, a chemical vapor deposition method, a sputtering method, a vacuum deposition method, or the like. After that, a connection hole 40 was formed in the source / drain region and the gate electrode of each transistor, and a wiring was taken out from each connection hole 40 by the electrode 28 to manufacture a CMOS transistor.

FIG. 7A is a diagram schematically showing the impurity concentration profile in the depth direction in the region of the drain 24a after the source 23a and the drain 24a are formed in the P-type well region 11a. That is, the N-type diffusion region 2
The effective acceptor impurity concentration in the P-type well region 11a before the formation of 2a is as shown by the curve a:
The characteristic is shown that it gradually increases with respect to the depth from the oxide film / silicon interface (same as curve c in FIG. 6). Then, the donor impurity concentration for forming the N-type diffusion region 22a and the drain 24a is distributed as shown by the curve b. As a result, the donor impurities for forming the N-type diffusion region 22a and the drain 24a are compensated by the effective acceptor impurities distributed as shown by the curve a, and as a result, the effective donor impurity concentration and the acceptor impurity concentration are It becomes as shown by the curve c. What can be seen from the curve c is that the effective donor impurity concentration and the acceptor impurity concentration distribution sharply change at the N-conducting type and P-conducting type junction surfaces, and the depth X _j of the junction surface becomes shallow. Is.

For comparison, in the conventional device in which the acceptor impurity concentration in the P-type well region 11a is made uniform with respect to the depth, the impurity concentration distribution shown in (2) of FIG. _{As j} becomes deeper, a low concentration N-type diffusion region is formed near the joint surface. As described above, in the conventional device, the N-type diffusion region of the electric field relaxation layer needs to be deep in the depth direction, so that the structure is likely to cause punch-through. However, according to the present invention, since the junction position becomes shallower in the depth direction even with the same drain structure, punch-through is less likely to occur as compared with the conventional example, so that the threshold voltage is reduced due to the short channel effect. Hard to do. Therefore, the element can be formed with extremely good reproducibility. Further, the resist coating step formed in this way is required only once. Therefore, the P-type well region and N
It can be formed extremely easily as compared with the conventional process in which ions are separately implanted into the mold well region. In addition, the P-type well region 1
The lateral spread of 1a is at most about 1 μm from the position patterned by the photoresist, and there is no great obstacle to miniaturization.

With the CMOS transistor device of this embodiment, it is possible to realize a structure in which the electric field is alleviated while suppressing an increase in the threshold voltage due to the short channel effect in the Nch transistor more than in the conventional example.
With respect to the Nch transistor, the effective acceptor concentration increases in the depth direction. Therefore, it is possible to make the diffusion depth shallower than that of the conventional structure. Further, since the conventional expansion can be obtained in the lateral direction, the electric field relaxation structure can be secured. Further, after forming the insulating film 19 in the lateral direction, the source 23a and the drain 24a having a high N-type impurity concentration are diffused. Therefore, the electric field relaxation structure in the lateral direction can be secured, and the hot carrier breakdown voltage is improved. Further, the diffusion depth is shallow, and the short channel effect can be suppressed. Further, a shallow junction is formed in the electric field relaxation layer by the angle ion implantation. Moreover, since the electric field relaxation layer can be formed laterally just below the gate electrode 18, it is not necessary to form the electric field relaxation layer so that the diffusion depth is deeper with respect to the source and the drain as in the conventional case, and the short channel effect can be suppressed. Becomes Further, in the transistor device of this embodiment, N
The type diffusion regions 21a, 22a, 21b, 22b are formed so as to overlap the gate electrode 18. Therefore, when a positive voltage is applied to the gate electrode 18 with respect to the potential of the substrate 10, an accumulation layer is formed. In the conventional LDD structure, the electric field relaxation layer serves as a resistance component and lowers the current capability. However, in the transistor device of this embodiment, the storage layer is formed as described above, which is an improvement. Therefore, the transistor of the present invention has a structure suitable for miniaturization, and can also achieve higher speed. That is, if an integrated circuit is formed by the present invention, higher integration can be achieved as compared with the conventional structure.

[Brief description of drawings]

FIG. 1 is a sectional view showing a structure of a CMOS transistor according to an embodiment of the present invention.

FIG. 2 is a schematic diagram showing a manufacturing process of an example transistor.

FIG. 3 is a schematic diagram showing a manufacturing process of an example transistor.

FIG. 4 is a schematic diagram showing a manufacturing process of an example transistor.

FIG. 5 is a schematic diagram showing a manufacturing process of an example transistor.

FIG. 6 is a characteristic diagram showing an impurity concentration distribution in a P-type well region of an example transistor.

FIG. 7 is a characteristic diagram showing an impurity concentration distribution in a depth direction in a source or drain formation portion of an example transistor and a conventional transistor.

FIG. 8 is a cross-sectional view showing the configuration of a conventional CMOS transistor device.

[Explanation of symbols]

 10 ... Semiconductor substrate 11a ... P-type well region 11b ... N-type well region 18 ... Gate electrode 19 ... Insulating film 21a, 22a, 21b, 22b ... N-type diffusion region 21a, 21b ... Source 22a, 22b ... Drain

Claims (2)

[Claims] 1. An impurity concentration higher than that of the P-type well region and the N-type well region and higher than that of the source and the drain at positions where a source and a drain are formed in the P-type well region and the N-type well region. In a complementary MIS transistor device having a low concentration and an N-type diffusion region having a wider diffusion region than the source and the drain, the P-type well region formed by impurity doping is:
In the vicinity of the surface, the impurity distribution is such that the effective acceptor impurity concentration gradually increases in the depth direction, and the N-type diffusion region and the source and drain formed in the N-type diffusion region are Compensating for the distribution,
Complementary type M characterized in that the depth of the N type diffusion region and the depth of the source or the drain are configured to be substantially equal by doping with a donor impurity so as to be N conduction type.
IS transistor device. 2. A P-type well formed on a P-type semiconductor substrate
Source and drain in the region and the N-type well region
At the formation position, the P-type well region and the N-type well region are formed.
The impurity concentration is higher than that of the well region, and the source and
The impurity concentration is lower than that of the drain, and the source and
An N-type diffusion region having a wider diffusion region than the drain is formed.
In manufacturing method of complementary MIS transistor device
The P-type well region of the P-type semiconductor substrate and the N-type
The region forming the well region is doped with donor impurities
And the doped region is made to be N-conductivity type, and the portion forming the N-type well region is masked to make the P
Only the part that forms the mold well region has already been doped.
Acceptor is not enough to overcompensate the donor impurity density.
The pure region is doped to make the doped region P-conducting, and then the semiconductor substrate is heat-treated to
Effective in the depth direction of the P-type well region near the surface
Distribution that gradually increases the typical acceptor impurity concentration
A gate electrode in the P-type well region and the N-type well region.
The N-type diffusion is performed by diffusing donor impurities using the pole as a mask.
A region is formed, and the N-type diffusion region and the N-type window of the P-type well region are formed.
A gate electrode is used as a mask in the N-type diffusion region of the well region.
The donor and acceptor impurities, respectively.
Characterized by diffusion to form a source and a drain
A method of manufacturing a complementary MIS transistor device.