JPH0645533A - Cmos type field effect semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To prevent latchup phenomenon due to a parasitic bipolar transistor, by ion-implanting oxygen atom or nitrogen atom, and forming an insulating layer of a silicon oxide film or a silicon nitride film in a well. CONSTITUTION:A P-type well 2 divided by a field oxide film 3 is formed on an N-type silicon substrate 1, and oxygen ion and nitrogen ion are implanted with high energy, thereby forming an insulating layer 11 of a silicon oxide film in the bottom surface part of a P-type well 2. A P-type source region 6, an N-type layer 7 for substrate contact, and a gate electrode 4 are formed on an N-type silicon substrate 4, thereby forming a P-channel type MOS transistor. An N-type source region 8, an N-type drain region 9, and a gate electrode 4 are formed in a P-type well 2, thereby constituting an N-channel type MOS transistor. Generation of a vertical type NPN parasitic bipolar transistor 18 can be prevented by the effect of insulation of the insulating layer 11 on the bottom surface of the P-well 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS field effect semiconductor device and a method of manufacturing the same, and more particularly to a latch-up countermeasure for a CMOS field effect semiconductor device using a silicon single crystal substrate.

[0002]

2. Description of the Related Art FIG. 2 shows a conventional CMOS transistor. A P-type source region 5, a P-type drain region 6, and a N-type layer 7 for substrate contact are formed on the N-type silicon substrate 1,
Further, the gate electrode 4 is formed on the channel region between the source and drain regions via the gate insulating film 21 to form a P-channel type MOS transistor. On the other hand, N
Type silicon substrate 1 with P divided by field oxide film 3
A well 2 is formed, an N-type source region 8, an N-type drain region 9 and a P-type layer 10 for well contact are formed therein, and a gate insulating film 21 is formed on the channel region between the source and drain regions. The gate electrode 4 is formed to form an N-channel type MOS transistor.

Such a CMOS transistor tends to be miniaturized with the high integration of an LSI using a silicon single crystal substrate. However, as miniaturization progresses, parasitic bipolar transistors 17 and 18 and resistors 16 and 19
The parasitic transistor action due to is increased, and the latch-up phenomenon is likely to occur. The latch-up phenomenon causes the CMOS transistor to malfunction, and in the worst case, the device may be destroyed.

A method widely used in the conventional latch-up prevention technique is a method using an epitaxial substrate (hereinafter referred to as an epi-wafer) as shown in FIG.
In FIG. 3, the parts having the same functions as those in FIG. 2 are denoted by the same reference numerals.

The epi-wafer for preventing latch-up of FIG. 3A is a wafer in which an N-type epi layer 15 having a low impurity concentration is formed by epitaxially growing silicon on the surface of an N ⁺ -type silicon substrate 20. By forming a CMOS transistor on the surface of the epi layer 15 as shown in FIG. 3B, the resistance value of the base resistor 16 existing in the N ⁺ type silicon substrate 20 of the lateral parasitic bipolar transistor 17 is low. Therefore, the bias (forward bias) between the base and the emitter decreases. Therefore, it becomes difficult for the lateral parasitic bipolar transistor 17 to turn on, and it is possible to prevent the occurrence of the latch-up phenomenon due to the lateral parasitic bipolar transistor 17, which is likely to occur when a noise current or a leak current occurs.

[0006]

The technique of the epi-wafer, which is widely used as a measure for latch-up of CMOS transistors, has a problem that the epi-wafer is generally twice as expensive as a normal silicon single crystal substrate. is there. There is also a problem that impurities in the high-concentration substrate are diffused into the epi layer by heat treatment at high temperature for a long time when forming the well.

[0007]

A feature of the present invention is that a semiconductor substrate of a first conductivity type and a second substrate formed on the semiconductor substrate.
A well region of a conductivity type, a field effect transistor of a second conductivity type channel formed in the first conductivity type region of the semiconductor substrate, and a field effect transistor of a first conductivity type channel formed in the well. In a CMOS type field effect semiconductor device, a CMOS type field effect transistor in which an insulating layer such as a silicon oxide film or a silicon nitride film is formed in a portion in the well deeper than the source and drain regions of the field effect transistor of the first conductivity type channel. It is in a field effect semiconductor device. This insulating layer is preferably formed on the bottom of the well.

Another feature of the present invention is that a well region of the second conductivity type is formed on a semiconductor substrate of the first conductivity type, and oxygen ions or nitrogen ions are doped into the well region by an ion implantation method to form the well region. A method for manufacturing a CMOS field effect semiconductor device, in which an insulating layer is formed inside.

[0009]

The present invention will be described below with reference to the drawings. Figure 1
FIG. 3 is a sectional view showing an embodiment of the present invention.

A field oxide film 3 is formed on the N-type silicon substrate 1.
To form an insulating layer on the bottom surface of the P-type well 2 by heat-treating the P-type well 2 with oxygen ions and nitrogen ions at high energy inside the P-type well 2. 11 is formed.

The conditions for forming a good insulating layer 11 require ion implantation at a high dose and subsequent heat treatment at high temperature for a long time.

Therefore, oxygen ions are implanted into a silicon single crystal substrate having a plane orientation (100) at room temperature at a dose of 1.5 × 10 ¹⁸ / c.
As a result of ion implantation with m ² and acceleration energy of 250 keV, and subsequent heat treatment at a temperature of 1250 ° C. for 12 hours, the composition ratio of silicon atom: oxygen atom is 1: 2 (SiO 2
_A good silicon oxide film close to ₂ ) was obtained as the insulating layer 11.

When the ion species is nitrogen ions, a silicon nitride film is formed as the insulating layer 11.

Then, on the N-type silicon substrate 1, a P-type source region 5, a P-type drain region 6 and N for substrate contact are formed.
The mold layer 7 is formed, and the gate electrode 4 is formed on the channel region between the source / drain regions 5 and 6 via the gate insulating film 21 to form a P-channel MOS transistor. On the other hand, an N-type source region 8, an N-type drain region 9 and a P-type layer 10 for well contact are formed in the P-type well 2, and a gate insulating film 21 is formed on the channel region between the source and drain regions 8 and 9. The gate electrode 4 is formed through the above to form an N-channel type MOS transistor.

In this way, the insulating layer 11 is formed on the bottom surface of the P-type well 2.
Are placed and electrically insulated there, the vertical NPN
The parasitic bipolar transistor 18 can be prevented from occurring, and the parasitic PNPN thyristor action due to the coupling with the lateral PNP parasitic bipolar transistor 17 does not occur, so that the inconvenient latch-up phenomenon can be prevented.

[0016]

As described above, according to the present invention, an oxygen atom or a nitrogen atom is ion-implanted into a well region of a field effect semiconductor device, and an insulating layer of a silicon oxide film or a silicon nitride film is formed inside the well by a subsequent heat treatment. Therefore, there is an effect that the latch-up phenomenon due to the parasitic bipolar transistor can be prevented.

Therefore, a CMO to which the technique of the present invention is applied
The field effect semiconductor device having the S structure has improved performance and reliability.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of the present invention.

FIG. 2 is a sectional view showing a conventional technique.

FIG. 3 is a cross-sectional view showing another conventional technique.

[Explanation of symbols]

1 N-type silicon substrate 2 P-type well 3 Field oxide film 4 Gate electrode 5 P-type source region 6 P-type drain region 7 N-type layer for substrate contact 8 N-type source region 9 N-type drain region 10 P for well contact Type layer 15 N type epi layer 16,19 resistance 17,18 parasitic bipolar transistor 20 N ⁺ type silicon substrate 21 gate insulating film

Claims (4)

[Claims] 1. A first conductivity type semiconductor substrate, a second conductivity type well region formed in the semiconductor substrate, and an electric field of a second conductivity type channel formed in the first conductivity type region of the semiconductor substrate. In a CMOS field effect semiconductor device having an effect transistor and a field effect transistor of a first conductivity type channel formed in the well, a source of the field effect transistor of the first conductivity type channel,
A CMOS field effect semiconductor device, wherein an insulating layer is formed at a location deeper than the drain region in the well. 2. The CMOS field effect semiconductor device according to claim 1, wherein the insulating layer is formed on a bottom portion of the well. 3. The CMOS field effect semiconductor device according to claim 1, wherein the insulating layer is a silicon oxide film or a silicon nitride film. 4. A well region of the second conductivity type is formed on a semiconductor substrate of the first conductivity type, and oxygen ions or nitrogen ions are doped into the well region by an ion implantation method to form an insulating layer inside the well. A method of manufacturing a CMOS field effect semiconductor device, which is characterized by forming the same.