JPH02260653A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To form a highly reliable semiconductor integrated circuit by a method wherein a silicon oxide film and a silicon nitride film are continuously grown to form a composite film and an active base region is protected with the composite film from plasma damage. CONSTITUTION:A composite film formed by growing continuously a silicon oxide film 22 and a silicon nitride film 23, which are formed by performing a selective etching or the like, is formed on an active base region of a lateral P-N-P transistor and moreover, a silicon oxide film 9 is selectively formed. Then, a continuously grown polycrystalline silicon film is selectively etched to form gate electrodes 10 and electrodes 24, with which the active base region is covered. After that, an emitter region, a collector region and the like are formed by an impurity implantation to form a bipolar transistor and the like. Thereby, the active base region is protected by the comsite film from damage due to plasma during production, a recombined current is inhibited and a reduction in a current amplification factor is prevented. Moreover, depletion and inversion of the vicinity of the surface of the active base region are prevented and a high-reliability semiconductor integrated circuit, in which there is no leakage current between the emitter and the collector, is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor integrated circuit in which a bipolar transistor and a MOS transistor are formed within the same semiconductor substrate.

Conventional technology In recent years, there has been a desire for higher speed semiconductor integrated circuits and coexistence of analog and digital functions, and bipolar transistors and CMO8 (
A B i -CMO3 collector circuit in which complementary Mo5) transistors are integrated on the same substrate is attracting attention. In particular, in order to integrate high-performance analog circuits with digital circuits on one chip, high-performance PNP transistors coexist with NPN transistors and MOS transistors.
- It is desired to realize a CMO8 integrated circuit device. A conventional Bi-CMO3 integrated circuit device had a structure as shown in FIG. 2a. Hereinafter, with reference to FIG. 2a, the conventional B
An example of the structure of an i-CMO8 integrated circuit device and its manufacturing method will be described.

First, an n-type or p-type silicon epitaxial layer having a resistivity of 1 to 5 Ωcm is formed on a p-type single crystal silicon substrate 1 on which n-type buried regions 2 and 21 and n-type buried regions 3 and 31 are selectively formed. 4 and n-type buried region 2
, 21 are formed with an n-well region 5 connected thereto, above the n-type buried region 3 with an isolation region 6 connected therewith, and above the n-type buried region 31 with an n-well region 7 formed. Form. Furthermore, by selective oxidation, a thick silicon oxide film 8 is grown to isolate the elements.

Furthermore, a thin silicon oxide film 9 to be a gate oxide film is formed, and a polycrystalline silicon film or the like is selectively formed on this film to form a gate electrode 10. Next, n-type impurities are selectively ion-implanted to form an n-channel MOS transistor.
- After forming a source region 11 and an n- drain region 111 and forming a side wall 12 on the gate electrode 10 using a silicon oxide film or the like, n-type impurities are selectively ion-implanted to form an n+ source region 13 and an n-channel MOS transistor. n
+ drain region 113, n-channel M
At the same time as forming the LDD structure of the OS transistor, the base contact region 14 of the lateral pnp transistor is formed. Furthermore, p-type impurity is selectively ion-implanted to form the p+ source region 15 of the p-channel MOS transistor.
and p+ drain region 115, and at the same time the lateral p+
An emitter region 16 and collector region 17 of an np transistor are formed.

FIG. 2 is a plan view of a lateral pnp transistor of the semiconductor integrated circuit device shown in FIG. 2a. 18.1
9.20 are the contact windows for the emitter, base, and collector of the lateral pnp transistor, respectively, and 26
is the active base region of the lateral pnp transistor.

Problems to be Solved by the Invention In the conventional manufacturing method of semiconductor integrated circuits, horizontal pn
The active base region 26 of the p-transistor is prone to plasma damage that causes an increase in recombination current during the manufacturing process, and the current amplification factor decreases due to the excess base current increase. Furthermore, since the surface potential of the active base region 26 of the lateral pnp transistor is not stabilized, depletion and inversion near the surface of the active base region are likely to occur (this increases leakage current between the emitter and collector, reducing the reliability of the device). The present invention solves the above-mentioned conventional problems by protecting the active base region 1 from plasma damage during the manufacturing process and suppressing the increase in recombination current. This prevents the current amplification factor from decreasing.Furthermore, by stabilizing the surface potential of the active base region, it prevents depletion and inversion near the surface of the active base region, thereby preventing leakage current between the emitter and collector. The purpose of the present invention is to provide a method for manufacturing a highly reliable semiconductor integrated circuit.

Means for Solving the Problems In order to solve these problems, the method for manufacturing a semiconductor integrated circuit of the present invention includes a step of successively growing a thin oxide film and a nitride film to form a composite film, and selecting the composite film. a step of leaving the composite film on at least a region that will become a bipolar transistor; and a step of successively growing a gate oxide film and a polycrystalline silicon film and then selectively etching the polycrystalline silicon film to form a MOS. A step of forming an electrode on the active base region of the lateral bipolar transistor at the same time as the gate electrode of the transistor, and implanting impurities using the electrode as a mask to form the source region and drain region of the MOS transistor and the emitter region and collector of the lateral bipolar transistor. and electrically connecting the emitter of the lateral bipolar transistor and the electrode on the active base region.

Effect: With this configuration, the active base region of the lateral pnp transistor is covered with a conductive film used as the gate electrode of the MOS transistor, so it is possible to prevent plasma damage that causes recombination current from entering the active base region during the manufacturing process. Therefore, it is possible to suppress a decrease in current amplification factor due to an increase in excess base current. Also horizontal pnp
The surface potential of the active base region of the transistor can be stabilized, and depletion and inversion near the surface of the active base can be prevented, thereby preventing an increase in leakage current between the emitter and collector, thereby suppressing a decrease in reliability. I can do it.

Embodiment Regarding an embodiment of the present invention, cross-sectional views of FIGS.
This will be explained with reference to the plan view of FIG. f.

First, as shown in FIG.
An n-type or p-type silicon epitaxial layer 4 is formed, an n-well region 5 is formed on the n-type buried region 2.21, and an isolation layer is formed on the n-type buried region 3. A region 6 is formed, and an n-well region 7 is formed on the n-type buried region 31. Furthermore, a thick silicon oxide film 8 is grown by selective oxidation to isolate the elements.

Next, as shown in Figure 1, after forming a thin silicon oxide film 22, a silicon nitride film 23 is continuously formed, and the silicon nitride film 23 is selectively removed so that it remains in the bipolar transistor region. Then, impurity doping is performed to control the threshold voltage of the MOS transistor. Thereafter, the thin silicon oxide film 22 in the MOS transistor 1 area is selectively removed using the silicon nitride film 23 as a mask.

Next, as shown in FIG. 1C, a thin silicon oxide film 9 that will become a gate oxide film is selectively formed using the silicon nitride film 23 as a mask, and a polycrystalline silicon film is continuously grown and selectively etched. By doing so, an electrode 24 covering the gate electrode 10 of the MOS transistor and the active base region of the lateral pnp transistor is formed.

Next, as shown in FIG. 1d, n-type impurities are selectively ion-implanted to form the n-source region 11 and n-drain region 111 of the n-channel MOS transistor, and the side walls of the gate electrode 10 are formed with a silicon oxide film or the like. form 12.

Next, as shown in FIG. 1e, by selectively ion-implanting n-type impurities to form the n+ source region 13 and n+ drain region 113 of the n-channel MOS transistor,
At the same time as forming the LDD structure of the n-channel MOS transistor, the base contact region 14 of the lateral pnp transistor is formed. Furthermore, by selectively ion-implanting p-type impurities, p+
Source region 15, p+ drain region 115 and horizontal pn
Emitter region 16 and collector region 17 of p-transistor
are formed at the same time. At this time, an active base region 26 is formed under the electrode 24.

FIG. 1f shows a lateral pnp semiconductor integrated circuit device of the present invention.
2 is a plan view of a transistor, in which an active base region 26 (not shown) is covered above the surface by an electrode 24, the potential of which is the same as that of the emitter by electrically connecting contact windows 18 and 25; FIG. potential.

According to this embodiment configured as described above, the horizontal pnp
The surface of the active base region 26 of the transistor is covered with a silicon oxide film 22. Since it is covered with a composite film composed of a silicon nitride film 23 and a polycrystalline silicon electrode 24, plasma damage during the manufacturing process can be prevented from entering the active base region 26, and an increase in recombination current can be suppressed, thereby increasing the current amplification factor. It is possible to prevent a decrease in Further, since the electrode 24 has the same potential as the emitter region 16 by being electrically connected to the emitter extraction electrode, depletion and inversion near the surface of the active base region 26 can be prevented. It is possible to prevent leakage current between the two and realize a highly reliable element.

Effects of the Invention As described above, the present invention prevents a decrease in the current amplification factor by covering the active base region of a lateral pnp transistor with a composite film composed of a conductive film and an insulating film having the same potential as the emitter. Since the surface potential of the base region can be stabilized, a highly reliable semiconductor integrated circuit manufacturing method can be realized.

[Brief explanation of drawings]

FIG. 1 is a sectional view and a plan view showing a semiconductor integrated circuit device according to an embodiment of the present invention, and FIGS. 2a and 2b are a sectional view and a plan view showing a semiconductor integrated circuit device having a conventional structure. 1...P-type car crystal silicon substrate, 9...
・Silicon oxide film, 10...Gate electrode, 14
...Base contact area, 16...
Emitter region, 17... Collector region, 26.
... Active base region, 22 ... Silicon oxide film, 23 ... Silicon nitride film, 24 ...
···electrode. Name of agent: Patent attorney Shigetaka Awano and 1 other person 1 Figure 1 Figure 14゛- Hesgontagt ↑ Tribute area I6- Emi 7da resignation precept 17°゛ Koregugu ryoshoku 2J--Ikkatsuka base area/-P next Simple silicon substrate Q, ZZ--siwabonic acid memi 4 grades. 10.-Kate acid, 24-t, ! f...-P! Monocrystalline silicon substrate

Claims (1)

[Claims] a step of successively growing a thin oxide film and a nitride film to form a composite film; a step of selectively removing the composite film to leave the composite film at least on a region that will become a bipolar transistor; and a step of forming a gate oxide film. a step of sequentially growing a polycrystalline silicon film and then selectively etching the polycrystalline silicon film to form an electrode on the active base region of the lateral bipolar transistor at the same time as the gate electrode of the MOS transistor; A step of simultaneously forming the source region and drain region of the MOS transistor and the emitter region and collector region of the lateral bipolar transistor by implanting impurities using a mask, and electrically connecting the electrodes on the emitter of the lateral bipolar transistor and the active base region. A method for manufacturing a semiconductor integrated circuit, which includes a connecting process.