JPH0322566A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0322566A JPH0322566A JP15809389A JP15809389A JPH0322566A JP H0322566 A JPH0322566 A JP H0322566A JP 15809389 A JP15809389 A JP 15809389A JP 15809389 A JP15809389 A JP 15809389A JP H0322566 A JPH0322566 A JP H0322566A
- Authority
- JP
- Japan
- Prior art keywords
- region
- conductivity type
- drain
- insulating film
- drain region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 239000012535 impurity Substances 0.000 claims abstract description 10
- 230000015556 catabolic process Effects 0.000 abstract description 15
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 8
- 239000001301 oxygen Substances 0.000 abstract description 8
- 229910052760 oxygen Inorganic materials 0.000 abstract description 8
- 238000000034 method Methods 0.000 abstract 2
- 150000002500 ions Chemical class 0.000 abstract 1
- -1 oxygen ions Chemical class 0.000 abstract 1
- 230000000452 restraining effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 20
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052681 coesite Inorganic materials 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- 229910004205 SiNX Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Landscapes
- Non-Volatile Memory (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置、特に高耐圧ＭＯＳトランジスタ
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a high voltage MOS transistor.
本発明は、第１導電形の半導体基体に形成した第２導電
形のウェル領域内に第１導電形チャンネルのＭＯＳトラ
ンジスタを形戊してなる半導体装置において、第２導電
形のウェル領域で且つ第１導電形チャンネルのＭＯＳト
ランジスタのドレイン領域下に空乏層の広がりを抑える
層を形戊することによって、ドレイン領域と基体間のパ
ンチスルーを防止し、Ｍ Ｏ Ｓ トランジスタのドレ
イン耐圧を向上するようにしたものである。The present invention provides a semiconductor device in which a MOS transistor of a first conductivity type is formed in a well region of a second conductivity type formed in a semiconductor substrate of a first conductivity type. By forming a layer that suppresses the spread of the depletion layer under the drain region of the MOS transistor of the first conductivity type channel, punch-through between the drain region and the substrate is prevented and the drain breakdown voltage of the MOS transistor is improved. This is what I did.
第１図は従来の高耐圧ＭＯＳトランジスタの一例を示す
。同図に示すようにＥＰＲＯＭ（ｅｒａｓａｂｌｅ ａ
ｎｄｐｒｏｇｒａｍｍａｂｌｅ ｒｅａｄ ｏｎｌｙ
ｍｅｍｏｒｙ） （２）とｐチャンネル高耐圧ＭＯＳト
ランジスタ（１）を同一の半導体基板に作る場合には、
ｐ形半導体基板（３）にｎ形ウェル領域（４）を形成し
、このｎ形ウェル領域（４）にｐヂャンネル高耐圧ＭＯ
Ｓトランジスタ（１）が形戊される。FIG. 1 shows an example of a conventional high voltage MOS transistor. As shown in the figure, EPROM (erasable a
ndprogrammable read only
memory) (2) and p-channel high voltage MOS transistor (1) on the same semiconductor substrate,
An n-type well region (4) is formed in a p-type semiconductor substrate (3), and a p-channel high breakdown voltage MO is formed in this n-type well region (4).
An S transistor (1) is formed.
即ち、ｐ形半導体基板（３）の１の領域には、ｎ形のソ
ース領域（５）及びドレイン領域（６）を形成し、ゲー
ト絶縁膜（７）を介してフローテインク・ゲート（８〕
及び制御ゲート （ワード線）（９）を形成し、ドレイ
ン領域（６）にＡｌビット線（１０）を接続してなるＢ
ＦＲＯＭ（２）のセル・アレイが形成される。基板（３
）の他の領域にはｎ形ウェル領域（４）を形成し、この
ウェル領域（４）にｐ形のソース領域（１１）、低濃度
ｐ形領域（１２Ａ）及び高濃度ｐ形領域（１２Ｂ）から
なるｐ形のドレイン領域（１２）を形成し、ゲート絶縁
膜（１３）を介してゲート電極（１４）を形戒すると共
に、Ａｌのソース電極（１５）及びドレイン電極（１６
）を形成してｐチャンネル高耐圧ＭＯＳトランジスタ（
１）が形成される。このＭＯＳ｝ランジスク（１）では
ドレイン領域（１２）に低濃度領域（１２Ａ） を設
けて空乏層を十分に延ばすことによって高耐圧を得てい
る。（１７）は選択酸化（ＬＯＧＯＳ） によるフィ
ールド絶縁膜（ＳｉＯ２）、（１８〉は層間絶縁膜であ
る。That is, in a region 1 of a p-type semiconductor substrate (3), an n-type source region (5) and a drain region (6) are formed, and a floating gate (8) is formed through a gate insulating film (7).
A control gate (word line) (9) is formed, and an Al bit line (10) is connected to the drain region (6).
A FROM(2) cell array is formed. Substrate (3
), an n-type well region (4) is formed in the well region (4), and a p-type source region (11), a low-concentration p-type region (12A), and a high-concentration p-type region (12B) are formed in this well region (4). ), a p-type drain region (12) is formed, and a gate electrode (14) is formed through a gate insulating film (13), and a source electrode (15) and a drain electrode (16) of Al are formed.
) to form a p-channel high voltage MOS transistor (
1) is formed. In this MOS transistor (1), a low concentration region (12A) is provided in the drain region (12) and the depletion layer is sufficiently extended to obtain a high breakdown voltage. (17) is a field insulating film (SiO2) formed by selective oxidation (LOGOS), and (18>) is an interlayer insulating film.
このようなＥＦＲＯＭ （２）とｐチャンネル高耐圧Ｍ
○Ｓトランジスタ（１）を有する半導体装置は、例えば
蛍光表示管の駆動用マイクロコンピュータ等に用いられ
る。Such EFROM (2) and p-channel high breakdown voltage M
A semiconductor device having the S transistor (1) is used, for example, in a microcomputer for driving a fluorescent display tube.
しかしながら、上述の高制圧ＭＯＳ｝ランジスク（１）
では、ドレイン領域（１２）から縦（深さ）方向に空乏
層が延びるため、ｐ形基板（３〕とドレイン領域（１２
）との間でパンチスルーを起こし、高いドレイン耐圧が
得られない。However, the above-mentioned high pressure MOS
In this case, since the depletion layer extends in the vertical (depth) direction from the drain region (12), there is a gap between the p-type substrate (3) and the drain region (12).
), and high drain breakdown voltage cannot be obtained.
本発明は、上述の点に鑑み、ウェル領域内に高耐圧ＭＯ
Ｓ｝ランシスタを形成した半導体装置において、ドレイ
ン領域と基体間のパンチスルーを防止し、ドレイン耐圧
の向上を図った半導体装置を提供するものである。In view of the above points, the present invention provides a high breakdown voltage MO in the well region.
The present invention provides a semiconductor device in which punch-through between a drain region and a substrate is prevented and drain breakdown voltage is improved in a semiconductor device in which a transistor is formed.
本発明は、第１導電形の半導体基体（２１）に形成した
第２導電形のウェル領域（２９）内に、低濃度第１導電
形不純物領域（３８八） と高濃度第１導電形不純物
領域（３８Ｂ） からなるドレイン領域（３８）を有
する第１導電形チャンネルのＭＯＳトランジスタ（４３
）が形成されてなる半導体装置において、第２導電形の
ウェル領域（２９）で、かつ第１導電形チャンネルのＭ
ＯＳトランジスタのドレイン領域（３８）下に空乏層の
広がりを抑える層（３０）を形成して構成する。The present invention provides a low concentration first conductivity type impurity region (388) and a high concentration first conductivity type impurity region in a second conductivity type well region (29) formed in a first conductivity type semiconductor substrate (21). A first conductivity type channel MOS transistor (43) having a drain region (38) consisting of a region (38B).
) is formed in the well region (29) of the second conductivity type and the M of the first conductivity type channel.
A layer (30) for suppressing the spread of a depletion layer is formed under the drain region (38) of the OS transistor.
空乏層の広がりを抑える層（３０）としては高酸素濃度
領域（ＳｉＯｘ層〉、高窒素濃度領域（ＳｉＮｘ層）、
又は高濃度の第２導電形不純物層等にて形成し得る。The layer (30) that suppresses the spread of the depletion layer includes a high oxygen concentration region (SiOx layer), a high nitrogen concentration region (SiNx layer),
Alternatively, it may be formed using a highly concentrated impurity layer of the second conductivity type.
第１導電形チャンネルのＭＯＳトランジスタが形成され
た第２導電形ウェル領域（２９）において、そのＭＯＳ
トランジスタ（４３）のドレイン領域（３８〉下に空乏
層の広がりを抑える層（３０）を形成することにより、
動作時、ドレイン領域（３Ｂ）から縦方向に空乏層が広
がるも上記層（３０）によりそれ以上の広がりが抑制さ
れる。従って、ドレイン領域（３８〉と基体（２１）間
のパンチスルーが防止され、ＭＯＳトランジスタ〈４３
）のドレイン耐圧が改善される。In the second conductivity type well region (29) in which the MOS transistor of the first conductivity type channel is formed, the MOS transistor is
By forming a layer (30) below the drain region (38) of the transistor (43) to suppress the spread of the depletion layer,
During operation, the depletion layer spreads in the vertical direction from the drain region (3B), but further spread is suppressed by the layer (30). Therefore, punch-through between the drain region (38) and the substrate (21) is prevented, and the MOS transistor <43>
) drain breakdown voltage is improved.
以下、第１図を用いて本発明による高耐圧Ｍ○Ｓトラン
ジスタの実施例を、その製法と共に説明する。なお、本
例では前述の第２図と同様に、同一の半導体基体上にＥ
ＦＲＯＭを共に形戊するｐチャンネル高耐圧ＭＯＳトラ
ンジスタに適用した場合であるが、第１図においてはｐ
チャンネル高耐圧ＭＯＳトランジスタのみを示す。Hereinafter, an embodiment of a high voltage M○S transistor according to the present invention will be described with reference to FIG. 1, along with a manufacturing method thereof. Note that in this example, similarly to the above-mentioned FIG.
This is a case where it is applied to a p-channel high voltage MOS transistor that forms a FROM.
Only channel high voltage MOS transistors are shown.
先ず第１図Ａに示すようにｐ形のシリコン半導体基体（
２１）を用意し、この基体（２ｌ）の主面にＳｉ０２等
の絶縁膜（２２）を形成した後、ウェル領域を形成する
部分に開口（２３）を有するレジストマスク（２４）を
形成する。そして、このレジストマスク（２４）を介し
て基体（２１）内にウェル領域を形成するためのｎ形不
純物（２５）をイオン注入する。First, as shown in FIG. 1A, a p-type silicon semiconductor substrate (
21) is prepared, and after forming an insulating film (22) of Si02 or the like on the main surface of this substrate (2l), a resist mask (24) having an opening (23) in a portion where a well region is to be formed is formed. Then, an n-type impurity (25) for forming a well region is ion-implanted into the base (21) through this resist mask (24).
次に、第１図Ｂに示すように、レジストマスク（２４）
を除去した後、再び絶縁膜（２２〉上に爾後形成される
高耐圧のドレイン領域に対応する部分に開口（２６）を
有するレジストマスク（２７）を形戊する。Next, as shown in FIG. 1B, a resist mask (24) is applied.
After removing, a resist mask (27) is formed again on the insulating film (22) having an opening (26) in a portion corresponding to a high breakdown voltage drain region to be formed later.
そして、このレジストマスク（２７）を介して基体（２
ｌ）内に酸素（２Ｂ）を高濃度にイオン注入する。Then, the substrate (2) is passed through this resist mask (27).
1) Oxygen (2B) is ion-implanted at a high concentration.
？に、第１図Ｃに示すように、熱処理してｎ形ウェル領
域（２９）を形成すると共に、ウェル領域（２９）のド
レイン領域下に対応する底部に高酸素濃度領域（即ち絶
縁性の８１０×層） （３０）を形成する。? Then, as shown in FIG. x layer) (30) is formed.
次に、第１図Ｄに示すように、通常の方法で選択酸（Ｌ
ＯＧＯＳ） によるフィールド絶縁膜（Ｓｉｎ■）
（３１）、ＳｉＯ■等によるゲート絶縁膜（３２）及び
例えば多結晶シリコンよりなるゲート電極（３３）を形
成した後、フィールド絶縁膜（３１）及びゲート電極（
３３〉をマスクにソース及びドレイ・ンとなる領域に低
濃度のｐ形不純物（３４）をイオン注入する。Next, as shown in FIG. 1D, a selective acid (L
Field insulation film (Sin■) by OGOS)
(31), a gate insulating film (32) made of SiO2, etc., and a gate electrode (33) made of polycrystalline silicon, for example, after forming a field insulating film (31) and a gate electrode (32) made of, for example, polycrystalline silicon.
Using 33> as a mask, low concentration p-type impurities (34) are ion-implanted into the regions that will become the source and drain.
次に、第１図已に示すようにドレイン側にさらにゲート
電極（３３）及びフィールド絶縁膜（３１）に接する部
分に選択的にレジストマスク（３５）を形戊して高濃度
のｐ形不純物（３６〉をイオン注入する。次いで、熱処
理して、高濃度ｐ形ソース領域（３７）と、高濃度ｐ形
領域（３８Ｂ） 及び低濃度ｐ形領域（３８Ａ）からな
る高耐圧ドレイン領域（３８）を形戊する。Next, as shown in FIG. 1, a resist mask (35) is selectively formed on the drain side in a portion in contact with the gate electrode (33) and the field insulating film (31), and a high concentration of p-type impurity is applied. (36) is ion-implanted. Next, heat treatment is performed to form a high-concentration p-type source region (37), a high-voltage drain region (38) consisting of a high-concentration p-type region (38B), and a low-concentration p-type region (38A). ).
しかる後、第１図Ｆに示すように、通常の方法で層間絶
縁膜（３９）、コンタクトホール（４０）及び八ｌのソ
ース電極（４ｌ）及びドレイン電極（４２）を形戊して
目的のｐチャンネル高耐圧ＭＯＳ｝ランシスタ（４３）
を得る。Thereafter, as shown in FIG. p-channel high voltage MOS} Runsistor (43)
get.
上述の構戒によれば、ｎ形ウェル領域（２９）に形成さ
れたｐチャンネルＭＯＳトランジスタ（４３）のドレイ
ン領域（３８）とｐ形基体（２１）間に、高酸素濃度領
域（３０）が設けられることにより、動作時に、ドレイ
ン領域（３８）から縦方向に広がる空乏層が高酸素濃度
領域ク３０）のところで抑えられ、基体（２ｌ）に到達
しない。従って、ドレイン領域（３８）及び基体（２ｌ
）間のパンチスルーを防止することができ、高耐圧ＭＯ
Ｓトランジスタ（４３）のドレイン耐圧を向上すること
ができる。According to the above structure, a high oxygen concentration region (30) is formed between the drain region (38) of the p-channel MOS transistor (43) formed in the n-type well region (29) and the p-type substrate (21). By providing this, during operation, the depletion layer extending vertically from the drain region (38) is suppressed at the high oxygen concentration region (30) and does not reach the substrate (2l). Therefore, the drain region (38) and the substrate (2l
) can prevent punch-through between
The drain breakdown voltage of the S transistor (43) can be improved.
尚、上例においては、高酸素濃度領域（３０）を設けた
が、これに代えて窒素を高濃度にイオン注入してなる高
窒素濃度領域（即ち絶縁性のＳｉＮｘ層）又はｎ形の高
不純物濃度領域を設けることも可能である。In the above example, the high oxygen concentration region (30) was provided, but instead of this, a high nitrogen concentration region (i.e., an insulating SiNx layer) formed by ion-implanting nitrogen at a high concentration or an n-type high It is also possible to provide an impurity concentration region.
又、上例ではｐチャンネル高耐圧ＭＯＳ＋−ランジスタ
に適用したが、ｐ形ウェル領域にｎチャンネル高耐圧Ｍ
ＯＳトランジスタを形成する場合にも適用できること勿
論である。Furthermore, although the above example is applied to a p-channel high-voltage MOS+- transistor, an n-channel high-voltage MOS transistor is
Of course, the present invention can also be applied to forming an OS transistor.
本発明の高耐圧Ｍ．ＯＳトランジスタによれば、第２導
電形ウェル領域に形成された第１導電形チセンネルのＭ
ＯＳトランジスタのドレイン領域を第ｌ導電形半導体基
体との間に空乏層の広がりを抑える層を設けることによ
り、ドレイン領域と基体間のパンチスルーを防止するこ
とができ、Ｍ○Ｓトランジスタのドレイン耐圧を向上す
ることができる。従って、例えば蛍光表示管の駆動用マ
イクロコンピュータ等を形成する半導体装置、即ちεＦ
ＲＯＭ と高耐圧ＭＯＳトランジスタを同一半導体基体
上に作る半導体装置に適用して好適ならしめるものであ
る。High voltage M. of the present invention. According to the OS transistor, M of the first conductivity type channel formed in the second conductivity type well region
By providing a layer between the drain region of the OS transistor and the I-th conductivity type semiconductor substrate to suppress the spread of the depletion layer, punch-through between the drain region and the substrate can be prevented, and the drain breakdown voltage of the M○S transistor can be reduced. can be improved. Therefore, for example, a semiconductor device forming a microcomputer for driving a fluorescent display tube, that is, εF
The present invention is suitable for application to a semiconductor device in which a ROM and a high voltage MOS transistor are formed on the same semiconductor substrate.
第１図Ａ−Ｆは本発明による半導体装置の一例を示す工
程順の断面図、第２図は従来のεＦＲＯＭ と高耐圧Ｍ
ＯＳトランジスタを有する半導体装置の例を示す断面図
である。
（２ｌ）はｐ形シリコン基体、（２９）はｎ形ウェル領
域、（３０）は高酸素濃度領域、（３３）はゲート電極
、（３７）ソース領域、（３８）はドレイン領域である
。FIGS. 1A to 1F are cross-sectional views showing an example of a semiconductor device according to the present invention in the order of steps, and FIG. 2 shows a conventional εFROM and a high breakdown voltage M
1 is a cross-sectional view showing an example of a semiconductor device having an OS transistor. (2l) is a p-type silicon substrate, (29) is an n-type well region, (30) is a high oxygen concentration region, (33) is a gate electrode, (37) is a source region, and (38) is a drain region.
Claims (1)
領域内に、低濃度第１導電形不純物領域と高濃度第１導
電形不純物領域からなるドレイン領域を有する第１導電
形チャンネルのＭＯＳトランジスタが形成されてなる半
導体装置において、上記第２導電形のウェル領域でかつ
上記第１導電形チャンネルのＭＯＳトランジスタの上記
ドレイン領域下に空乏層の広がりを抑える層が形成され
て成る半導体装置。A first conductivity type channel MOS having a drain region consisting of a low concentration first conductivity type impurity region and a high concentration first conductivity type impurity region in a second conductivity type well region formed in a first conductivity type semiconductor substrate. A semiconductor device having a transistor formed therein, wherein a layer for suppressing the spread of a depletion layer is formed in the well region of the second conductivity type and below the drain region of the MOS transistor of the first conductivity type channel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15809389A JPH0322566A (en) | 1989-06-20 | 1989-06-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15809389A JPH0322566A (en) | 1989-06-20 | 1989-06-20 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0322566A true JPH0322566A (en) | 1991-01-30 |
Family
ID=15664150
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15809389A Pending JPH0322566A (en) | 1989-06-20 | 1989-06-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0322566A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100422325B1 (en) * | 2002-06-12 | 2004-03-11 | 동부전자 주식회사 | Fabricating method of semiconductor device |
-
1989
- 1989-06-20 JP JP15809389A patent/JPH0322566A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100422325B1 (en) * | 2002-06-12 | 2004-03-11 | 동부전자 주식회사 | Fabricating method of semiconductor device |
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