JPH01307266A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To overlap a gate electrode and source-drain sufficiently, and to obtain a MIS type field-effect transistor, breakdown strength of which is increased and current driving capacitance of which is augmented, by forming the low-concentration source-drain through oblique ion implantation. CONSTITUTION:Phosphorus is implanted at an angle of 45 deg.-60 deg. in the vertical direction to an silicon substrate 1 while using a gate electrode 5 as a mask. Rotational implantation in the two-four directions is conducted in consideration of the direction of the gate electrode 5 of a transistor shaped onto the substrate in ion implantation at that time, thus preventing the generation of asymmetry to source-drain. An silicon oxide film is applied, and sidewall spacers 7 are formed onto the sidewalls of the gate electrode 5 by using reactive ion etching. N<+> layers 8 are shaped through a rotational implantation method in which arsenic is implanted at an angle of 0 deg. or approximately 7 deg. in the vertical direction to the silicon substrate. Accordingly, a MIS type field-effect transistor having high breakdown strength and high current driving capacitance can be acquired.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for forming a MIS field effect transistor that can achieve high reliability and high current drive capability. The present invention relates to a manufacturing method suitable for.

[Conventional technology]

Conventionally, structures and manufacturing methods that can achieve high reliability and high current drive capability in MIS type field effect transistors are described, for example, by IEE and Electron Device Letters.

E.D.L.8. (1987) pp. 151-153 (IE E E, Electron D
eviceLatters, EDL-8 (1987)
, pp. 151-153).
) structure, it is necessary that the amount of overlap between the gate and the lightly doped drain is sufficient, and that the highly doped drain reaches just below the gate electrode. IT-LDD is one manufacturing method for forming this.

In addition, one of the methods for forming the LDD structure is published in IEICE Technical Report, Vol.
l, 87. No. 343 (1988), pages 25 to 30, to prevent asymmetry during ion implantation, rotational implantation is performed from four directions at an angle of 7° to the wafer and perpendicular direction. I can give you a method. This is shown in FIGS. 2(a) and 2(b).

Furthermore, in order to simply ensure the amount of overlap between the low concentration source/drain layer and the gate, it is possible to perform sufficient heat treatment during the formation of the low concentration layer and form a large diffusion layer by thermal diffusion, or to form a large diffusion layer during ion implantation. One method is to use high energy to form a large diffusion layer. This is shown in FIG. 2(c).

[Problem to be solved by the invention]

In the above-mentioned conventional technology, the method for forming an IT-LDD lacks stability and ease of manufacturing process, such as stopping etching midway through processing the gate electrode.

In addition, in the angled rotational ion implantation method, it is possible to simply
Although the asymmetry is only improved, the structure itself remains the same as the conventional LDD structure, and higher breakdown voltage and higher current drive capability cannot be achieved.

Furthermore, as shown in FIG. 2(c), when securing the amount of overlap between the gate, source, and drain only by thermal diffusion, the diffusion layer generally extends not only in the lateral direction but also in the depth direction. This results in a large increase in the short channel effect.

SUMMARY OF THE INVENTION An object of the present invention is to provide a manufacturing method for easily forming an LDD structure in which the gate, source, and drain sufficiently overlap and the high concentration diffusion end reaches directly below the gate electrode.

[Means to solve the problem]

The above purpose is to increase the angle of incidence during ion implantation for forming low-concentration sources and drains with respect to the direction perpendicular to the wafer, that is, to perform oblique ion implantation in a method for forming MIS type field effect transistors, and to form sidewall spacers. This is achieved by later forming a highly doped drain so as to reach just below the gate electrode.

[Effect]

Low concentration source of MIS type field effect transistor.

By forming the drain by oblique ion implantation, it is possible to form a diffusion layer that has a larger elongation in the lateral direction than in the depth direction, suppressing the increase in the short channel effect, and
The amount of overlap between the gate electrode, source, and drain can be increased. Furthermore, since the highly doped source and drain reach directly below the gate, a significant improvement in current drive capability can be expected.

As described above, it is possible to obtain a MIS type field effect transistor which has a higher breakdown voltage and higher current drive capability than the conventional LDD.

〔Example〕

Embodiment 1 A first embodiment of the present invention will be described below with reference to FIG.

First, as shown in Figure 1(a), p-type silicon (specific resistance 5~
(approximately 100) on the substrate 1, selectively 500 ~
A 700 nm silicon oxide film is formed, and boron is implanted over the entire surface at an energy of 150 to 200 KeV, 0.5 to
Ion implantation was performed at a dose of I x 1013 cm-'',
A high concentration buried layer 2 is formed in the substrate. Thereafter, a gate oxide film 4 is formed to a thickness of 10 to 20 nm, and boron 3 is again implanted at a low energy of 0.5 to 1.5 x 10" cm to set a threshold voltage. This can be omitted depending on the implantation amount of the buried layer 2. Also, in the figure.

Element isolation regions are omitted. Next, a polycrystalline silicon film is coated to a thickness of about 300 to 350 nm, and a gate electrode 5 is patterned by etching the first layer as shown in the figure.

Next, as shown in Figure 1(b), using the gate electrode as a mask, 5X
About IO"~2 x 101cm-" of phosphorus.

The implantation is performed at an angle of 456 to 60' with respect to the direction perpendicular to the silicon substrate 1. At this time, ion implantation takes into consideration the direction of the gate electrode of the transistor formed on the substrate.
Rotational implantation is performed in 2 to 4 directions to prevent source/drain asymmetry. In this embodiment, the size of the n-layer 6 is ultimately 0.1 to 0.15 μm in the depth direction and 0.15 μm in the lateral direction (that is, the amount of overlap with the gate).
It became ~0.2 μm.

Furthermore, as shown in FIG. 1(c), a silicon oxide film of 100%
A film of ~150 nm is formed, and sidewall spacers 7 are formed on the side walls of the gate electrode 5 using reactive ion etching. At this time, the spacer length is 0.1 to 0.15 μm
It became. Thereafter, an n+ layer 8 is formed by rotational implantation of about 1 to 5 x 1015 am-'' of arsenic into the silicon substrate at an angle of about 0'' or 7'' with respect to the vertical direction. The amount of lateral diffusion of the n+ layer is 0.
．． It was 1 to 0.15 μm. The width of the sidewall spacer 7 needs to be set to be equal to or less than the amount of lateral diffusion of the n+ layer.

As a result of the above, it was possible to obtain a MIS type field effect transistor with high breakdown voltage and high current instantaneous ability, which secured the amount of gate overlap, without increasing the number of process steps. 2 is not formed, the short channel effect is also suppressed, and it is very effective at a gate length of 0.5 μm.

Embodiment 2 Next, a second embodiment of the present invention will be described with reference to FIG.

First, as shown in FIG. 3(a), the formation of the gate current 5 is performed in the same steps as in FIG. 1(a) in the first embodiment, and then phosphorus is I Q 1
Ion implantation is performed obliquely from the drain to the source by about 3 cm to form an n-type low concentration diffusion layer 6. As a result, n- and fl having a large amount of overlap with the gate are formed on the drain side. The source side is in the shadow of the gate electrode 5 and has no n- layer.

Next, as shown in FIG. 3(b), a side wall spacer of about 0.1 to 0.15 μm is formed, and from now on, arsenic is applied perpendicularly to the silicon substrate by 1 to 5×10 15 CII! -Enter about 2. The subsequent steps are the same as in the first embodiment.

According to this embodiment, n having a large amount of overlap
- Since the layer is located on the drain side, high reliability can be achieved in the same way as in the first embodiment, while higher current drive capability can be achieved. In the first and second embodiments described above, an example of an n-channel transistor was shown, but by reversing the conductivity types, the present invention can easily be applied to an n-channel transistor as well.

Embodiment 3 Finally, an embodiment in which the present invention is applied to a process for forming complementary MOS transistors will be described with reference to FIG.

First, as shown in Fig. 4(a), a p-type well was formed by selectively implanting boron and phosphorus ions into a p-type silicon substrate (specific resistance 5-10ΩcIl) and heat-treating at 1050-1150°C for 20-30 hours. 51 and an n-type well 52 are selectively formed. At this time, the concentration of the well is 1~3X1016c■
-3, and the depth of the diffusion edge of the well was 4 to 5 μm. Subsequently, as shown in the figure, a thick silicon oxide film for element isolation is formed to a thickness of 500 to 700 nm.

Next, as shown in FIG. 4(b), 1 boron is added to the p-type well 50.
A buried p-wall high concentration layer 55 is formed by implanting 5 to 10×101012 cr” at 50 to 200 KeV, and 5 to 10 cr of phosphorus is implanted at 200 to 300 KeV to form a buried p-wall high concentration layer 55.
X 1012cm-” implantation, increase n-type high concentration [
56 was formed. These high concentration buried layers 55,'
56 has a final peak concentration of 2~5X10"7am-3
Therefore, it can serve as both a punch-through stopper for a transistor and a channel stopper layer for isolation.

Subsequently, a gate oxide film 49 is formed to a thickness of 10 to 15 nm, and a gate electrode 57 is formed thereon using polycrystalline silicon.

At this time, the threshold voltage of the n-channel and p-channel MOS transistors is 1 to 1.7X of boron before the gate electrode is formed.
Set by ion implantation of 1012c-2. However, depending on the profile of the high concentration buried layer, ion implantation for setting the threshold voltage can be omitted.

Next, as shown in FIG. 4(c), first, the p-channel side is covered with a resist 58, and the phosphorus is 1 to 5×1()13c11-
2 is implanted diagonally to form an n- layer 59 with a large amount of overlap with the gate. Next, as shown in FIG. 4(d), the n-channel side is covered with a resist 58, and boron is obliquely implanted in a thickness of 1 to 5 x 1013 cm to form a p-layer 60 similar to the n-layer 59 described above. do.

Next, as shown in FIGS. 4(e) to 4(g), sidewall spacers 61 of 0.1 to 0.25 μm are formed of a silicon oxide film. Next, arsenic was added to the n-channel at 1 to 5 × 1
0"am-", p channel number is boron 1~2X
Selectively drive about 101sc+*-” and n to each
"m 62 * p" M 63 is formed.

Finally, as shown in FIG.
After forming and drilling contact holes.

Complete by forming aluminum electrodes.

What is important in the above manufacturing process is that the n+ layer 62 and the p
Both diffusion ends of the + layer 63 reach directly below the gate electrode. In this case, sidewall spacers may be made separately for n-channel and p-channel according to the elongation of the diffusion layer.

In this example, the same spacer length was provided. In this case, n
+ layer 62 and p+ layer 63 formation, and n +.

By adjusting the heat treatment after forming the p+ calendar shadow (particularly the former), the elongation of the n''*P+ layer is made almost the same.As a result, the amount of gate overlap can be sufficiently reduced using a manufacturing method that is almost the same as the conventional process. In this example, we were able to form complementary MOS transistors with high breakdown voltage and high current drive capability.
Although a transistor is used, one of them may be formed using a conventional structure and process.

Further, for the p4'' layer of the source and drain of the p-channel, a second sidewall and the like are formed once again.

If the total sidewall spacer length of the p-channel is increased, it can be applied to the complementary MOS process as described above. However, in this case, the number of steps increases to some extent.

〔Effect of the invention〕

According to the present invention, a high breakdown voltage can be achieved without increasing the number of steps by slightly improving the conventional LDD structure formation process.

It is possible to obtain a MIS type field effect transistor with high current drive capability and a UL S I with a gate length of 0.5 μm or less.
(Ultra Large 5cale Integ
It is very effective as a basic device for

[Brief explanation of the drawing]

Fig. 1 is a manufacturing method process diagram showing a typical embodiment of the present invention, Fig. 2 is a process schematic diagram showing a conventional manufacturing method, and Fig. 3 is a process diagram showing a conventional manufacturing method.
4 and 4 are diagrams showing other embodiments of the present invention. 1.50... Semiconductor substrate, 2, 55.56... High concentration buried layer, 3... Impurity layer for threshold voltage setting, 4.
49... Gate insulating film, 5, 57... Gate electrode,
7.10,61...Side wall spacer, 6.9
, 11, 59, 60...Low concentration diffusion layer, 8.62.6
3... High concentration diffusion layer, 51, 52... Well layer. ￥ / En 2nd Zukan 5th 4th - En

Claims (1)

[Claims] 1. A method for forming a MIS field effect transistor on a semiconductor substrate, which includes the steps of forming a gate electrode, and forming a source and drain with low impurity concentration by oblique ion implantation using the gate electrode as a mask. 1. A method of manufacturing a semiconductor device, comprising the steps of forming a source and a drain with high impurity concentration from a location away from an end of the gate electrode to directly below the gate electrode. 2. A method for manufacturing a semiconductor device according to claim 1, characterized in that the low impurity concentration layer is formed only on the drain side by oblique ion implantation. 3. In the method for manufacturing a semiconductor device according to claim 1, the low impurity concentration source and drain of at least one conductivity type channel transistor are used in forming a complementary MIS field effect transistor, and the complementary 1. A method for manufacturing a semiconductor device, comprising forming a high-concentration source and a drain of a type transistor so that the depths of the diffusion layers are the same. 4. A method for manufacturing a semiconductor device according to claim 3, including a step of forming a source and drain with high impurity concentration for one conductivity type channel of a complementary MIS field effect transistor, and a step of forming a high impurity concentration source and drain for the other conductivity type channel. 1. A method of manufacturing a semiconductor device, comprising a heat treatment step between a step of forming a source and a drain with high impurity concentration.