JPH03262130A - Manufacture of semiconductor element - Google Patents

Abstract

PURPOSE:To enable the title semiconductor element having excellent electric field relieving effect and punch-through preventive effect to be manufactured by a method wherein the first conductivity type impurity ions are implanted making a deep angle with the perpendicular direction to substrate surface and then the second conductivity type impurity ions are implanted making a shallow angle with the same. CONSTITUTION:A field oxide film 2 is formed on inactive regions of a P type silicon semiconductor substrate 1 and then a gate oxide 3 and a gate electrode 4 are formed on the surface of an active region. Next, boron is ion-implanted in the direction making an oblique angle exceeding 20 deg. but not exceeding 90 deg. with the perpendicular direction to a wafer surface using the gate electrode 4 as a mask so as to form a P<+>type region 5 for preventing punch-through. Successively, phosphorus ions are implanted in the direction making an angle exceeding 0 deg. but not exceeding 10 deg. with the perpendicular direction to the wafer surface using the gate electrode 4 as a mask so as to form an N<->type region 6 in LDD structure. Furthermore, sidewall spacers 7 are formed at the edge parts on both sides of the gate electrode 4 while ions are implanted using the gate electrode 4 and the sidewall spacers 7 as masks to form N<+>type source.drain diffused layers 8.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device.
The present invention relates to a method of manufacturing a type field effect transistor.

(Prior art) Conventionally, as MO3 field effect transistors are scaled down, the electric field inside the device increases, and hot carriers with high energy are generated and trapped in the gate oxide film or at the interface. Increase level. As a result, the so-called hot carrier effect that causes deterioration of device characteristics, such as fluctuations in dark value voltage, becomes a problem. Furthermore, bunch-through development, in which leakage current occurs between the source and drain, becomes noticeable when the MO3 field effect transistor is in the off state.

Therefore, in order to solve such a problem, for example, t L
f, International Electron Device Meeting (International Electron Device Meeting)
A new transistor structure has been proposed in the document published by N.DevicesMeeting), 1985 Technical Digest, pages 230-233.

Next, an outline of the proposed MO3 field effect transistor will be explained with reference to FIG. First, a gate oxide film 102 is formed on a P-type silicon substrate 101, and a gate electrode 103 is patterned on this gate oxide film 102. Using this gate electrode 103 as a mask, a P-type pocket layer 104 for preventing punch-through is formed by boron ion implantation in a direction tilted from the direction perpendicular to the wafer surface. Similarly, LDD is created by ion implantation of phosphorus from the vertical direction.
A shallow N-type layer 105 for the (upper tightly doped drrain) structure is formed. Afterwards, chemical vapor deposition (CVD) and reactive ion etching (RIE)
A sidewall spacer 106 is provided on the edge portion of the gate electrode 103 and on the gate oxide film 102 using the method.

Next, using the sidewall spacer 106 and the gate electrode 103 as a mask, arsenic ions are implanted to form an N-type source/drain diffusion layer 107.

By carefully setting the formation conditions of the P+ type pocket layer 104 and the N- type layer 105, a positional relationship is established in which the P'' type pocket layer 104 is on the inside and the N- type layer 105 is on the outside, as shown in FIG. ζ can be formed. In this structure, the N-type layer 105 alleviates electric field concentration at the drain edge and suppresses the generation of hot carriers, and the P-type pocket layer 104 shortens the extension of the depletion layer toward the channel side. Punch-through can also be suppressed.

(Problem to be Solved by the Invention) However, even with the method described above, the P'' type pocket layer 104 for punch-through prevention is
Since they are formed using the same gate electrode 103 as a mask and substantially the same ion implantation angle as in the case of forming the P-type pocket layer 104 and the N-type layer 105, it is not possible to control each of them arbitrarily. For this reason, the degree of freedom in forming the length of the P'' type pocket 1 to the layer 104 is reduced, and because the length becomes short, there is a problem that a sufficient punch-through prevention effect may not work.

Therefore, if the concentration of the P-type pocket layer 104 is increased to obtain a sufficient punch-through prevention effect, the junction capacitance will increase, making high-speed operation disadvantageous, and the electric field strength will increase at the junction, resulting in an electric field relaxation effect. A new problem arises in that the generation of hot carriers increases.

In order to solve the above-mentioned problem in which the punch-through prevention effect does not work due to the low degree of freedom in forming the punch-through prevention region, the present invention provides ion implantation and electric field relaxation for forming the punch-through prevention region. The ion implantation angle difference for ion implantation to form the area for use is made sufficiently,
It is an object of the present invention to provide a method for manufacturing a semiconductor device with excellent electric field relaxation effect and punch-through prevention effect.

(Means for Solving the Problems) A method for manufacturing a semiconductor device of the present invention includes a first step of forming a gate insulating film on a first conductivity type semiconductor substrate, and a second step of forming a gate electrode on the gate insulating film. a third step of implanting impurity ions of the first conductivity type at an ungrooved angle of 20° or more and 90° with respect to the direction perpendicular to the substrate surface;
A fourth step of implanting second conductivity type impurity ions at an angle of 0° or less, a fifth step of forming a sidewall spacer at the edge of the gate electrode, and implanting second conductivity type impurity ions at a high concentration. This includes a sixth step.

(Function) In the method of manufacturing a semiconductor device according to the present invention, in order to implant the first conductivity type impurity at a relatively deep angle with respect to the direction perpendicular to the substrate surface, the implantation region is implanted deep inside the substrate under the gate electrode. The length of the implanted region of the first conductivity type can be left long in order to implant impurity ions of the second conductivity type at a shallow angle.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a process sectional view showing an embodiment of the present invention.

First, a P-type silicon semiconductor substrate 1 having a specific resistance of about 1 to 10 Ωcm is prepared, and a field oxide film 2 is formed in its non-active region by selective oxidation or the like. A gate oxide film 3 having a thickness of approximately 15 nm is formed on the surface of the active region of a P-type silicon semiconductor substrate 1 by thermal oxidation. Next, polysilicon that will become the gate electrode 4 is deposited over the entire surface to a thickness of about 300 nm using the CVD method, and 5XIO of phosphorus is added to make it conductive.
The polysilicon doped with phosphorus is then patterned using photolithography and dry etching techniques to form a gate electrode 4 on the gate oxide film 3 (see FIG. 1). See A))
.

Next, using the gate electrode 4 as a mask, boron is implanted into the P-type at a dose of 5 x 10 cm to 5 x 10" cm and an ion implantation energy of 60 to 120 KeV from a direction tilted 30° to 60° from the direction perpendicular to the wafer surface. Ions are implanted into the silicon semiconductor substrate 1 to form a P+ type region 5 for punch-through prevention.At this time, the ion implantation is performed while rotating the wafer so that it is symmetrical in both directions of the gate edge.

By this ion implantation, a P-type region 5 can be formed so as to be recessed in the lower part of the periphery within the edge of the gate electrode 4. The overlamp amount of the P+ type region 5 under the gate electrode 4 can be arbitrarily set depending on the ion implantation conditions (see FIG. 1(B)).

Next, ions are implanted into the P-type silicon semiconductor substrate 1 from a direction almost perpendicular to the wafer surface using the gate electrode 4 as a mask under the conditions of a phosphorus dose of about 2×10"cm-2 and an ion implantation energy of about 50 KeV. Inject, L
An N-type region 6 having a DD structure is formed. This N-type region 6
are formed on both sides of the P type silicon semiconductor substrate 1 under the gate electrode 4, and a pair of P' type regions 5 remain below the gate electrode 4 in the form of pockets adjacent to the N- type region 6 (see Fig. 1). (
(See C)) Furthermore, a CVD oxide film is deposited on the entire surface by the CVD method, and sidewall spacers 7 are formed at the edge portions on both sides of the gate electrode 4 by highly anisotropic dry etching. Then, using the gate electrode 4 and sidewall spacer 7 as a mask, arsenic is applied at a dose of 5×IO”cm−
Ions are implanted into the P-type silicon semiconductor substrate 1 under conditions of about 2 to form N source/drain diffusion layers 8 on both sides under the gate electrode 4. An N- type region 6 remains adjacent to and between this N" type source/drain diffusion layer 8 and P1 type region 5 (see FIG. 1(D)).

Although not shown in the drawings, an insulating film for interlayer isolation is formed, contact holes are opened in necessary locations for connection with metal wiring, and metal wiring is formed of an aluminum-silicon alloy. Finally, a protective passivation film is applied to complete the wafer process.

In the above embodiments, a method for manufacturing an N-channel field effect transistor has been described, but the method can also be applied to a P-channel field effect transistor by reversing the polarity of impurities.

In the above embodiment, the ion implantation for the P-type region is performed at an angle of 20' or more and less than 90' from the vertical direction of the wafer surface, and the ion implantation for the N-type region is performed at the same angle of <10'.
If it is performed at an angle of less than 100°, it is sufficiently effective in preventing punch-through.

(Effects of the Invention) As described above, according to the manufacturing method of the present invention, impurity ions of the first conductivity type are implanted at an angle of 20° or more and less than 90° with respect to the direction perpendicular to the surface of the semiconductor substrate, using the gate electrode as a mask. The amount of over-ramp under the gate electrode is controlled, and the second conductivity type impurity ions are implanted at an angle of 0° or more and 10° or less, leaving a region where the first conductivity type impurity ions are implanted to prevent punch-through and to relax the electric field. Since a second conductivity type impurity ion implantation region is formed for the purpose of preventing punch-through, the concentration, depth, and length conditions of the region for punch-through prevention can be set within a wide range, and the punch-through prevention effect and electric field relaxation effect can be improved. can be expected to improve.

[Brief explanation of drawings]

FIG. 1 is a process sectional view of a method of manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a sectional view of a device for explaining a conventional method of manufacturing a semiconductor device. 0 In the figure, 1... P type silicon semiconductor substrate, 3... Gate oxide film, 4... Gate electrode, 5... P' type region 6... N- type region, 7...・Sidewall spacer, 8N+ type source/drain diffusion layer. ■

Claims (1)

[Claims] A first step of forming a gate insulating film on a semiconductor substrate of a first conductivity type, a second step of forming a gate electrode on the gate insulating film, and using the gate electrode as a mask. a third step of implanting impurity ions of a first conductivity type into the semiconductor substrate at an angle of 20° or more and less than 90° with respect to a direction perpendicular to the surface of the semiconductor substrate to form a first region; Using the electrode as a mask, impurity ions of a second conductivity type opposite to the first conductivity type are implanted into the semiconductor substrate at an angle of 0° or more and 10° or less with respect to a direction perpendicular to the surface of the semiconductor substrate. a fourth step of forming a second region of a conductive type; a fifth step of forming sidewall spacers on both edge portions of the gate electrode; and a sixth step of implanting conductive type impurity ions into the semiconductor substrate at a high concentration.