JPH10321871A - Semiconductor device having soi structure and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a MOS transistor having a SOI(silicon-on-insulator) structure, which enables reduction in breakdown voltage between source and drain regions and improvement in the short-channel effect. SOLUTION: This semiconductor device has source/drain extended regions 114a, 114b doped with P<0> -type impurity ions at a low concentration and an N-type impurity implanted region formed in a lower part of a SOI layer 100c. The P<0> source extended region 114a is formed between a P<+> -source region 112a and an embedded oxide film 100b. The P<0> -drain extended region 114b is formed between a P<+> -source region 112b and the buried oxide film 100b. The N-type impurity implanted region formed in the lower part of the SOI layer 100c includes three regions, that is, an N<-> -region 116a, an N<--> -region 102 and an N<-> -region 116b. Thus, even if the thickness of the SOI layer is not smaller than 1400 Å, the short channel effect can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to SOI (Silic).
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an on-on-insulator structure and a method of manufacturing the same, and more particularly, to reducing a breakdown voltage between a source and a drain region of a MOS transistor and improving a short channel effect. MOS transistor having an SOI structure and a method of manufacturing the same.

[0002]

2. Description of the Related Art Currently, in the manufacture of integrated circuits, PMO
The gate electrode of the S transistor is formed of the same material as the gate electrode of the NMOS transistor, for example, an N ⁺ -type polysilicon film to simplify the manufacturing process.
In a bulk PMOS transistor, a buried channel is generally used.
l) is used. In a PMOS transistor having an SOI structure, the silicon thickness of a channel region is small, and an N ⁺ type polysilicon film is used as a gate electrode. In this case, the SOI PMOS transistor has an accumulation mode type similar to that of a buried channel.
pe) is used.

FIG. 1 is a sectional view showing a conventional MOS transistor having an SOI structure. Conventional MOS transistors have an SOI structure formed as a silicon substrate 10a, a buried oxide film 10b, and an SOI layer (for example, a P- type semiconductor layer) 10c. Buried oxide film 10b is formed on the main surface of silicon substrate 10a. SO
I layer 10c is formed on buried oxide film 10b. S
The MOS transistor formed on the OI layer 10c
P ⁺ diffusion regions (eg, source / drain regions) 18,
A channel region (for example, a part of a P ⁻ type semiconductor layer) and a gate electrode 1 formed of P ⁺ type polysilicon
4 inclusive. A gate electrode 14 is formed on the channel region with the gate oxide film 12 therebetween. Further, gate spacers 16 are formed on both side walls of the gate electrode 14.

In the structure described above, when an N ⁺ type polysilicon layer is used for the gate electrode 14, if the SOI layer 10c is used with a thickness of less than about 1000 °, no gate voltage is applied to the channel region. However, it is completely depleted, that is, depleted. It is because of a band structural difference between a channel and a gate electrode.
ence). Therefore, in the lower portion (bottom portion) of the SOI layer 10c, a body current flow path (neutral region) (body current) formed from the P ⁺ source, the P ⁻ channel, and the P ⁺ drain type region
flow path (neutralregio
n)) does not occur. When a negative gate voltage is applied, the accumulation channel is formed on the surface of the channel region.
nnel) is formed.

However, the thickness of the SOI layer 10c is reduced to about 140
In the conventional MOS transistor having the above-described structure of 0 ° or more, the channel region is not completely depleted when no gate voltage is applied. Therefore, S
P ⁺ source, P ^- channel,
Then, a body current flow path (neutral area) formed by the P ^- drain type region is generated, so that a leak current is generated even when no gate voltage is applied, and the current flows through the body current flow path. Become. When a voltage is applied between the source and drain regions, the lower portion of the channel region is easily depleted. This reduces the source / drain breakdown voltage.

Further, in the above-described structure, when the length of the channel is shortened, a new problem occurs that the short channel effect is greatly increased.

[0007]

SUMMARY OF THE INVENTION The present invention provides an SOI structure that can effectively reduce the breakdown voltage between the source and drain regions and improve the short channel effect. Holding M
An object is to provide an OS transistor.

It is another object of the present invention to effectively reduce the breakdown voltage between the source and drain regions and improve the short channel effect.
An object of the present invention is to provide a method for manufacturing a MOS transistor having an OI structure.

[0009]

According to the present invention, there is provided a semiconductor device having an SOI structure, comprising: a semiconductor substrate having a main surface; an insulating layer formed on the main surface of the semiconductor substrate; A semiconductor layer formed on the insulating layer, a first conductivity type channel region formed in the element forming region of the semiconductor layer, and a first layer formed in a lower portion of the semiconductor layer. An impurity-implanted region having a second conductivity type opposite to the conductivity type, a pair of impurity diffusion regions of the first conductivity type for sandwiching a channel region in the element formation region, and a gate oxide film interposed on the channel region. Since the impurity diffusion regions in the element formation region are formed below the formed gate electrodes, the impurity concentration is set to be relatively lower than that of the impurity diffusion regions. Was the first conductivity type pair formed diffusion region extension region (Diffusion regio
n extension, and an injection region extension region (injection region) formed at both ends of the impurity implantation region in the element formation region and paired with the second conductivity type located between each diffusion region extension region and the impurity implantation region.
a pair of PN junctions is formed below the impurity diffusion region, and each PN junction is formed in each diffusion region region and each implantation region extension region adjacent thereto, and each injection region The extension region is configured to have a relatively higher doping concentration than the impurity implantation region.

In order to achieve the above object, according to the present invention, a method of manufacturing a semiconductor device having an SOI structure further comprises the steps of: providing an insulating layer for forming an SOI substrate on a main surface of the semiconductor substrate; Forming a
Implanting an impurity into the semiconductor layer to form an impurity implantation region directly in contact with the insulating layer; and forming a semiconductor layer to form a first conductivity type element formation region on the second conductivity type impurity implantation region. Implanting impurities into the device, forming a gate structure on the element formation region, and implanting impurities into the element formation region using the gate structure as a mask to form a first conductivity type first impurity implantation layer. Ion implantation, implanting impurities into the element formation region using the gate structure as a mask to form a first conductivity type second impurity implantation layer directly below the first impurity implantation layer, impurity implantation region Implanting impurities into the impurity implantation region using the gate structure as a mask to form a third impurity implantation layer of the second conductivity type therein; forming the first, second, and third impurity implantation layers; Expansion Performing a heat treatment to cause the first impurity-implanted layer to be diffused to form a paired source / drain region, and the second impurity-implanted layer to have a relatively low doping compared to the source / drain region. The third impurity implantation layer is diffused to form a paired implantation region extension region at both ends of the impurity implantation region, and is diffused to form a paired source / drain region extension region having a concentration.

Referring to FIG. 5, the structure of the present invention will be described. A semiconductor device having a novel SOI structure according to an embodiment of the present invention provides an advantage of a MOS transistor having an SOI structure, and a thickness of an SOI layer. Is 1400 ° or more, a PN junction formed below the source / drain region can effectively prevent a body current flow path generated in a lower portion of the SOI layer. In addition, the P of the present invention
It is possible to provide an advantage that a depletion region hardly occurs in a lower portion of the SOI layer due to the N junction. as a result,
The channel punch-through (punch-through) phenomenon does not occur, so that the short channel effect can be improved.

Further, the present invention provides a method for manufacturing the above MOS transistor.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to FIGS.

Referring to FIG. 5, a novel MOS transistor according to an embodiment of the present invention comprises a silicon substrate 100.
a, a buried oxide film 100b, and an SOI layer (for example,
The SOI structure formed on the P-type semiconductor layer) 100c is included. The buried oxide film 100b is formed on the main surface of the semiconductor substrate 100a. SOI layer 100c is formed on buried oxide film 100b. MOS transistor P ⁺ diffusion regions (for example, source and drain regions) 112 a and 112 b formed on SOI layer 100 c, channel region (for example, a part of P ⁻ type semiconductor layer) 10
4, and a gate electrode 108 formed of P ⁺ type polysilicon. The gate electrode 108 is formed on the channel region with the gate oxide film 106 interposed therebetween.
Gate spacers 110 are formed on both side walls of the gate electrode 108.

The MOS transistor has source and drain extension regions 114a and 114b lightly doped with P ⁰ impurity ions and an N-type impurity implantation region formed under the SOI layer 100c. The P ⁰ source extension region 114a is formed between the P ⁺ source region 112a and the buried oxide film 100b, and the P ⁰ drain extension region 114b is formed between the P ⁺ source region 112b and the buried oxide film 100b. ing. SOI layer 100c
N-type impurity implantation region formed in the lower portion of the three regions, i.e., N ^- -type region 116a, N ^- -type region 10
2, and N ^- type region 116b. These areas 1
16a, 102 and 116b are source drain extension areas 1
The body current flow path (body current fl) is provided between the lower portions 14a and 114b of the SOI layer 100c.
ow path) is formed in series so as to prevent the occurrence of (ow path). Therefore, when a voltage is applied to the source and drain regions 112a and 112b, PN junctions are formed below the source and drain regions 112a and 112b, respectively. Each PN junction has a source / drain extension region 114a or 114b and an N ⁻ type region (ie,
N ^- type extended region) 116a to 116b. These PN junctions are different from the P ⁺ / P ⁻ junctions of the conventional MOS transistor shown in FIG.
Is approximately 1400 ° or more, the generation of a body current flow path is effectively prevented. Further, even when the thickness of the SOI layer 100c becomes about 1400 ° or more, a depletion region is not easily formed in the SOI layer 100c due to the PN junction. This causes a channel punch-through phenomenon to be difficult, and the short channel effect is improved.

Hereinafter, a method of manufacturing the above-described MOS transistor will be described with reference to FIGS.

Referring to FIG. 2, a silicon substrate 100
a, a buried oxide film 100b, and an SOI layer (for example,
An SOI substrate 100 having a (semiconductor layer) 100c is formed. In order to form the N ⁻ -type impurity implantation region 102 in the lower portion of the SOI layer 100c, N-type impurity ions, for example,
Phosphorus (P) ions are implanted into the SOI layer 100c of the SOI substrate 100 at a dose of about 8E11 atoms / cm ² and an energy of about 100 keV. Here, the term "dose" refers to the dopant doping amount of the impurity dopant. Next, a P-type impurity ion, for example, BF ₂ ion is formed at a dose of about 7E11 atoms / cm ² and about 40 keV to form the P ⁻ -type channel region 104 on the element formation region, particularly, the N ⁻ -type impurity implantation region 102. Ions are implanted into the SOI layer 100c with the energy of.

As shown in FIG. 3, a gate oxide film 110 and a gate polysilicon layer 108 are sequentially formed by ordinary photolithography and patterned. Then, gate spacers 110 are formed on both side walls of the gate electrode to form a gate structure.

In FIG. 4, P-type impurity ions, eg, BF ₂ ions, are implanted in SOI layer 100c at a dose of about 2E15 atoms / cm ² and an energy of about 30 keV using the gate structure as a source / drain formation mask. Injected. In this way, the impurity implantation layers 112 are formed in the SOI layers 100c on both sides of the gate structure. Similarly, since BF ₂ ions form the impurity implantation layer 114 below the impurity implantation layer 112 in the SOI layer 100c, the dose of about 1E15 atoms / cm ² and 60
Ions are implanted into the SOI layer 100c at an energy of keV. As here depicted, the impurity-implanted layer 114 has a relatively low doping concentration than the impurity-implanted layer 112 for source / drain, P ^- -type channel region 1
It has a higher doping concentration as compared with 04. Next, for example, N-type impurity ions, arsenic (As) ions, the gate structure to form the impurity-implanted layer 116 used as a mask, the energy of about 2E13 dose and about 180 keV, N ^- -type implanted region Ions are implanted into 102. By performing arsenic ion implantation at an angle of 15 degrees with respect to the SOI substrate 100, the impurity implantation
N ⁻ type impurity implanted region 1
02 can be formed in the inner part.

Finally, as shown in FIG. 5, the impurity implantation layers 112, 114 and 116 are subjected to a heat treatment (therma).
l treatment), and the P ⁺ type source / drain regions 112a, 112b, P ⁰ type source /
Drain extension regions 114a and 114b and N ⁻ -type regions 116a and 116b are simultaneously formed.

As shown in FIG. 5, the P ⁰ type source /
The drain extension regions 114a and 114b are P ⁺ type sources /
The drain regions 112a and 112b are respectively located below. N ⁻ -type regions 116 a and 116 b are formed at both ends of the N ⁻ -type impurity implantation region 102 and on the side surfaces of the P ⁰ source drain extension regions 114 a and 114 b. P
^{The 0-} type source extension region 114a and the N ^- type region (ie,
The N ⁻ -type extended region) 116a has an SOI layer 100c of about 1
Even with a thickness of 400 ° or more, one PN junction is formed to effectively prevent the generation of a body current flow path in the lower portion of the SOI layer 100c between the source and drain regions. P ⁰
The type drain extension region 114b and the N ⁻ type region (ie, the N ⁻ type extension region) 116b are used to effectively prevent a body current flow path in a lower portion of the SOI layer 10c between the drain and the source region. Construct a PN junction.
As a result, as shown in FIG. 6, the breakdown voltage between the source and drain regions is improved.

[0022]

The present invention provides the advantage of a MOS transistor having an SOI structure, in which the thickness of the SOI layer is 1400Å.
With the above, a body current flow path generated from the lower portion of the SOI layer at the PN junction formed below the source / drain region can be effectively prevented.

Further, the present invention can provide an advantage that a depletion region hardly occurs in a lower portion of the SOI layer due to a PN junction. As a result, there is an effect that the channel punch-through phenomenon does not occur and thus the short channel effect can be improved.

That is, the present invention can be summarized as follows. The present invention relates to a semiconductor device having an SOI structure and a method of manufacturing the same, and is formed in a lower portion of source / drain extension regions 114a and 114b lightly doped with P ⁰ type impurity ions and an SOI layer 100c. Including an N-type impurity implantation region. P0 source extension region 114a is formed between the buried oxide film 100b and the P ⁺ source region 112a, P ⁰ drain extension region 114b is buried oxide layer 100 and the P ⁺ source region 112b
b. The N-type impurity implanted region formed in the lower portion of the SOI layer 100c has three regions, namely, an N ⁻ type region 116a, an N ⁻ type region 102, and
Includes N ^- type region 116b. These areas 116a, 10
2, 116b are formed in series between the source and drain extension regions 114a and 114b to prevent a body current flow path generated from a lower portion of the SOI layer 100c. With such a semiconductor device and a method of manufacturing the same, the advantage of a MOS transistor having an SOI structure is provided.
The body flow path generated from the lower part of the SOI layer due to the PN junction formed under the source / drain region can be effectively prevented. Further, the present invention can provide an advantage that a depletion region is hardly generated in a lower portion of the SOI layer by a PN junction. As a result, the channel punch-through phenomenon does not occur, so that the short channel effect can be improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a conventional MOS transistor having an SOI structure.

FIG. 2 shows a MOS having an SOI structure according to an embodiment of the present invention.
FIG. 4 is a cross-sectional view illustrating a transistor.

FIG. 3 shows a MOS having an SOI structure according to an embodiment of the present invention;
FIG. 4 is a cross-sectional view illustrating a transistor.

FIG. 4 shows a MOS having an SOI structure according to an embodiment of the present invention.
FIG. 4 is a cross-sectional view illustrating a transistor.

FIG. 5 shows a MOS having an SOI structure according to an embodiment of the present invention.
FIG. 4 is a cross-sectional view illustrating a transistor.

FIG. 6 is a graph showing characteristics of the MOS transistors of FIGS. 1 and 5;

[Explanation of symbols]

10a, 100a: Silicon substrate 10b, 100b: Buried oxide film 10c, 100c: SOI layer 12, 106: Gate oxide film 14, 108: Gate electrode 16, 110: Gate spacer 18: Source / drain region 102: N ^- type region 104 ... P ^- -type channel region 112a, 112b ... P ⁺ source / drain regions 114a, 114b ... source / drain extension regions 116a, 116b ... N ^- -type region

Claims (13)

[Claims] A semiconductor substrate having a main surface; an insulating layer formed on the main surface of the semiconductor substrate; a semiconductor layer having an element formation region and formed on the insulating layer; A first conductivity type channel region formed in the device formation region, an impurity implantation region formed in a lower portion of the semiconductor layer and having a conductivity type opposite to the first conductivity type, and A first conductivity type impurity diffusion region paired with a channel region in the region interposed therebetween, a gate electrode formed on the channel region with a gate oxide film interposed therebetween, and an impurity diffusion region in the element formation region. A pair of first conductivity type diffusion region extension regions formed on the lower side and formed with a lower doping concentration than the impurity diffusion region; and formed at both ends of an impurity implantation region in the element formation region. A pair of second conductivity type implanted region extended regions located between each of the diffused region extended regions and the impurity implanted region, and a pair of PNs below the impurity diffused region. A junction is formed, and each PN junction is constituted by each of the diffusion region regions and each of the implantation region extension regions adjacent thereto, and these implantation region extension regions have a higher doping concentration than the impurity implantation regions. A semiconductor device having an SOI structure. 2. The semiconductor device according to claim 1, wherein said semiconductor layer has a thickness of about 1400 ° or more. 3. The semiconductor device according to claim 1, wherein all of the diffusion region extension region, the implantation region extension region, and the impurity implantation region are formed so as to directly contact an insulating layer. Semiconductor device. 4. A step of forming a semiconductor layer between an insulating layer for forming an SOI substrate on a main surface of the semiconductor substrate, and forming an impurity-implanted region in direct contact with the insulating layer in the semiconductor layer. Implanting impurities into the semiconductor layer to form a first conductivity type element formation region on the second conductivity type impurity implantation region; and forming a gate structure on the element formation region. Forming a first impurity implanted layer using a gate structure as a mask to form a first impurity implanted layer of a first conductivity type; Implanting an impurity into the element formation region using a gate structure as a mask to form a second impurity implantation layer of a first conductivity type below, and a second conductivity type implanted inside the impurity implantation region. Implanting impurities into the impurity implantation region using a gate structure as a mask to form a third impurity implantation layer; and diffusing the first impurity layer, the second impurity layer, and the third impurity implantation layer, respectively. Performing a heat treatment to cause the first impurity-implanted layer to be diffused to form a paired source / drain region.
The third impurity implantation layer is diffused to form a paired source / drain region extension region having a lower doping concentration than the source / drain region, and the third impurity implantation layer is paired at both ends of the impurity implantation region. A method for manufacturing a semiconductor device, having a SOI structure diffused to form a region. 5. The device according to claim 4, wherein all of the diffusion region extension region, the implantation region extension region, and the impurity implantation region are formed so as to directly contact the insulating layer. A method for manufacturing a semiconductor device. 6. The impurity-implanted region is formed by ion-implanting phosphorus (P) ions.
13. The method for manufacturing a semiconductor device according to item 5. 7. The ion implantation of phosphorus (P) ions is performed at a dose of about 8E11 atoms / cm ² and about 100 ke.
7. The method according to claim 6, wherein the method is performed with an energy of V. 8. The method according to claim 4, wherein the element formation region is formed by implanting BF ₂ ions. 9. The method according to claim 1, wherein the ion implantation of the BF ₂ ions is about 7E.
9. The method according to claim 8, wherein the method is performed at a dose of 11 atoms / cm < ² > and an energy of about 40 keV. 10. The method of claim 1, wherein the first impurity implantation layer has a thickness of about 2E15.
The method of manufacturing a semiconductor device according to claim 4, the energy of the atoms / cm ² dose and about 30keV, characterized in that it is formed by implanting BF ₂ ions. 11. The method according to claim 1, wherein the second impurity implantation layer has a thickness of about 1E15.
The method of manufacturing a semiconductor device according to claim 4, the dose and approximately BF ₂ ions at an energy of 60keV in atoms / cm ^2, characterized in that it is formed by ion implantation. 12. The method according to claim 11, wherein the third impurity implantation layer has a thickness of about 2E13.
The method according to claim 4, wherein the semiconductor device is formed by implanting arsenic (As) ions at a dose of atoms / cm ² and an energy of about 180 keV. 13. The method according to claim 12, wherein the arsenic (As) ions are implanted into the SOI substrate at an angle of about 15 degrees.