JPH03276730A - Mos transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To decrease a threshold voltage and to suppress a short-channel effect by forming a low-concentration first-conductivity type surface layer on the surface of a first-conductivity type silicon substrate, and forming second- conductivity type first and second diffusing layers and a high-concentration first-conductivity type semiconductor region. CONSTITUTION:In a silicon substrate 1 (p-type well region), a low-concentration n<->-type diffusing region 5 (second-conductivity type first diffusing region) which is to become the parts of a source and a drain) is formed directly beneath a side wall oxide film 4. A high-concentration n<+>-type diffusing region 6 (second- conductivity type second diffusing region) which is to become the source and the drain is formed in the lateral direction of the n<->-type diffusing region 5. A low-concentration p<->-type surface layer 7 (first conductivity type surface layer) is formed in a region which is bonded to the n<->-type diffusing region 5 in the vicinity of the surface of the silicon substrate 1. A high-concentration p<+>-type semiconductor region 8 (first-conductivity type semiconductor region) is formed directly beneath the p<->-type surface layer 7, the n<->-type diffusing region 5 and the p<+>-type diffusing region 6.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a low concentration diffusion drain structure (hereinafter referred to as "LD").
My name is DJ. ) and a method for manufacturing the same.

[Conventional technology]

Regarding the conventional LDD structure MOS)
This will be explained based on the diagram.

FIG. 4 is a sectional view showing the main parts of a conventional N-channel type MO3 transistor.

As shown in FIG. 4, an oxide film (not shown) is deposited on a silicon substrate 1" (p-type well region), a polysilicon film (not shown) is deposited on this oxide film, and then a photo A gate oxide film 2 is formed by a lithography technique or the like, and a gate electrode 3 made of a polysilicon film is further formed on the gate oxide film 2.

Then, by ion-implanting phosphorus (P) using the gate electrode 3 as a mask, a low concentration n diffusion region 5 is formed.

Next, a sidewall oxide film 4 to serve as a spacer is formed on the sidewall of the gate electrode 3 by chemical vapor deposition (CVD).

Then, by ion-implanting arsenic (As) using the gate electrode 3 and the sidewall insulating film 4 as a mask, MO
Highly doped n diffusion regions 6 are formed which will become the drain and source of the S transistor.

1 like this. , DD structure) Randisk reduces the electric field strength near the drain by forming a low concentration n-diffusion region 5 to alleviate the impurity concentration gradient under the edge of the gate electrode 3. I can do it.

[Problem to be solved by the invention]

However, in such a conventional MOS transistor, when hot carriers are generated, the generation location is the lower part of the sidewall insulating film 4. On the other hand, the sidewall oxide film 4 is made of C
It is formed by the VD method and has many interface states. Therefore, the injection of hot carriers into the sidewall insulating film 4 is promoted and trapping becomes more likely, resulting in a problem that the characteristics of the MOS transistor deteriorate.

Further, when the dark value voltage Vth is lowered in order to bring out the performance, there is a problem that the short channel effect becomes significant.

SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a MOS transistor that can reduce the amount of hot carriers trapped, suppress the short channel effect, and reduce the dark value voltage, and a method for manufacturing the same.

[Means to solve the problem]

The MOS transistor according to claim (1) includes a silicon substrate of a first conductivity type, a gate electrode formed on this silicon substrate, and a low concentration layer forming part of a source and a drain formed under an end of this gate electrode. a first diffusion region of a second conductivity type formed on the outside of the first diffusion region of a second conductivity type, a highly doped second diffusion region of a second conductivity type forming a source and a drain; Near the surface of the substrate, a second
a low concentration first conductivity type surface layer formed so as to be in contact with the first conductivity type diffusion region, and this first conductivity type surface layer;
The semiconductor device includes a first diffusion region of the second conductivity type and a high concentration semiconductor region of the first conductivity type formed directly under the second diffusion region of the second conductivity type.

The method for manufacturing a MOS transistor according to claim (2) includes:
By forming a protective film on a silicon substrate of the first conductivity type and ion-implanting impurities into the silicon substrate through this protective film, a high concentration of the first conductivity type is formed deep from the surface of the silicon substrate. a step of forming a first conductivity type surface layer with a low concentration near the surface of the silicon substrate by ion-implanting impurities into the silicon substrate; and a step of forming a gate electrode on the silicon substrate. By forming the gate electrode and implanting impurity ions using this gate electrode as a mask, a low-concentration first conductivity type of the second conductivity type is formed under the edge of the gate electrode to become part of the source and drain.
A process of forming a diffusion region of the gate electrode, a process of forming a sidewall insulating film to serve as a spacer on the sidewall of the gate electrode, and a process of ion implantation of impurities using the gate electrode and the sidewall insulating film as a mask to form a high concentration diffusion region that will become the source and drain. forming a second diffusion region of a second conductivity type.

[Effect]

According to the configuration of the present invention, by forming a low concentration surface layer of the first conductivity type on the surface of the silicon substrate of the first conductivity type, the dark value voltage can be lowered and the layer becomes a source and a drain. By forming a highly concentrated semiconductor region of the first conductivity type directly under the first diffusion region of the second conductivity type, the second diffusion layer of the second conductivity type, and the surface layer of the first conductivity type, By suppressing the spread of the depletion layer, the short channel effect can be suppressed. In addition, by forming a low concentration first conductivity type surface layer and a low concentration second conductivity type first diffusion region, the electric field near the drain is relaxed, and the peak of the electric field strength is shifted from just below the sidewall oxide film. It can be moved below the edge of the gate electrode, and the amount of hot carriers trapped in the sidewall oxide film can be reduced.

〔Example〕

FIG. 1 is a sectional view showing a main part of an N-channel type MO3 transistor according to an embodiment of the present invention.

As shown in FIG. 1, a gate oxide film 2 is formed on a silicon substrate 1, a gate electrode 3 is formed on the gate oxide film 2, and a sidewall oxide film 4 is formed on the sidewalls of the gate electrode 3. did.

In the silicon substrate 1 (p-type well region), a low concentration n-type diffusion region 5 (first diffusion region of second conductivity type) which becomes part of the source and drain is located directly under the sidewall oxide film 4.
In the lateral direction of this n-type diffusion region 5, a highly concentrated n-type diffusion region 6 (second
A conductive type second diffusion region) was formed. In addition, a low concentration p-type surface layer 7 (first conductivity type surface layer) was formed near the surface of the silicon substrate 1 and in a region that is in contact with the n-type diffusion region 5.

Also, p-type surface layer 7. Immediately below the n-type diffusion region 5 and the n-type diffusion region 6, there is a highly doped p-type semiconductor region 8 (
A semiconductor region of the first conductivity type) was formed.

FIGS. 2(a) to 2(a) are cross-sectional views in the order of steps showing an example in which the method for manufacturing a MOS transistor according to an embodiment of the present invention is applied to an N-channel type MO3 transistor.

As shown in FIG. 2(a), the surface of the silicon substrate 1 (p-type well region) is thermally oxidized to form a silicon oxide film 9 having a thickness of about 500 nm and serving as a protective film.

Next, as shown in FIG. 2 Φ), a dose of 2×10 12 cm
Ion implantation of poron (B) (acceleration voltage 150 keV,
By following arrow A), a highly doped p+ type semiconductor region 8 is formed deep from the surface of the silicon substrate 1.

Next, as shown in FIG. 2(C), the surface was
By ion-implanting phosphorus (P) of .

Next, the silicon oxide film 9 serving as a protective film is removed, and the surface of the p-type surface layer 7 is thermally oxidized to form a silicon oxide film 10 with a thickness of approximately 170 mm. Then, on this silicon oxide film 10, a film with a thickness of about 4
A polycrystalline silicon film 11 having a thickness of 1,000 mm is formed.

Next, as shown in FIG. 2(d), the silicon oxide film 10 and the polycrystalline silicon film 11 are etched into a wiring shape using photoresist technology and etching technology, thereby forming a gate oxide film 2 and a gate electrode 3. .

Next, as shown in FIG. 2(e), using the gate electrode 3 as a mask, the p-type surface layer 7 is exposed to a dose of 2×10
Ion implantation of phosphorus (P) at cm-2 (acceleration voltage 30k)
eV), a low concentration n-type diffusion wA@5 (second conductivity type first
diffusion region).

Next, as shown in FIG. 2(f), a silicon oxide film (not shown) with a thickness of approximately 2,500 yen is deposited on the surface using the CVD method, and sidewall oxide film (not shown), which will become a spacer, is deposited using photolithography and etching techniques. A film 4 is formed.

Thereafter, using the sidewall oxide film 4 and gate electrode 3 as a mask, arsenic (As) is ion-implanted at a dose of 5 x 10"cm-2 to form a highly concentrated n-type material that will become the source and drain. A diffusion region 6 (second diffusion jl t!! of the second conductivity type) is formed.

The MO3+- run lister formed in this way can lower the threshold voltage by forming a low concentration p- type surface layer 7 on the surface of the silicon substrate 1, and
By forming a highly doped p-type semiconductor region 8 directly under the −-type surface layer 7, the lightly doped n-type diffusion region 5, and the heavily doped n-type diffused region 6, which become the source and drain. By suppressing the spread of the depletion layer, the short channel effect can be suppressed. Furthermore, by forming the low concentration p~ type surface layer 7 and the low concentration n type diffusion region 5, the electric field strength near the drain can be relaxed, and the electric field peak position can be moved directly below the sidewall oxide film 4. The amount of hot carriers trapped in the sidewall oxide film 4 can be reduced by moving the hot carriers from 1 to below the edge of the gate electrode 3.1 FIG. FIG. 3 is a diagram showing the impurity concentration in the depth direction from the surface of a silicon substrate forming an S transistor.

In FIG. 3, the vertical axis indicates the impurity concentration, and the horizontal axis indicates the position in the depth direction from the surface of the silicon substrate (that is, the 7th part of the silicon substrate 1.degree. 1.degree. in FIG. 1 and FIG. 4).

Further, X represents the impurity concentration in the depth direction of the silicon substrate of the embodiment, Y represents the impurity concentration in the depth direction of the conventional silicon substrate, and X represents the diffusion length of the source and drain.

As shown in Figure 3, the impurity concentration of the conventional silicon substrate has a peak near the surface of the silicon substrate 1'' and decreases in the depth direction, whereas the impurity concentration of the silicon substrate of the example The impurity concentration of the silicon substrate 1 is relatively low on the surface of the silicon substrate 1 (due to the low concentration p-type surface layer 7), and the impurity concentration peaks are at the high concentration of the source and drain. It is located near the interface between the diffusion region 6 and the highly doped p-type semiconductor region 8.

2. Although this embodiment shows an N-channel type MO3 transistor and its manufacturing method, it can also be applied to a P-channel type MOS transistor. In that case, the conductivity type of the impurity to be ion-implanted into the silicon substrate may be changed from n-type to p-type and from p-type to n-type.

〔Effect of the invention〕

According to the MOS transistor and the method of manufacturing the same of the present invention, the first conductive type silicon substrate has a low concentration on the surface of the silicon substrate of the first conductivity type.
By forming a conductivity type surface layer, the dark voltage can be lowered, and the second conductivity type first diffusion fJ (jli and the second conductivity type second diffusion layer By forming a highly concentrated semiconductor region of the first conductivity type directly under the surface layer of the first conductivity type, the short channel effect can be suppressed by suppressing the spread of the depletion layer. The occurrence of through-through can be eliminated.Also, by forming a lightly doped first conductivity type surface layer and a lightly doped second conductivity type first diffusion region, the electric field near the drain can be relaxed and the electric field The intensity peak can be moved from directly under the sidewall oxide film to under the edge of the gate electrode, and the amount of hot carriers trapped in the sidewall oxide film can be reduced.As a result, the short channel effect can be suppressed, and A high-performance MOS transistor that can reduce the dark voltage can be obtained.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing the main parts of an N-channel MO3 transistor according to an embodiment of the present invention, and FIGS. 3 is a cross-sectional view showing an example of application to a type MO3 transistor in the order of steps; FIG. 3 is a diagram showing the impurity concentration in the depth direction from the surface of the silicon substrate constituting the N-channel type MO3 transistor of the embodiment and the conventional example; FIG. is the conventional N
FIG. 3 is a cross-sectional view showing a main part of a channel type MO3 transistor. 1... Silicon substrate, 3... Gate electrode, 4...
sidewall insulating film, 5...n-diffusion region (first conductivity type
diffusion region), 6... n1 diffusion region (second diffusion region of second conductivity type), 7... surface layer, 8... p' type semiconductor region 8 (semiconductor region of first conductivity type). ), 9...Silicone oxide film (protective film) 5-m-Silicone--...Ge "electrode--1 layer 15 gates" and f: Non-1--n-N-oxygen Boundary (early 2 conductivity!'s 1st Kousuke) - 1-n + Mineral region (second bound power field's 2nd Koukan area) - 1-p
-Surface layer (first conductivity type dispersion layer)...-p + cattle conductor back 8 (semi-conducting stop mass of bud 1 exclusive power type) - - one bait Hisirifun (
Figure 2 Figure Figure Figure

Claims (2)

[Claims] (1) A silicon substrate of a first conductivity type, a gate electrode formed on this silicon substrate, and a first silicon substrate of a second conductivity type with a low concentration that forms part of the source and drain formed under the edge of this gate electrode. a second diffusion region of a second conductivity type with a high concentration to serve as a source and a drain formed outside the first diffusion region of the second conductivity type; the first of the second conductivity type
a low concentration surface layer of a first conductivity type formed so as to be in contact with a diffusion region of the first conductivity type; a highly concentrated semiconductor region of the first conductivity type formed directly under the diffusion region of No. 2;
S transistor. (2) Forming a protective film on the silicon substrate of the first conductivity type; and ion-implanting impurities into the silicon substrate through this protective film to achieve a high concentration deep from the surface of the silicon substrate. forming a first conductivity type semiconductor region with a low concentration near the surface of the silicon substrate by ion-implanting impurities into the silicon substrate; By forming a gate electrode on the silicon substrate and implanting impurity ions using this gate electrode as a mask, a low-concentration second conductivity type that becomes part of the source and drain is formed under the edge of the gate electrode. A step of forming a first diffusion region, a step of forming a sidewall insulating film to serve as a spacer on the sidewall of the gate electrode, and ion implantation of an impurity using the gate electrode and the sidewall insulating film as a mask, the source and A method for manufacturing a MOS transistor, comprising the step of forming a second diffusion region of a second conductivity type with high concentration to serve as a drain.