JPH06326122A - Mos semiconductor device and its manufacture - Google Patents
Mos semiconductor device and its manufactureInfo
- Publication number
- JPH06326122A JPH06326122A JP5114459A JP11445993A JPH06326122A JP H06326122 A JPH06326122 A JP H06326122A JP 5114459 A JP5114459 A JP 5114459A JP 11445993 A JP11445993 A JP 11445993A JP H06326122 A JPH06326122 A JP H06326122A
- Authority
- JP
- Japan
- Prior art keywords
- diffusion layer
- concentration diffusion
- type
- gate electrode
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 96
- 238000004519 manufacturing process Methods 0.000 title claims description 23
- 238000009792 diffusion process Methods 0.000 claims description 100
- 239000000758 substrate Substances 0.000 claims description 30
- 238000000034 method Methods 0.000 claims description 28
- 238000005530 etching Methods 0.000 claims description 9
- 238000002955 isolation Methods 0.000 claims description 8
- 238000005468 ion implantation Methods 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 6
- 230000001590 oxidative effect Effects 0.000 claims description 5
- 229910021332 silicide Inorganic materials 0.000 abstract description 20
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract description 20
- 230000000694 effects Effects 0.000 abstract description 15
- 230000003071 parasitic effect Effects 0.000 abstract description 8
- 238000002513 implantation Methods 0.000 description 9
- 230000006866 deterioration Effects 0.000 description 8
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 3
- -1 arsenic ions Chemical class 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000002784 hot electron Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ＭＯＳ型半導体装置の
微細化を実現し、かつ高速で高信頼性で、しかも低消費
電力な半導体集積回路に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit which realizes miniaturization of a MOS type semiconductor device, has high speed and high reliability, and has low power consumption.
【０００２】[0002]
【従来の技術】超集積回路装置いわゆるＶＬＳＩにおい
て、ＭＯＳ型半導体装置は高集積化の要請からハーフミ
クロン領域に微細化されつつある。この微細化に伴い、
ホットキャリアによる電気特性劣化が深刻な問題となっ
ている。このホットキャリア劣化耐性を維持した状態
で、しかも、駆動能力を向上したＭＯＳ型半導体装置と
して、非対称型ＬＤＤＭＯＳＦＥＴ構造が提案されてい
る。例えばI.E.E.E.1992 Symposium on VLSI Technolog
y Digest of Technical Papers pp88-89にT.Horiuchi等
によって選択的酸化膜堆積技術を用いた非対称型ＬＤＤ
ＭＯＳＦＥＴ構造が提案されている。2. Description of the Related Art In super integrated circuit devices, so-called VLSI, MOS type semiconductor devices are being miniaturized into a half micron region due to the demand for higher integration. With this miniaturization,
Deterioration of electrical characteristics due to hot carriers has become a serious problem. An asymmetric LDDMOSFET structure has been proposed as a MOS semiconductor device in which the drive capability is improved while maintaining the resistance to hot carrier deterioration. For example, IEEE 1992 Symposium on VLSI Technolog
y Digest of Technical Papers pp 88-89 by T. Horiuchi et al. Asymmetric LDD using selective oxide film deposition technology
MOSFET structures have been proposed.
【０００３】選択的酸化膜堆積技術を用いた非対称型Ｌ
ＤＤＭＯＳＦＥＴ構造のＭＯＳ型半導体装置を図７に、
及びその製造方法を図８に示す。同図において、２１は
ｐ型半導体基板、２２はＬＯＣＯＳ、２３はゲート酸化
膜、２４はゲート電極、２５はゲート側壁、２６はｎ型
低濃度拡散層、２７はｎ型高濃度拡散層、２８はレジス
トである。Asymmetric L using selective oxide deposition technique
A MOS type semiconductor device having a DDMOSFET structure is shown in FIG.
And the manufacturing method thereof is shown in FIG. In the figure, 21 is a p-type semiconductor substrate, 22 is a LOCOS, 23 is a gate oxide film, 24 is a gate electrode, 25 is a gate sidewall, 26 is an n-type low concentration diffusion layer, 27 is an n-type high concentration diffusion layer, 28 Is a resist.
【０００４】この半導体装置において特徴的なことは、
非対称型ＬＤＤＭＯＳＦＥＴのドレイン側には低濃度拡
散層、高濃度拡散層の両方があるのに対して、ソース側
には高濃度拡散層だけしかないということである。これ
はＭＯＳＦＥＴの駆動力はソース側の寄生抵抗に非常に
影響を受け、ＭＯＳＦＥＴの信頼性はドレイン側の電界
集中度合で決定されるためである。A characteristic of this semiconductor device is that
This means that the drain side of the asymmetric LDDMOSFET has both a low concentration diffusion layer and a high concentration diffusion layer, whereas the source side has only a high concentration diffusion layer. This is because the driving force of the MOSFET is greatly affected by the parasitic resistance on the source side, and the reliability of the MOSFET is determined by the degree of electric field concentration on the drain side.
【０００５】さらにこの半導体装置の製造方法において
特徴的なことは、選択的酸化膜堆積技術により、非対称
型ＬＤＤＭＯＳＦＥＴのドレイン側だけにサイドウォー
ルを形成できるために、従来の技術に比較して、イオン
注入の回数の増加、高温度の熱拡散をすることなく既存
のプロセス技術で簡単に作製することができる。Further, a characteristic of this method of manufacturing a semiconductor device is that a side wall can be formed only on the drain side of an asymmetric LDD MOSFET by the selective oxide film deposition technique. It can be easily manufactured by the existing process technology without increasing the number of times of implantation and thermal diffusion at high temperature.
【０００６】またさらに微細化に伴い、ショートチャネ
ル効果及びそれを抑制するためのパンチスルーストッパ
の高濃度化による接合容量の増大が深刻な問題となって
いる。接合容量を大幅に抑えた状態で、しかも、ショー
トチャネル効果を改善したＭＯＳ型半導体装置として、
ポケットパンチスルーストッパ構造が提案されている。
例えばI.E.E.E.1991 I.E.D.M Technical Digest pp641-
644にA.Hori等によってSPI(Self-aligned Pocket Impla
ntation)MOSFETが提案されている。Further, with further miniaturization, there is a serious problem that the short channel effect and the increase of the junction capacitance due to the high concentration of the punch through stopper for suppressing the short channel effect. As a MOS type semiconductor device in which the short channel effect is improved while the junction capacitance is greatly suppressed,
A pocket punch through stopper structure has been proposed.
For example, IEEE1991 IEDM Technical Digest pp641-
In 644, SPI (Self-aligned Pocket Impla
ntation) MOSFET has been proposed.
【０００７】ＳＰＩ構造のＭＯＳ型半導体装置を図９
に、及びその製造方法を図１０に示す。同図において、
３１はｐ型半導体基板、３２はゲート酸化膜、３３はゲ
ート電極、３４はゲート側壁、３５はｎ型低濃度拡散
層、３６はｎ型高濃度拡散層、３７はシリサイド、３８
はポケットパンチスルーストッパーである。A MOS type semiconductor device having an SPI structure is shown in FIG.
10 and its manufacturing method are shown in FIG. In the figure,
31 is a p-type semiconductor substrate, 32 is a gate oxide film, 33 is a gate electrode, 34 is a gate sidewall, 35 is an n-type low-concentration diffusion layer, 36 is an n-type high-concentration diffusion layer, 37 is a silicide, 38
Is a pocket punch through stopper.
【０００８】この半導体装置において特徴的なことは、
シリサイドをマスクとしてパンチスルーストッパーを注
入するため、接合容量を大幅に抑えた状態でショートチ
ャネル効果が改善される。さらにゲート電極及びソー
ス、ドレイン部の寄生抵抗が減少する。A characteristic of this semiconductor device is that
Since the punch-through stopper is implanted using the silicide as a mask, the short channel effect is improved while the junction capacitance is greatly suppressed. Further, the parasitic resistance of the gate electrode and the source / drain portion is reduced.
【０００９】[0009]
【発明が解決しようとする課題】しかしながら、これら
の構造ではハーフミクロン領域以下のＭＯＳ型半導体装
置として充分ではない。というのも、第７図に示した構
造においては以下の重大な問題点がある。However, these structures are not sufficient as a MOS type semiconductor device in the half micron region or less. This is because the structure shown in FIG. 7 has the following serious problems.
【００１０】１）非対称型ＬＤＤＭＯＳＦＥＴのソース
側にゲート側壁がないためシリサイド工程が容易に導入
できず、拡散抵抗による駆動力の劣化が著しい。1) Since there is no gate side wall on the source side of the asymmetric LDD MOSFET, the silicide process cannot be easily introduced, and the driving force is significantly deteriorated due to the diffusion resistance.
【００１１】２）ショートチャネル効果を改善するため
にパンチスルーストッパを注入すると、接合容量が大幅
に増加する。2) Injecting a punch through stopper to improve the short channel effect significantly increases the junction capacitance.
【００１２】３）非対称型ＬＤＤＭＯＳＦＥＴのソース
側がシングルドレイン構造のため、ゲートソースオーバ
ラップ容量が大きくなる。3) Since the source side of the asymmetric LDD MOSFET has a single drain structure, the gate-source overlap capacitance becomes large.
【００１３】１）と２）の問題点を解決するために図８
（ｄ）の後で、サイドウォールを新たに形成し、シリサ
イド形成後、サイドウォールを除去しポケットパンチス
ルーストッパを注入する方法がある。しかしながらプロ
セスが非常に複雑になるうえに、選択的酸化膜堆積技術
により形成されたサイドウォールを除去する際にＬＯＣ
ＯＳもかなりエッチングされる可能性があり、この方法
は非常に実現性に乏しい。In order to solve the problems 1) and 2), FIG.
After (d), there is a method of newly forming a sidewall, forming a silicide, removing the sidewall, and implanting a pocket punch through stopper. However, the process is very complicated and LOC is required when removing the sidewalls formed by the selective oxide film deposition technique.
The OS can also be significantly etched, making this method very impractical.
【００１４】さらに図９に示した構造において、非対称
型ＬＤＤＭＯＳＦＥＴを実現しようとすると、図１０
（ａ）の低濃度拡散層形成後でドレイン側をマスクで覆
った状態でソース側に高濃度拡散層を形成する方法があ
る。しかしながらこの方法には以下の問題点がある。Further, if an asymmetric LDDMOSFET is to be realized in the structure shown in FIG.
There is a method of forming a high concentration diffusion layer on the source side with the drain side covered with a mask after forming the low concentration diffusion layer of (a). However, this method has the following problems.
【００１５】１）高濃度拡散層を形成するためのイオン
注入が１回から２回に増加する。 ２）ソース側の高濃度拡散層形成のためのイオン注入の
回数が２回になるため、接合深さが深くなるために、シ
ョートチャネル効果が劣化する。1) The number of ion implantations for forming the high concentration diffusion layer is increased from once to twice. 2) Since the number of times of ion implantation for forming the high-concentration diffusion layer on the source side is twice, the junction depth becomes deep and the short channel effect deteriorates.
【００１６】かかる点に鑑み、本発明では非対称型と対
称型のＭＯＳの混在するＶＬＳＩにおいてシリサイド工
程が容易に適用でき、また非対称型ＭＯＳＦＥＴにポケ
ットパンチスルーストッパーを注入する工程が容易に適
用可能な半導体装置及び半導体装置の製造方法、さらに
それに加えて駆動力を低下させることなく非対称型ＭＯ
ＳＦＥＴの寄生容量を低減させることが可能な半導体装
置及び半導体装置の製造方法を提供する。In view of the above point, in the present invention, the silicidation process can be easily applied to a VLSI in which asymmetrical and symmetrical MOSs are mixed, and the process of implanting a pocket punch through stopper into an asymmetrical MOSFET can be easily applied. Semiconductor device and method of manufacturing semiconductor device, and in addition to that, asymmetric MO without reducing driving force
Provided are a semiconductor device capable of reducing the parasitic capacitance of an SFET and a method for manufacturing the semiconductor device.
【００１７】[0017]
【課題を解決するための手段】本発明の請求項１記載の
ＭＯＳ型半導体装置は、第１導電型の半導体基板の一主
面に素子分離領域で分離された複数の島領域と、前記第
１導電型の半導体基板の一主面にゲート酸化膜を介して
設けられたゲート電極と、前記ゲート電極の側部に形成
されたＬ型の側壁を有し、ドレイン側に第２導電型の低
濃度拡散層と第２導電型の高濃度拡散層を有し、ソース
側にＬ型側壁下で浅い接合深さを有する第２導電型の高
濃度拡散層と前記第２導電型の高濃度拡散層を有し、前
記第２導電型の高濃度拡散層及び前記ゲート電極がシリ
サイド化されていることを特徴とする。According to a first aspect of the present invention, there is provided a MOS semiconductor device having a plurality of island regions separated by an element isolation region on one main surface of a semiconductor substrate of a first conductivity type. It has a gate electrode provided on one main surface of a semiconductor substrate of one conductivity type via a gate oxide film, and an L-type sidewall formed on a side portion of the gate electrode, and has a second conductivity type on the drain side. A second-conductivity-type high-concentration diffusion layer having a low-concentration diffusion layer and a second-conductivity-type high-concentration diffusion layer and having a shallow junction depth under the L-type sidewall on the source side, and the second-conductivity-type high concentration A diffusion layer is provided, and the high-concentration diffusion layer of the second conductivity type and the gate electrode are silicided.
【００１８】本発明の請求項２記載のＭＯＳ型半導体装
置は、第１導電型の半導体基板の一主面に素子分離領域
で分離された複数の島領域と、前記第１導電型の半導体
基板の一主面にゲート酸化膜を介して設けられたゲート
電極と、前記ゲート電極の側部に形成されたＬ型の側壁
を有し、選択的にある島領域においては、第２導電型の
低濃度拡散層と第２導電型の高濃度拡散層を有し、選択
的に他の島領域においては、ドレイン側に第２導電型の
低濃度拡散層と前記第２導電型の高濃度拡散層を有し、
ソース側にＬ型側壁下で浅い接合深さを有する第２導電
型の高濃度拡散層と前記第２導電型の高濃度拡散層を有
し、前記第２導電型の高濃度拡散層及び前記ゲート電極
がシリサイド化されていることを特徴とする。According to a second aspect of the present invention, in a MOS type semiconductor device, a plurality of island regions separated by element isolation regions on one main surface of a first conductivity type semiconductor substrate and the first conductivity type semiconductor substrate. Has a gate electrode provided on one main surface via a gate oxide film and an L-type sidewall formed on a side portion of the gate electrode, and selectively has an island region of the second conductivity type. A low-concentration diffusion layer and a second-conductivity-type high-concentration diffusion layer are provided, and in another island region, the second-conductivity-type low-concentration diffusion layer and the second-conductivity-type high-concentration diffusion are selectively provided on the drain side. Have layers,
A second conductive type high-concentration diffusion layer having a shallow junction depth below the L-type side wall and the second conductive type high-concentration diffusion layer on the source side; It is characterized in that the gate electrode is silicided.
【００１９】本発明の請求項３記載のＭＯＳ型半導体装
置は、請求項１に記載のＭＯＳ型半導体装置において、
Ｌ型側壁下で浅い接合深さを有する第２導電型の高濃度
拡散層上にゲート酸化膜中央部より厚いゲート酸化膜を
有することを特徴とする。A MOS type semiconductor device according to claim 3 of the present invention is the MOS type semiconductor device according to claim 1, wherein
It is characterized by having a gate oxide film thicker than the central portion of the gate oxide film on the second-conductivity-type high-concentration diffusion layer having a shallow junction depth under the L-type sidewall.
【００２０】本発明の請求項４記載のＭＯＳ型半導体装
置の製造方法は、第１導電型の半導体基板上の所定の位
置にゲート酸化膜とゲート電極を形成する工程と、前記
半導体基板および前記ゲート電極上に第１の絶縁膜と、
第２の絶縁膜とを堆積させる工程と、前記第１の絶縁膜
と前記第２の絶縁膜とを選択的にエッチングして、前記
ゲート電極のソースおよびドレイン側の両側面に前記第
１の絶縁膜からなるＬ型側壁と前記第２の絶縁膜からな
る側壁とを残置させる工程と、前記ソース側の前記第２
の絶縁膜を選択的にエッチングすることにより前記ソー
ス側の前記Ｌ型側壁を露出させる工程と、前記ゲート電
極をマスクとして前記半導体基板に、イオン注入によ
り、ドレイン側には第２導電型の高濃度拡散層を形成
し、ソース側には前記第２導電型の高濃度拡散層と前記
Ｌ型側壁下で浅い接合を有する第２導電型の高濃度拡散
層を形成する工程と、ドレイン側の前記第２の絶縁膜を
選択的にエッチングすることにより、前記ゲート電極側
面のドレイン側に前記第１の絶縁膜からなるＬ型側壁を
露出させる工程と、前記ゲート電極をマスクとして前記
半導体基板上に、イオン注入により、第２導電型の低濃
度拡散層を形成する工程と、前記第２導電型の高濃度拡
散層及び前記ゲート電極とをシリサイド化する工程を有
することを特徴とする。According to a fourth aspect of the present invention, there is provided a method of manufacturing a MOS semiconductor device, which comprises forming a gate oxide film and a gate electrode at predetermined positions on a first conductivity type semiconductor substrate, the semiconductor substrate and the semiconductor substrate. A first insulating film on the gate electrode,
Depositing a second insulating film; and selectively etching the first insulating film and the second insulating film to form the first electrode on both side surfaces of the gate electrode on the source and drain sides. Leaving the L-shaped side wall made of an insulating film and the side wall made of the second insulating film, and the second side of the source side.
Exposing the L-type side wall on the source side by selectively etching the insulating film of the second conductive film, and ion-implanting the semiconductor substrate with the gate electrode as a mask, thereby forming a high conductivity type of the second conductivity type on the drain side. Forming a concentration diffusion layer, forming a second conductivity type high concentration diffusion layer on the source side and a second conductivity type high concentration diffusion layer having a shallow junction under the L-type sidewall; Selectively etching the second insulating film to expose an L-shaped side wall made of the first insulating film on the drain side of the side surface of the gate electrode, and using the gate electrode as a mask on the semiconductor substrate And a step of forming a second-conductivity-type low-concentration diffusion layer by ion implantation, and a step of silicidizing the second-conductivity-type high-concentration diffusion layer and the gate electrode.
【００２１】本発明の請求項５記載のＭＯＳ型半導体装
置の製造方法は、請求項４に記載のＭＯＳ型半導体装置
の製造方法において、ゲート電極側面のソース側に第１
の絶縁膜からなるＬ型側壁を形成し、ゲート電極側面の
ドレイン側は前記第１の絶縁膜と第２の絶縁膜で覆われ
た状態で酸化工程を行なうことを特徴とする。According to a fifth aspect of the present invention, there is provided a method of manufacturing a MOS semiconductor device according to the fourth aspect, wherein the first side is provided on a side of the gate electrode on the source side.
The L-shaped side wall made of the insulating film is formed, and the oxidation step is performed while the drain side of the side surface of the gate electrode is covered with the first insulating film and the second insulating film.
【００２２】[0022]
【作用】本発明の請求項１に記載のＭＯＳ型半導体装置
は、ソースとドレインの構造が非対称であることが特徴
である。すなわちドレイン側をＬＤＤ構造にすることで
ドレイン近傍の水平電界を緩和しホットエレクトロン劣
化を抑制し、一方ソース側をシングルドレイン構造にす
ることでソース部の寄生抵抗を低減し駆動能力を向上さ
せている。The MOS type semiconductor device according to claim 1 of the present invention is characterized in that the source and drain structures are asymmetric. That is, by making the drain side an LDD structure, the horizontal electric field in the vicinity of the drain is relaxed and hot electron deterioration is suppressed, while by making the source side a single drain structure, the parasitic resistance of the source part is reduced and the driving capability is improved. There is.
【００２３】また従来の技術と比較して、ソース側のＬ
型側壁下で浅い接合深さを有する高濃度拡散層の接合深
さが高濃度拡散層の接合深さよりも浅く形成され、ソー
ス拡散層からのポテンシャルのチャネル方向への広がり
を効果的に抑え、ショートチャネル効果を抑制してい
る。Further, as compared with the conventional technique, L on the source side is
The junction depth of the high-concentration diffusion layer having a shallow junction depth under the side wall of the mold is formed to be shallower than the junction depth of the high-concentration diffusion layer, effectively suppressing the spread of the potential from the source diffusion layer in the channel direction. The short channel effect is suppressed.
【００２４】またこのソース領域は、従来技術における
深い接合深さを有する高濃度拡散層からなるシングルド
レイン構造に比して、ゲートドレインオーバラップ容量
を低減でき素子の高速化を可能にする。Further, this source region can reduce the gate-drain overlap capacitance and can speed up the device, as compared with the single drain structure composed of a high-concentration diffusion layer having a deep junction depth in the prior art.
【００２５】さらに従来の技術と比較して、ソース・ド
レイン及びゲート電極がシリサイド化されているため、
ソース・ドレイン部の拡散抵抗に起因する駆動力の劣
化、ゲート抵抗に起因するスイッチング時間の増大を改
善することができる。またシリサイドをマスクとしてＬ
型側壁部分からポケットパンチスルーストッパを注入で
きるためにソースドレイン部の接合容量が増加すること
なしに効果的にショートチャネル効果を抑制できる。Further, compared with the conventional technique, since the source / drain and gate electrodes are silicided,
It is possible to improve the deterioration of the driving force due to the diffusion resistance of the source / drain portions and the increase of the switching time due to the gate resistance. Also, using the silicide as a mask, L
Since the pocket punch through stopper can be injected from the mold side wall portion, the short channel effect can be effectively suppressed without increasing the junction capacitance of the source / drain portion.
【００２６】また、本発明の請求項２に記載のＭＯＳ型
半導体装置は、請求項１に記載のＭＯＳ型半導体装置の
他に、普通の対称型のＬＤＤＭＯＳＦＥＴが混在するこ
とが特徴である。ソースとドレインが固定されているよ
うなＭＯＳＦＥＴには非対称型のＭＯＳＦＥＴを用いる
ことで駆動力を向上させることができ、一方ソースとド
レインの向きが入れ替わるようなＭＯＳＦＥＴ（例えば
センスアンプ）には対称型のＭＯＳＦＥＴを用いること
で対応できる。The MOS semiconductor device according to a second aspect of the present invention is characterized in that, in addition to the MOS semiconductor device according to the first aspect, an ordinary symmetrical LDD MOSFET is mixed. The driving force can be improved by using an asymmetrical MOSFET for a MOSFET having a fixed source and drain, while a symmetrical type is used for a MOSFET (for example, a sense amplifier) in which the directions of the source and drain are switched. This can be dealt with by using the above MOSFET.
【００２７】また、本発明の請求項３に記載のＭＯＳ型
半導体装置は、請求項１に記載のＭＯＳ型半導体装置に
おいて、ソース側のＬ型側壁下で浅い接合を有する高濃
度拡散層上にゲート酸化膜中央部より厚いゲート酸化膜
を有することで、駆動力を殆ど低下させることなく、酸
化膜容量を減少させることで素子のスイッチイング時間
を改善させることができる。A MOS semiconductor device according to a third aspect of the present invention is the MOS semiconductor device according to the first aspect, wherein the high concentration diffusion layer having a shallow junction is formed under the source-side L-type sidewall. By having the gate oxide film thicker than the central portion of the gate oxide film, it is possible to improve the switching time of the device by reducing the oxide film capacitance without substantially reducing the driving force.
【００２８】また、本発明の請求項４に記載のＭＯＳ型
半導体装置の製造方法は、非対称型と対称型のＭＯＳの
混在するプロセスにシリサイド工程とシリサイドをマス
クとしてポケットパンチスルーストッパーを注入する工
程が容易に適用可能である。具体的には１）Ｌ型側壁の
一部がゲート電極上部とシリコン基板上にも残るように
形成し、サイドウォールに窒化膜を用いることで、ゲー
ト電極、ＬＯＣＯＳをエッチングすることなく、サイド
ウォールだけを選択的にエッチングできる工程が可能で
ある。２）シングルドレインのサイドウォール除去、ｎ
＋層形成、ＬＤＤのサイドウォール除去、ｎ−層形成の
工程により、効果的に非対称型と対称型のＭＯＳを製造
できる。３）最後に残ったＬ型側壁によりシリサイドが
容易に形成できる。According to a fourth aspect of the present invention, in a method of manufacturing a MOS type semiconductor device, a step of implanting a pocket punch through stopper using a silicide step and a silicide as a mask in a process in which asymmetrical and symmetrical MOSs are mixed. Is easily applicable. Specifically, 1) a sidewall is formed without leaving the gate electrode and LOCOS by forming a part of the L-shaped sidewall so as to remain on the gate electrode and the silicon substrate and using a nitride film for the sidewall. It is possible to have a process capable of selectively etching only the film. 2) Single drain sidewall removal, n
By the steps of + layer formation, sidewall removal of LDD, and n-layer formation, asymmetrical and symmetrical MOSs can be effectively manufactured. 3) A silicide can be easily formed by the L-type sidewall left at the end.
【００２９】また、本発明の請求項５に記載のＭＯＳ型
半導体装置の製造方法は、本発明の請求項４に記載のＭ
ＯＳ型半導体装置の製造方法において、酸化種を通し難
い第２の絶縁膜のサイドウォールのドレイン側を残し、
ソース側をエッチングした状態で、酸化工程を行なうこ
とにより、ドレイン側のゲート電極端部を酸化すること
なく、ソース側のゲート電極端部のゲート絶縁膜を厚く
形成することができる。A method of manufacturing a MOS type semiconductor device according to a fifth aspect of the present invention is the M method according to the fourth aspect of the present invention.
In the method of manufacturing an OS type semiconductor device, the drain side of the sidewall of the second insulating film, which is difficult to pass the oxidizing species, is left,
By performing the oxidation step with the source side etched, the gate insulating film at the source side gate electrode end can be formed thick without oxidizing the drain side gate electrode end.
【００３０】[0030]
【実施例】以下本発明のＭＯＳ型半導体装置およびその
製造方法について、図面を参照しながら説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS A MOS type semiconductor device and a method of manufacturing the same according to the present invention will be described below with reference to the drawings.
【００３１】（実施例１）図１は本発明の実施例におけ
るＭＯＳ型半導体装置の断面図である。図１において、
１はｐ型半導体基板、２はＬＯＣＯＳ分離、３はゲート
酸化膜、４はゲート電極、５はＬ型側壁、６はｎ型高濃
度拡散層、７はＬ型側壁下で浅い接合深さを有するｎ型
高濃度拡散層、８はｎ型低濃度拡散層、９はシリサイ
ド、１０はポケットパンチスルーストッパである。(Embodiment 1) FIG. 1 is a sectional view of a MOS type semiconductor device according to an embodiment of the present invention. In FIG.
1 is a p-type semiconductor substrate, 2 is a LOCOS isolation, 3 is a gate oxide film, 4 is a gate electrode, 5 is an L-type sidewall, 6 is an n-type high-concentration diffusion layer, and 7 is a shallow junction depth under the L-type sidewall. The n-type high-concentration diffusion layer is provided, 8 is an n-type low-concentration diffusion layer, 9 is a silicide, and 10 is a pocket punch through stopper.
【００３２】図１で特徴的なことは、ソースとドレイン
の構造が非対称であるということである。すなわちドレ
イン側をｎ型高濃度拡散層６とｎ型低濃度拡散層８で構
成されたＬＤＤ構造にすることでドレイン近傍の水平電
界を緩和しホットエレクトロン劣化を抑制し、一方ソー
ス側をｎ型高濃度拡散層６、Ｌ型側壁下で浅い接合深さ
を有するｎ型高濃度拡散層７のシングルドレイン構造に
することでソース部の寄生抵抗を低減し駆動能力を向上
させている。A characteristic of FIG. 1 is that the source and drain structures are asymmetric. That is, by making the drain side an LDD structure composed of the n-type high-concentration diffusion layer 6 and the n-type low-concentration diffusion layer 8, the horizontal electric field near the drain is relaxed and hot electron deterioration is suppressed, while the source side is n-type. The single-drain structure of the high-concentration diffusion layer 6 and the n-type high-concentration diffusion layer 7 having a shallow junction depth under the L-type side wall reduces the parasitic resistance of the source portion and improves the driving capability.
【００３３】また従来の技術と比較して、ソース側のＬ
型側壁下で浅い接合深さを有する高濃度拡散層７の接合
深さが高濃度拡散層６の接合深さよりも浅く形成され、
ソース拡散層からのポテンシャルのチャネル方向への広
がりを効果的に抑え、ショートチャネル効果を抑制して
いる。Compared with the conventional technique, L on the source side
The junction depth of the high-concentration diffusion layer 7 having a shallow junction depth under the side wall of the mold is formed to be shallower than the junction depth of the high-concentration diffusion layer 6.
Effectively suppressing the spread of the potential from the source diffusion layer in the channel direction, and suppressing the short channel effect.
【００３４】またこのソース領域は、従来技術における
深い接合深さを有する高濃度拡散層からなるシングルド
レイン構造に比して、ゲートドレインオーバラップ容量
を低減でき素子の高速化を可能にする。In addition, this source region can reduce the gate-drain overlap capacitance and can speed up the device, as compared with the single drain structure which is formed of a high-concentration diffusion layer having a deep junction depth in the prior art.
【００３５】さらに従来の技術と比較して、ソース・ド
レイン及びゲート電極４がシリサイド化されているた
め、ソース・ドレイン部の拡散抵抗に起因する駆動力の
劣化、ゲート抵抗に起因するスイッチング時間の増大を
改善することができる。またさらにシリサイドをマスク
としてＬ型側壁部分からポケットパンチスルーストッパ
１０を注入できるためにソースドレイン部の接合容量が
増加することなしに効果的にショートチャネル効果を抑
制できる。Further, as compared with the conventional technique, since the source / drain and the gate electrode 4 are silicided, the driving force is deteriorated due to the diffusion resistance of the source / drain portion, and the switching time due to the gate resistance is reduced. The increase can be improved. Furthermore, since the pocket punch through stopper 10 can be injected from the L-shaped side wall portion using the silicide as a mask, the short channel effect can be effectively suppressed without increasing the junction capacitance of the source / drain portion.
【００３６】（実施例２）図２は本発明の実施例におけ
るＭＯＳ型半導体装置の断面図である。図２において、
１はｐ型半導体基板、２はＬＯＣＯＳ分離、３はゲート
酸化膜、４はゲート電極、５はＬ型側壁、６はｎ型高濃
度拡散層、７はＬ型側壁下で浅い接合深さを有するｎ型
高濃度拡散層、８はｎ型低濃度拡散層、９はシリサイ
ド、１０はポケットパンチスルーストッパである。(Embodiment 2) FIG. 2 is a sectional view of a MOS type semiconductor device according to an embodiment of the present invention. In FIG.
1 is a p-type semiconductor substrate, 2 is a LOCOS isolation, 3 is a gate oxide film, 4 is a gate electrode, 5 is an L-type sidewall, 6 is an n-type high-concentration diffusion layer, and 7 is a shallow junction depth under the L-type sidewall. The n-type high-concentration diffusion layer is provided, 8 is an n-type low-concentration diffusion layer, 9 is a silicide, and 10 is a pocket punch through stopper.
【００３７】図２で特徴的なことは、図１のＭＯＳ型半
導体装置に、普通の対称型のＬＤＤＭＯＳＦＥＴが混在
することが特徴である。ソースとドレインが固定されて
いるようなＭＯＳＦＥＴには非対称型のＭＯＳＦＥＴを
用いることで駆動力を向上させることができ、一方ソー
スとドレインの向きが入れ替わるようなＭＯＳＦＥＴ
（例えばセンスアンプ）には対称型のＭＯＳＦＥＴを用
いることで対応できる。A characteristic feature of FIG. 2 is that ordinary symmetrical LDD MOSFETs are mixed in the MOS semiconductor device of FIG. A MOSFET having a fixed source and drain can improve driving force by using an asymmetrical MOSFET, while the source and drain are switched in direction.
This can be dealt with by using a symmetrical type MOSFET (for example, a sense amplifier).
【００３８】図５（ａ）、（ｂ）は各々プロセスシミュ
レータを用いて求められた対称型ＭＯＳと非対称型ＭＯ
Ｓのチャネル方向のプロファイル図である。このプロセ
スシミュレーションにおいては、ゲート長０．３ｕｍ、
ゲート酸化膜厚８ｎｍに設定し、ｎ型高濃度拡散層６、
７はヒ素イオンを注入エネルギー８０ＫｅＶ、注入ドー
ズ量６Ｅ１５ｃｍ−２程度イオン注入することで形成
し、ｎ型低濃度拡散層８はリンイオンを注入エネルギー
８０ＫｅＶ、注入ドーズ量４Ｅ１３ｃｍ−２程度で７度
の角度でイオン注入することで形成している。5 (a) and 5 (b) respectively show a symmetric MOS and an asymmetric MO obtained by using a process simulator.
It is a profile diagram of S in the channel direction. In this process simulation, the gate length is 0.3um,
The gate oxide film thickness is set to 8 nm, the n-type high concentration diffusion layer 6,
7 is formed by implanting arsenic ions with an implantation energy of 80 KeV and an implantation dose of about 6E15 cm −2, and the n-type low-concentration diffusion layer 8 is phosphorus ions with an implantation energy of 80 KeV and an implantation dose of about 4E13 cm −2 and an angle of 7 degrees. It is formed by ion implantation.
【００３９】図５（ａ）、（ｂ）より分かる通り、対称
型ＭＯＳと非対称型ＭＯＳの実行チャネル長はほぼ同じ
になっている。また図５（ｂ）より分かる通り、ソース
側のプロファイルの形状はリンに関係せず、ヒ素で決定
されており、さらにＬ型側壁５のためにその直下でのプ
ロファイルがゆるやかになっていることが分かる。また
デバイスシミュレータにより計算したしきい値電圧は対
称型ＭＯＳ、非対称型ＭＯＳともに約０．２Ｖで、ソー
ス側のＬ型側壁下で浅い接合深さを有する高濃度拡散層
７の接合深さが高濃度拡散層６の接合深さよりも浅く形
成され、ソース拡散層からのポテンシャルのチャネル方
向への広がりを効果的に抑え、ショートチャネル効果を
抑制していることが理解できる。As can be seen from FIGS. 5A and 5B, the symmetric MOS and the asymmetric MOS have substantially the same execution channel length. Further, as can be seen from FIG. 5 (b), the shape of the profile on the source side is not related to phosphorus and is determined by arsenic, and the profile immediately below is gentle due to the L-shaped side wall 5. I understand. The threshold voltage calculated by the device simulator is about 0.2 V for both the symmetrical MOS and the asymmetric MOS, and the high-concentration diffusion layer 7 having a shallow junction depth under the source-side L-type sidewall has a high junction depth. It can be understood that it is formed shallower than the junction depth of the concentration diffusion layer 6 to effectively suppress the spread of the potential from the source diffusion layer in the channel direction and suppress the short channel effect.
【００４０】図６にデバイスシミュレータにより求めら
れた対称型ＭＯＳと非対称型ＭＯＳの飽和電流値の違い
を示す。図６において横軸はドレイン電圧、縦軸はドレ
イン電流を示しており、このときのゲート電圧の値は３
Ｖである。図６より分かるように、非対称型ＭＯＳの飽
和電流値は対称型ＭＯＳの飽和電流値に比較して３４％
も増加している。これはソース側をｎ型高濃度拡散層
６、Ｌ型側壁下で浅い接合深さを有するｎ型高濃度拡散
層７のシングルドレイン構造にすることでソース部の寄
生抵抗を低減し駆動能力を向上させているためである。FIG. 6 shows the difference in saturation current value between the symmetrical MOS and the asymmetrical MOS obtained by the device simulator. In FIG. 6, the horizontal axis represents the drain voltage and the vertical axis represents the drain current, and the value of the gate voltage at this time is 3
V. As can be seen from FIG. 6, the saturation current value of the asymmetrical MOS is 34% compared to the saturation current value of the symmetrical MOS.
Is also increasing. This is because the source side has a single drain structure of the n-type high-concentration diffusion layer 6 and the n-type high-concentration diffusion layer 7 having a shallow junction depth under the L-type sidewall, thereby reducing the parasitic resistance of the source part and improving the driving capability. This is because it is improving.
【００４１】（実施例３）図３は本発明の実施例におけ
るＭＯＳ型半導体装置の断面図である。図３において、
１はｐ型半導体基板、２はＬＯＣＯＳ分離、３はゲート
酸化膜、４はゲート電極、５はＬ型側壁、６はｎ型高濃
度拡散層、７はＬ型側壁下で浅い接合深さを有するｎ型
高濃度拡散層、８はｎ型低濃度拡散層、９はシリサイ
ド、１０はポケットパンチスルーストッパである。(Embodiment 3) FIG. 3 is a sectional view of a MOS semiconductor device according to an embodiment of the present invention. In FIG.
1 is a p-type semiconductor substrate, 2 is a LOCOS isolation, 3 is a gate oxide film, 4 is a gate electrode, 5 is an L-type sidewall, 6 is an n-type high-concentration diffusion layer, and 7 is a shallow junction depth under the L-type sidewall. The n-type high-concentration diffusion layer is provided, 8 is an n-type low-concentration diffusion layer, 9 is a silicide, and 10 is a pocket punch through stopper.
【００４２】図３で特徴的なことは、図１のＭＯＳ型半
導体装置において、ソース側のＬ型側壁下で浅い接合深
さを有するｎ型高濃度拡散層７上にゲート酸化膜３中央
部より厚いゲート酸化膜３を有することで、駆動力を殆
ど低下させることなく、酸化膜容量を減少させることで
素子のスイッチイング時間を改善させることができるこ
とである。3 is characterized in that in the MOS type semiconductor device of FIG. 1, the gate oxide film 3 has a central portion on the n-type high concentration diffusion layer 7 having a shallow junction depth under the source-side L-type sidewall. By having a thicker gate oxide film 3, it is possible to improve the switching time of the device by reducing the oxide film capacitance without substantially reducing the driving force.
【００４３】（実施例４）図４は本発明の実施例におけ
るＭＯＳ型半導体装置の製造方法の工程断面図である。(Embodiment 4) FIGS. 4A to 4D are process sectional views of a method of manufacturing a MOS semiconductor device according to an embodiment of the present invention.
【００４４】工程（ａ）において、ｐ型半導体基板１上
にゲート酸化膜３を膜厚８ｎｍ程度に形成し、ゲート電
極４となる導電性膜を堆積し、ゲート酸化膜３とゲート
電極４となる導電性膜からなる多層膜の所定の位置を選
択的に垂直方向に強い異方性ドライエッチングによりゲ
ート酸化膜３が露出するまでエッチングを行い、ゲート
電極４を形成する。In step (a), the gate oxide film 3 is formed on the p-type semiconductor substrate 1 to a film thickness of about 8 nm, a conductive film to be the gate electrode 4 is deposited, and the gate oxide film 3 and the gate electrode 4 are formed. A predetermined position of the multilayer film made of the conductive film is selectively etched in the vertical direction by strong anisotropic dry etching until the gate oxide film 3 is exposed to form a gate electrode 4.
【００４５】工程（ｂ）において、ｐ型半導体基板１お
よびゲート電極４上に約２５ｎｍの第１の絶縁膜５、例
えば酸化膜を形成し、さらに酸素を透過させない第２の
絶縁膜１０、例えば、窒化膜を約１５０ｎｍ堆積させ
る。In step (b), a first insulating film 5 having a thickness of about 25 nm, such as an oxide film, is formed on the p-type semiconductor substrate 1 and the gate electrode 4, and a second insulating film 10 that does not allow oxygen to pass, for example, an oxide film. , A nitride film is deposited to a thickness of about 150 nm.
【００４６】工程（ｃ）において、選択的に垂直方向に
強い異方性ドライエッチングにより、ｐ型半導体基板１
上とゲート電極４上部が約１５ｎｍ程度第１の絶縁膜５
で覆われた状態で、第１の絶縁膜５および第２の絶縁膜
１０をゲート電極４の側面に残置させる。In step (c), the p-type semiconductor substrate 1 is selectively etched by strong anisotropic dry etching in the vertical direction.
The upper part and the upper part of the gate electrode 4 are about 15 nm thick.
The first insulating film 5 and the second insulating film 10 are left on the side surfaces of the gate electrode 4 in a state of being covered with.
【００４７】工程（ｄ）において、第１の絶縁膜５と第
２の絶縁膜１０上に第３の絶縁膜１１、例えば酸化膜を
約５ｎｍ堆積し、さらにフォトレジスト１２を塗布す
る。In step (d), a third insulating film 11, for example, an oxide film is deposited to a thickness of about 5 nm on the first insulating film 5 and the second insulating film 10, and a photoresist 12 is applied.
【００４８】工程（ｅ）において、ゲート電極４の一部
とドレインを覆った状態にフォトレジスト１２を選択的
にパターニングし、フォトレジスト１２をマスクとし
て、フォトレジスト１２に覆われてない部分の第３の絶
縁膜１１を選択的にフッ酸でウエットエッチングする。In step (e), the photoresist 12 is selectively patterned so as to cover a part of the gate electrode 4 and the drain, and the photoresist 12 is used as a mask to expose a portion of the portion not covered with the photoresist 12. The insulating film 11 of No. 3 is selectively wet-etched with hydrofluoric acid.
【００４９】工程（ｆ）において、フォトレジスト１２
を除去し、第３の絶縁膜１１をマスクにして、ソース側
の第２の絶縁膜１０を選択的に熱リン酸溶液によりエッ
チングすることによりゲート電極４側面のソース側に第
１の絶縁膜５からなるＬ型側壁５を形成する。この際第
３の絶縁膜１１に覆われていない部分の第１の絶縁膜５
が約５ｎｍ程度エッチングされる（熱リン酸溶液の窒化
膜と酸化膜の選択比は３０なので、窒化膜を１５０ｎｍ
エッチングする際、酸化膜も約５ｎｍ程度エッチングさ
れる）。In step (f), the photoresist 12
Is removed, and the second insulating film 10 on the source side is selectively etched with a hot phosphoric acid solution using the third insulating film 11 as a mask to form the first insulating film on the source side on the side surface of the gate electrode 4. An L-shaped side wall 5 of 5 is formed. At this time, the portion of the first insulating film 5 not covered with the third insulating film 11
Is etched by about 5 nm. (Since the selection ratio between the nitride film and the oxide film of hot phosphoric acid solution is 30,
When etching, the oxide film is also etched by about 5 nm).
【００５０】工程（ｇ）において、ゲート電極４をマス
クとしてｎ型の不純物、例えば、ヒ素イオンを注入エネ
ルギー８０ＫｅＶ、注入ドーズ量６Ｅ１５ｃｍ−２程度
イオン注入し、ｎ型高濃度拡散層６、Ｌ型側壁下で浅い
接合深さを有するｎ型高濃度拡散層７を形成する。この
時ソース側はＬ型側壁５をマスクとしてＬ型側壁下で浅
い接合深さを有するｎ型高濃度拡散層７を形成するの
で、ソース側のＬ型側壁下で浅い接合深さを有する高濃
度拡散層７の接合深さが高濃度拡散層６の接合深さより
も浅く形成される。さらに第３の絶縁膜１１をエッチン
グする。この際第３の絶縁膜１１に覆われていない部分
の第１の絶縁膜５が約５ｎｍ程度エッチングされる。In the step (g), an n-type impurity such as arsenic ion is ion-implanted with an implantation energy of 80 KeV and an implantation dose amount of 6E15 cm −2 using the gate electrode 4 as a mask to form the n-type high-concentration diffusion layer 6 and L-type diffusion layer 6. An n-type high concentration diffusion layer 7 having a shallow junction depth is formed under the side wall. At this time, since the n-type high-concentration diffusion layer 7 having a shallow junction depth is formed under the L-type sidewall on the source side using the L-type sidewall 5 as a mask, a high junction depth is formed under the L-side sidewall on the source side. The junction depth of the concentration diffusion layer 7 is formed shallower than the junction depth of the high concentration diffusion layer 6. Further, the third insulating film 11 is etched. At this time, the portion of the first insulating film 5 which is not covered with the third insulating film 11 is etched by about 5 nm.
【００５１】工程（ｈ）において、ドレイン側の第２の
絶縁膜１０を選択的に熱リン酸溶液によりエッチングす
ることにより、ゲート電極４側面のドレイン側に第１の
絶縁膜５からなるＬ型側壁５を形成する。この際第１の
絶縁膜５が約５ｎｍ程度エッチングされる。さらにｎ型
の不純物、例えば、リンイオンを注入エネルギー８０Ｋ
ｅＶ、注入ドーズ量４Ｅ１３ｃｍ−２程度で７度の角度
でイオン注入しｎ型低濃度拡散層８を形成する。In the step (h), the second insulating film 10 on the drain side is selectively etched with a hot phosphoric acid solution to form an L-type structure made of the first insulating film 5 on the drain side on the side surface of the gate electrode 4. The side wall 5 is formed. At this time, the first insulating film 5 is etched by about 5 nm. Further, n-type impurities such as phosphorus ions are implanted at an energy of 80K.
The n-type low-concentration diffusion layer 8 is formed by ion implantation with an eV and an implantation dose amount of about 4E13 cm −2 at an angle of 7 degrees.
【００５２】工程（ｉ）において、Ｌ型側壁５を残した
状態で、Ｌ型側壁５以外の第１の絶縁膜５をエッチング
する。最終的にはソース側のＬ型側壁は約５ｎｍ程度、
ドレイン側のＬ型側壁は約１５ｎｍ程度になる。In step (i), the first insulating film 5 other than the L-shaped side wall 5 is etched with the L-shaped side wall 5 left. Finally, the L-side sidewall on the source side is about 5 nm,
The L-type side wall on the drain side is about 15 nm.
【００５３】工程（ｊ）において、ｎ型高濃度拡散層６
及びゲート電極４をシリサイド化する。In step (j), the n-type high concentration diffusion layer 6
And the gate electrode 4 is silicidized.
【００５４】以上のように構成された実施例４の半導体
製造方法では、現在のＬＳＩ技術では容易に実現できし
かも、自己整合性良く多くの工程を必要とせずＭＯＳ電
界効果トランジスタを実現できる。The semiconductor manufacturing method according to the fourth embodiment having the above-described structure can be easily realized by the current LSI technology, and a MOS field effect transistor can be realized with good self-alignment without requiring many steps.
【００５５】[0055]
【発明の効果】以上のように、本発明の請求項１に記載
のＭＯＳ型半導体装置は、ソースとドレインの構造が非
対称であることが特徴である。すなわちドレイン側をＬ
ＤＤ構造にすることでドレイン近傍の水平電界を緩和し
ホットエレクトロン劣化を抑制し、一方ソース側をシン
グルドレイン構造にすることでソース部の寄生抵抗を低
減し駆動能力を向上させている。As described above, the MOS semiconductor device according to the first aspect of the present invention is characterized in that the source and drain structures are asymmetric. That is, the drain side is L
The DD structure relaxes the horizontal electric field near the drain to suppress hot electron deterioration, while the single drain structure on the source side reduces the parasitic resistance of the source portion and improves the driving capability.
【００５６】また従来の技術と比較して、ソース側のＬ
型側壁下で浅い接合深さを有する高濃度拡散層の接合深
さが高濃度拡散層の接合深さよりも浅く形成され、ソー
ス拡散層からのポテンシャルのチャネル方向への広がり
を効果的に抑え、ショートチャネル効果を抑制してい
る。Compared with the conventional technique, L on the source side
The junction depth of the high-concentration diffusion layer having a shallow junction depth under the side wall of the mold is formed to be shallower than the junction depth of the high-concentration diffusion layer, effectively suppressing the spread of the potential from the source diffusion layer in the channel direction. The short channel effect is suppressed.
【００５７】またこのソース領域は、従来技術における
深い接合深さを有する高濃度拡散層からなるシングルド
レイン構造に比して、ゲートドレインオーバラップ容量
を低減でき素子の高速化を可能にする。Further, this source region can reduce the gate-drain overlap capacitance and enable the speeding up of the device, as compared with the conventional single-drain structure consisting of a high-concentration diffusion layer having a deep junction depth.
【００５８】さらに従来の技術と比較して、ソース・ド
レイン及びゲート電極がシリサイド化されているため、
ソース・ドレイン部の拡散抵抗に起因する駆動力の劣
化、ゲート抵抗に起因するスイッチング時間の増大を改
善することができる。またシリサイドをマスクとしてＬ
型側壁部分からポケットパンチスルーストッパを注入で
きるためにソースドレイン部の接合容量が増加すること
なしに効果的にショートチャネル効果を抑制できる。Further, compared with the conventional technique, since the source / drain and gate electrodes are silicided,
It is possible to improve the deterioration of the driving force due to the diffusion resistance of the source / drain portions and the increase of the switching time due to the gate resistance. Also, using the silicide as a mask, L
Since the pocket punch through stopper can be injected from the mold side wall portion, the short channel effect can be effectively suppressed without increasing the junction capacitance of the source / drain portion.
【００５９】また、本発明の請求項２に記載のＭＯＳ型
半導体装置は、請求項１に記載のＭＯＳ型半導体装置の
他に、普通の対称型のＬＤＤＭＯＳＦＥＴが混在するこ
とが特徴である。ソースとドレインが固定されているよ
うなＭＯＳＦＥＴには非対称型のＭＯＳＦＥＴを用いる
ことで駆動力を向上させることができ、一方ソースとド
レインの向きが入れ替わるようなＭＯＳＦＥＴ（例えば
センスアンプ）には対称型のＭＯＳＦＥＴを用いること
で対応できる。The MOS semiconductor device according to claim 2 of the present invention is characterized in that, in addition to the MOS semiconductor device according to claim 1, ordinary symmetrical LDD MOSFETs are mixed. The driving force can be improved by using an asymmetrical MOSFET for a MOSFET having a fixed source and drain, while a symmetrical type is used for a MOSFET (for example, a sense amplifier) in which the directions of the source and drain are switched. This can be dealt with by using the above MOSFET.
【００６０】また、本発明の請求項３に記載のＭＯＳ型
半導体装置は、請求項１に記載のＭＯＳ型半導体装置に
おいて、ソース側のＬ型側壁下で浅い接合を有する高濃
度拡散層上にゲート酸化膜中央部より厚いゲート酸化膜
を有することで、駆動力を殆ど低下させることなく、酸
化膜容量を減少させることで素子のスイッチイング時間
を改善させることができる。Further, a MOS type semiconductor device according to a third aspect of the present invention is the MOS type semiconductor device according to the first aspect, wherein the high concentration diffusion layer having a shallow junction is formed under the source-side L-type sidewall. By having the gate oxide film thicker than the central portion of the gate oxide film, it is possible to improve the switching time of the device by reducing the oxide film capacitance without substantially reducing the driving force.
【００６１】また、本発明の請求項４に記載のＭＯＳ型
半導体装置の製造方法は、非対称型と対称型のＭＯＳの
混在するプロセスにシリサイド工程とシリサイドをマス
クとしてポケットパンチスルーストッパーを注入する工
程が容易に適用可能である。具体的には１）Ｌ型側壁の
一部がゲート電極上部とシリコン基板上にも残るように
形成し、サイドウォールに窒化膜を用いることで、ゲー
ト電極、ＬＯＣＯＳをエッチングすることなく、サイド
ウォールだけを選択的にエッチングできる工程が可能で
ある。２）シングルドレインのサイドウォール除去、ｎ
＋層形成、ＬＤＤのサイドウォール除去、ｎ−層形成の
工程により、効果的に非対称型と対称型のＭＯＳを製造
できる。３）最後に残ったＬ型側壁によりシリサイドが
容易に形成できる。According to a fourth aspect of the present invention, in a method of manufacturing a MOS type semiconductor device, a step of implanting a pocket punch through stopper using a silicide step and a silicide as a mask in a process in which asymmetrical and symmetrical MOSs are mixed. Is easily applicable. Specifically, 1) a sidewall is formed without leaving the gate electrode and LOCOS by forming a part of the L-shaped sidewall so as to remain on the gate electrode and the silicon substrate and using a nitride film for the sidewall. It is possible to have a process capable of selectively etching only the film. 2) Single drain sidewall removal, n
By the steps of + layer formation, sidewall removal of LDD, and n-layer formation, asymmetrical and symmetrical MOSs can be effectively manufactured. 3) A silicide can be easily formed by the L-type sidewall left at the end.
【００６２】また、本発明の請求項５に記載のＭＯＳ型
半導体装置の製造方法は、本発明の請求項４に記載のＭ
ＯＳ型半導体装置の製造方法において、酸化種を通し難
い第２の絶縁膜のサイドウォールのドレイン側を残し、
ソース側をエッチングした状態で、酸化工程を行なうこ
とにより、ドレイン側のゲート電極端部を酸化すること
なく、ソース側のゲート電極端部のゲート絶縁膜を厚く
形成することができる。A method of manufacturing a MOS type semiconductor device according to a fifth aspect of the present invention is the same as the M method according to the fourth aspect of the present invention.
In the method of manufacturing an OS type semiconductor device, the drain side of the sidewall of the second insulating film, which is difficult to pass the oxidizing species, is left,
By performing the oxidation step with the source side etched, the gate insulating film at the source side gate electrode end can be formed thick without oxidizing the drain side gate electrode end.
【００６３】従って、本発明のＭＯＳ型半導体装置は、
ハーフミクロン領域以下のＶＬＳＩ技術に要求される短
チャネル効果を抑制しホットキャリア劣化耐性が高い高
信頼性で高速、低消費電力なＭＯＳ型半導体装置であ
る。さらに、本発明のＭＯＳ型半導体装置の製造方法
は、前記ＭＯＳ型半導体装置を容易に得る製造方法であ
り、その工業的価値はきわめて高い。Therefore, the MOS type semiconductor device of the present invention is
It is a highly reliable, high-speed, low-power-consumption MOS semiconductor device that suppresses the short channel effect required for VLSI technology in the half micron region or less and has high resistance to hot carrier deterioration. Furthermore, the method for manufacturing a MOS semiconductor device of the present invention is a method for easily obtaining the MOS semiconductor device, and its industrial value is extremely high.
【図１】本発明の第１の実施例におけるＭＯＳ型半導体
装置の断面図FIG. 1 is a sectional view of a MOS semiconductor device according to a first embodiment of the present invention.
【図２】本発明の第２の実施例におけるＭＯＳ型半導体
装置の断面図FIG. 2 is a sectional view of a MOS semiconductor device according to a second embodiment of the present invention.
【図３】本発明の第３の実施例におけるＭＯＳ型半導体
装置の断面図FIG. 3 is a sectional view of a MOS semiconductor device according to a third embodiment of the present invention.
【図４】本発明の第４の実施例におけるＭＯＳ型半導体
装置の製造方法の工程断面図FIG. 4 is a process sectional view of a method of manufacturing a MOS semiconductor device according to a fourth embodiment of the present invention.
【図５】本発明の第２の実施例におけるＭＯＳ型半導体
装置のチャネル方向のプロファイル分布図FIG. 5 is a profile distribution diagram in the channel direction of the MOS semiconductor device according to the second embodiment of the present invention.
【図６】本発明の第２の実施例におけるＭＯＳ型半導体
装置の対称型ＭＯＳと非対称型ＭＯＳの飽和電流値の違
いを示す図FIG. 6 is a diagram showing a difference in saturation current value between a symmetrical MOS and an asymmetrical MOS of a MOS semiconductor device according to a second embodiment of the present invention.
【図７】従来例１のＭＯＳ型半導体装置の断面図FIG. 7 is a cross-sectional view of a MOS semiconductor device of Conventional Example 1.
【図８】従来例１のＭＯＳ型半導体装置の製造方法の工
程断面図FIG. 8 is a process sectional view of a method for manufacturing a MOS semiconductor device of Conventional Example 1.
【図９】従来例２のＭＯＳ型半導体装置の断面図FIG. 9 is a cross-sectional view of a MOS semiconductor device of Conventional Example 2.
【図１０】従来例２のＭＯＳ型半導体装置の製造方法の
工程断面図FIG. 10 is a process sectional view of a method for manufacturing a MOS semiconductor device of Conventional Example 2.
１ ｐ型半導体基板 ２ ＬＯＣＯＳ分離 ３ ゲート酸化膜 ４ ゲート電極 ５ Ｌ型側壁 ６ ｎ型高濃度拡散層 ７ Ｌ型側壁下で浅い接合深さを有するｎ型高濃度拡散
層 ８ ｎ型低濃度拡散層 ９ シリサイド １０ ポケットパンチスルーストッパ １１ 第２の絶縁膜 １２ 第３の絶縁膜 １３ フォトレジスト ２１ ｐ型半導体基板 ２２ ＬＯＣＯＳ ２３ ゲート酸化膜 ２４ ゲート電極 ２５ ゲート側壁 ２６ ｎ型低濃度拡散層 ２７ ｎ型高濃度拡散層 ２８ レジスト ３１ ｐ型半導体基板 ３２ ゲート酸化膜 ３３ ゲート電極 ３４ ゲート側壁 ３５ ｎ型低濃度拡散層 ３６ ｎ型高濃度拡散層 ３７ シリサイド ３８ ポケットパンチスルーストッパ1 p-type semiconductor substrate 2 LOCOS isolation 3 gate oxide film 4 gate electrode 5 L-type sidewall 6 n-type high-concentration diffusion layer 7 n-type high-concentration diffusion layer having a shallow junction depth under the L-type sidewall 8 n-type low-concentration diffusion Layer 9 Silicide 10 Pocket punch through stopper 11 Second insulating film 12 Third insulating film 13 Photoresist 21 p-type semiconductor substrate 22 LOCOS 23 Gate oxide film 24 Gate electrode 25 Gate sidewall 26 n-type low-concentration diffusion layer 27 n-type High-concentration diffusion layer 28 Resist 31 p-type semiconductor substrate 32 gate oxide film 33 gate electrode 34 gate sidewall 35 n-type low-concentration diffusion layer 36 n-type high-concentration diffusion layer 37 silicide 38 pocket punch through stopper
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 21/28 ３０１ Ｓ 7376−4Ｍ 21/316 8617−4Ｍ Ｈ０１Ｌ 21/265 Ｌ 9274−4Ｍ 21/94 Ａ 9054−4Ｍ 29/78 ３０１ Ｐ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification number Office reference number FI technical display location H01L 21/28 301 S 7376-4M 21/316 8617-4M H01L 21/265 L 9274-4M 21 / 94 A 9054-4M 29/78 301 P
Claims (5)
離領域で分離された複数の島領域と、前記第１導電型の
半導体基板の一主面にゲート酸化膜を介して設けられた
ゲート電極と、前記ゲート電極の側部に形成されたＬ型
の側壁を有し、ドレイン側に第２導電型の低濃度拡散層
と第２導電型の高濃度拡散層を有し、ソース側にＬ型側
壁下で浅い接合深さを有する第２導電型の高濃度拡散層
と前記第２導電型の高濃度拡散層を有し、前記第２導電
型の高濃度拡散層及び前記ゲート電極がシリサイド化さ
れていることを特徴とするＭＯＳ型半導体装置。1. A plurality of island regions separated by an element isolation region on one main surface of a first conductivity type semiconductor substrate, and a gate oxide film provided on one main surface of the first conductivity type semiconductor substrate. A low-concentration diffusion layer of the second conductivity type and a high-concentration diffusion layer of the second conductivity type on the drain side, A second conductive type high-concentration diffusion layer having a shallow junction depth below the L-type side wall and the second conductive type high-concentration diffusion layer on the source side; A MOS type semiconductor device characterized in that a gate electrode is silicided.
離領域で分離された複数の島領域と、前記第１導電型の
半導体基板の一主面にゲート酸化膜を介して設けられた
ゲート電極と、前記ゲート電極の側部に形成されたＬ型
の側壁を有し、選択的にある島領域においては、第２導
電型の低濃度拡散層と第２導電型の高濃度拡散層を有
し、選択的に他の島領域においては、ドレイン側に第２
導電型の低濃度拡散層と第２導電型の高濃度拡散層を有
し、ソース側にＬ型側壁下で浅い接合深さを有する第２
導電型の高濃度拡散層と前記第２導電型の高濃度拡散層
を有し、前記第２導電型の高濃度拡散層及び前記ゲート
電極がシリサイド化されていることを特徴とするＭＯＳ
型半導体装置。2. A plurality of island regions separated by element isolation regions on one main surface of a first conductivity type semiconductor substrate and a gate oxide film on one main surface of the first conductivity type semiconductor substrate. A low-concentration diffusion layer of the second conductivity type and a high-concentration second conductivity type in an island region selectively having an L-type sidewall formed on a side portion of the gate electrode. It has a diffusion layer and selectively has a second side on the drain side in another island region.
A second conductive type low-concentration diffusion layer and a second conductive type high-concentration diffusion layer, which has a shallow junction depth under the L-type sidewall on the source side.
A MOS having a conductive type high-concentration diffusion layer and the second conductive type high-concentration diffusion layer, wherein the second conductive type high-concentration diffusion layer and the gate electrode are silicided.
Type semiconductor device.
電型の高濃度拡散層上にゲート酸化膜中央部より厚いゲ
ート酸化膜を有することを特徴とする請求項１に記載の
ＭＯＳ型半導体装置。3. The method according to claim 1, further comprising a gate oxide film thicker than a central portion of the gate oxide film on the second-conductivity-type high-concentration diffusion layer having a shallow junction depth under the L-type sidewall. MOS semiconductor device.
ゲート酸化膜とゲート電極を形成する工程と、 前記半導体基板および前記ゲート電極上に第１の絶縁膜
と、第２の絶縁膜とを堆積させる工程と、 前記第１の絶縁膜と前記第２の絶縁膜とを選択的にエッ
チングして、前記ゲート電極のソースおよびドレイン側
の両側面に前記第１の絶縁膜からなるＬ型側壁と前記第
２の絶縁膜からなる側壁とを残置させる工程と、 前記ソース側の前記第２の絶縁膜を選択的にエッチング
することにより前記ソース側の前記Ｌ型側壁を露出させ
る工程と、 前記ゲート電極をマスクとして前記半導体基板に、イオ
ン注入により、ドレイン側には第２導電型の高濃度拡散
層を形成し、ソース側には前記第２導電型の高濃度拡散
層と前記Ｌ型側壁下で浅い接合を有する第２導電型の高
濃度拡散層を形成する工程と、 ドレイン側の前記第２の絶縁膜を選択的にエッチングす
ることにより、前記ゲート電極側面のドレイン側に前記
第１の絶縁膜からなるＬ型側壁を露出させる工程と、 前記ゲート電極をマスクとして前記半導体基板上に、イ
オン注入により、第２導電型の低濃度拡散層を形成する
工程と、 前記第２導電型の高濃度拡散層及び前記ゲート電極とを
シリサイド化する工程を有することを特徴とするＭＯＳ
型半導体装置の製造方法。4. A step of forming a gate oxide film and a gate electrode at predetermined positions on a first conductivity type semiconductor substrate, a first insulating film on the semiconductor substrate and the gate electrode, and a second insulating film. A step of depositing a film, and selectively etching the first insulating film and the second insulating film to form the first insulating film on both source and drain side surfaces of the gate electrode. Leaving the L-type sidewall and the sidewall made of the second insulating film, and exposing the L-side sidewall on the source side by selectively etching the second insulating film on the source side. A second conductive type high-concentration diffusion layer is formed on the drain side and the second conductive type high-concentration diffusion layer is formed on the source side by ion implantation into the semiconductor substrate using the gate electrode as a mask. Make a shallow junction under the L-shaped sidewall Forming a second-conductivity-type high-concentration diffusion layer, and forming the first insulating film on the drain side of the side surface of the gate electrode by selectively etching the second insulating film on the drain side Exposing the L-type sidewall, forming a second conductivity type low-concentration diffusion layer by ion implantation on the semiconductor substrate using the gate electrode as a mask, and the second conductivity-type high-concentration diffusion layer And a MOS including a step of silicidizing the gate electrode
Type semiconductor device manufacturing method.
からなるＬ型側壁を露出させ、ゲート電極側面のドレイ
ン側は前記第１の絶縁膜と第２の絶縁膜で覆われた状態
で酸化し、前記ソース側のゲート酸化膜を厚くすること
を特徴とする請求項４に記載のＭＯＳ型半導体装置の製
造方法。5. A state in which an L-shaped side wall made of a first insulating film is exposed on the source side of the side surface of the gate electrode, and the drain side of the side surface of the gate electrode is covered with the first insulating film and the second insulating film. 5. The method for manufacturing a MOS type semiconductor device according to claim 4, wherein the gate oxide film on the source side is thickened by oxidizing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5114459A JPH06326122A (en) | 1993-05-17 | 1993-05-17 | Mos semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5114459A JPH06326122A (en) | 1993-05-17 | 1993-05-17 | Mos semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06326122A true JPH06326122A (en) | 1994-11-25 |
Family
ID=14638271
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5114459A Pending JPH06326122A (en) | 1993-05-17 | 1993-05-17 | Mos semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06326122A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6040629A (en) * | 1997-02-05 | 2000-03-21 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit having silicided elements of short length |
| US6239471B1 (en) | 1996-12-10 | 2001-05-29 | Mitsubishi Denki Kabushiki Kaisha | MIS transistor and manufacturing method thereof |
| US6359321B2 (en) | 1997-02-04 | 2002-03-19 | Mitsubishi Denki Kabushiki Kaisha | MIS transistor and method of fabricating the same |
| KR100396895B1 (en) * | 2001-08-02 | 2003-09-02 | 삼성전자주식회사 | Method of fabricating semiconductor device having L-type spacer |
| EP1406295A2 (en) * | 2002-10-01 | 2004-04-07 | Chartered Semiconductor Manufacturing Pte Ltd. | A method of forming a CMOS device |
| JP2008199027A (en) * | 2007-02-13 | 2008-08-28 | Qimonda Ag | Integrated circuit having three-dimensional channel field-effect transistor and method of manufacturing the same |
| WO2009001252A1 (en) * | 2007-06-27 | 2008-12-31 | Nxp B.V. | An extended drain transistor and a method of manufacturing the same |
| JP2012253371A (en) * | 2005-10-07 | 2012-12-20 | Internatl Business Mach Corp <Ibm> | Method of forming asymmetric spacer structures for semiconductor device |
| CN116230755A (en) * | 2023-05-05 | 2023-06-06 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and manufacturing method thereof |
-
1993
- 1993-05-17 JP JP5114459A patent/JPH06326122A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6239471B1 (en) | 1996-12-10 | 2001-05-29 | Mitsubishi Denki Kabushiki Kaisha | MIS transistor and manufacturing method thereof |
| US6359321B2 (en) | 1997-02-04 | 2002-03-19 | Mitsubishi Denki Kabushiki Kaisha | MIS transistor and method of fabricating the same |
| US6107156A (en) * | 1997-02-05 | 2000-08-22 | Mitsubishi Denki Kabushiki Kaisha | Silicide layer forming method and semiconductor integrated circuit |
| US6040629A (en) * | 1997-02-05 | 2000-03-21 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit having silicided elements of short length |
| KR100396895B1 (en) * | 2001-08-02 | 2003-09-02 | 삼성전자주식회사 | Method of fabricating semiconductor device having L-type spacer |
| EP1406295A2 (en) * | 2002-10-01 | 2004-04-07 | Chartered Semiconductor Manufacturing Pte Ltd. | A method of forming a CMOS device |
| EP1406295A3 (en) * | 2002-10-01 | 2008-09-10 | Chartered Semiconductor Manufacturing Pte Ltd. | A method of forming a CMOS device |
| JP2012253371A (en) * | 2005-10-07 | 2012-12-20 | Internatl Business Mach Corp <Ibm> | Method of forming asymmetric spacer structures for semiconductor device |
| JP2008199027A (en) * | 2007-02-13 | 2008-08-28 | Qimonda Ag | Integrated circuit having three-dimensional channel field-effect transistor and method of manufacturing the same |
| US8216908B2 (en) | 2007-06-27 | 2012-07-10 | Nxp B.V. | Extended drain transistor and method of manufacturing the same |
| WO2009001252A1 (en) * | 2007-06-27 | 2008-12-31 | Nxp B.V. | An extended drain transistor and a method of manufacturing the same |
| CN116230755A (en) * | 2023-05-05 | 2023-06-06 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and manufacturing method thereof |
| CN116230755B (en) * | 2023-05-05 | 2023-09-12 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and manufacturing method thereof |
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