JPS61119078A - Mos semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the generation of short channel effect and to prevent the decline of conductance by forming a gate electrode in a manner it covers the overall surface of a low-concentration impurity layer and a channel region. CONSTITUTION:On a surface of a P type silicon substrate 21, N<+> layers 22 and 23 which become source and drain respectively are formed and the N<-> layers 24 and 25 are formed respectively on the channel side in the vicinity of the N<+> layers 22 and 23. These N<-> layers 24 and 25 are low-concentration impurity layers for alleviating an electric field in an LDD structure and both are formed more thinly than the N<+> layers 22 and 23. On a surface of the silicon substrate 21, a gate electrode 26 is arranged through a gate insulating film 26 and the gate electrode 26 extends its ends to the internal ends of the N<+> layers 22 and 23 to become source and drain and it covers the overall surface of a channel region and the N<-> layers 24 and 25.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to an MO3 type semiconductor device, and in particular to an MO3 type semiconductor device that prevents deterioration in reliability due to hot carriers when the effective channel length is shortened. Regarding.

[Technical Background of the Invention] Generally, a MOS transistor, as shown in FIG.
For example, an N" layer 12.13 that becomes a source and a drain is formed in a P-type silicon substrate 11, and these N" layers 12.1
A gate electrode 15 is formed on a silicon substrate 11 between three layers with a gate insulating film 14 interposed therebetween.

In such a structure, as the channel length C becomes shorter, the electric field near the drain region increases and hot carriers are generated. These hot carriers insulate the gate [1
14 or forming an interfacial unit at the substrate interface, the conductance of the transistor decreases, reducing reliability.

Recently, for such a structure, a N layer 16 has been formed in the source and drain regions as shown in FIG. 5 and FIG. A structure has been proposed to reduce the generation of .

In the case of Figure 5, Double (Graded)
This is called a D Hrusad [) rain (D D D or GDD) structure, in which the N layer 16.16 is formed deeper than the N+ layer 12.13.

On the other hand, Fig. 6 shows LightV Doped
This is called a drain (LDD) structure in which the N layer 17.17 is formed shallower than the N+ layer 12.13.

[Problems of Background Art] In both the DDD structure and the LDO structure described above, forming a low concentration impurity layer near the drain region has a large effect of reducing hot carrier generation efficiency.

However, in the ODD structure MOS transistor,
N-1116 is formed by thermal diffusion after ion implantation, and in order to suppress the generation of hot carriers, the width 1 of the N-1116 needs to be about 0.2μ, so the same gate electrode Lc becomes smaller than the width La of 15. Further, the junction depth xj of the N layer 16 to the silicon substrate 11 also increases.

That is, this structure has the disadvantage that the short channel effect becomes large. Therefore, it is particularly disadvantageous to use it in a semiconductor device using a substrate bias.

Furthermore, in a MoS transistor with an LDD structure, N
"Since the layer 11 does not exist under the gate electrode 15, this N
The hot carriers generated in the layer 17
When trapped by 118, an inversion layer is likely to be formed at N-1117, resulting in a decrease in conductance.

Moreover, the N layer 17 is outside the 113111 region of the gate electrode 15. Since this region acts as a resistor, the conductance of this structure is essentially smaller than that of the structure of FIG. Further, when a semiconductor device using an LDD structure is sealed with resin, it is possible that the N layer 17 may be contaminated and the reliability may be reduced.

[Object of the Invention] The present invention has been made in view of the above-mentioned circumstances, and its purpose is to prevent the occurrence of short channel effects and a decrease in conductance, and to prevent a decrease in reliability due to hot carriers. An object of the present invention is to provide a MOS type semiconductor device that can prevent the above problems.

[Summary Page of the Invention] The present invention provides a -conductivity type semiconductor substrate, a pair of high-concentration impurity layers forming a source and a drain, which are formed spaced apart in the same substrate by impurities of a conductivity type opposite to that of the substrate; A low concentration impurity layer of a conductivity type opposite to that of the substrate is formed shallower than the high concentration impurity layer at least near the drain side of the channel region between these high concentration impurity layers, and a low concentration impurity layer is provided on the semiconductor substrate with an insulating film interposed therebetween. MOS with gate electrode
In the type semiconductor device, the gate electrode is formed to cover the channel region and the entire surface of the low concentration impurity layer.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In FIG. 1, 21 is a P-type silicon substrate, and on the surface of this silicon substrate 21 are formed N+ layers 22 and 23, which serve as sources and drains, respectively.
．． 23, there are N” layers 24 and 25 on the channel side, respectively.
is formed. These N+ layers 24 and 25 are low concentration impurity layers for relaxing the electric field in the aforementioned LDD structure, and both are formed shallower than the N+ layers 22 and 23. A gate insulator 1I26 is provided on the surface of the silicon substrate 21.
A gate electrode 26 is provided via the gate electrode 26 . This gate electrode 26 has an N'' layer 2 whose both ends become a source and a drain.
2.23 to each inner edge, covering the channel region and the entire surface of N-824°25.

Next, a method for manufacturing a MOS transistor having the above structure will be described. First, as shown in FIG. 2, thermal oxidation is performed to form a gate insulator 111 (Si0
2) Grow 26 to 300 people. Next, after forming about 4000 polycrystalline silicon layers 27 for gate electrodes by vapor phase growth, POC
The impurity phosphorus is diffused into the polycrystalline silicon layer 21 at 1000° C. by l3. Next, to form a gate electrode, PEP (Photo J, noraVinG
After forming a pattern by 1rocess), anisotropic ion etching is performed to form a polycrystalline silicon layer 21.
and end the etching with 500 people remaining. As a result, a step 27a is formed in the polycrystalline silicon layer 27.

Next, as shown in FIG. 3, N ions are implanted through the thin portion of the polycrystalline silicon layer 27 using the ion implantation method, and N ions are implanted into the source and drain regions for electric field relaxation.
Form a layer 24.25. Thereafter, approximately 4000 polycrystalline silicon layers 28 are formed on the polycrystalline silicon layer 27 by vapor phase growth. Next, as shown in Figure 1,
The entire surface of the polycrystalline silicon layer 28 is etched by anisotropic etching, and the stepped portion 27 of the polycrystalline silicon layer 21 is etched.
Only the thickly deposited portion (hereinafter referred to as spacer portion 28a) at a (gate end) is left. Here, since the polycrystalline silicon layer 28 is deposited directly on the polycrystalline silicon layer 27, the polycrystalline silicon layer 28 for the gate electrode
This means that the spacer portion 28a and the spacer portion 28a are electrically connected.

Next, a portion of the gate insulating film 26 other than the gate portion is heated using NH4.
After removal with an etching solution such as F, an N-type impurity such as arsenic is added at a high concentration into the silicon substrate 21 by ion implantation to form N+ layers 22 and 23.

In the MoS transistor formed in this manner, the N layer 24.25 of the low concentration impurity region in the source and drain regions is thermally diffused deeper than the N+ layer 22.23 as in the DDD structure described above. Since this is not necessary, the junction depth can be reduced and thus the channel length can be increased. Therefore, short channel effects can be suppressed. In addition, the spacer portion 28a that serves as a mask when forming the N4 layers 22 and 23 of the source and drain is the polycrystalline silicon layer 27.
Since it has the same potential as the gate electrode and acts as a gate electrode, the N layer 24
．． 25 isometrically below the gate electrode. Therefore, N
The decrease in conductance due to hot carriers generated in 24 and 25 is further reduced.

In the above embodiment, the N layer is the source.

Although the structure is such that the electrodes are provided on both drain sides, the present invention is not limited to this, and may be provided only on the drain side. In addition, although conductive polycrystalline silicon was used as the gate electrode and spacer material, molybdenum silicide (MoS) was used instead of the polycrystalline silicon layer.
i), molybdenum silicide (MoSi)
In an element using a two-layer structure of polycrystalline silicon and polycrystalline silicon, the material for forming the spacer 28a is molybdenum silicide for the molybdenum silicide gate element, and polycrystalline for the element with a polycide structure of polycrystalline silicon and molybdenum silicide. Silicone shall be used.

[Effects of the Invention] As described above, the present invention provides a MOS type semiconductor that can prevent short channel effects from occurring, prevent conductance from decreasing, and prevent reliability from decreasing due to hot carriers. equipment can be provided.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing the structure of a MOS transistor according to an embodiment of the present invention, FIGS. 2 and 3 are cross-sectional views showing the manufacturing process of the structure of FIG. 1, and FIGS. 4 to 6 are FIG. 3 is a cross-sectional view showing the structure of a conventional MOS transistor. 21...Silicon substrate, 22.23...N+ layer, 2
4.25...N single layer, 26...gate insulating film, 27
．． 28... Polycrystalline silicon film, 28a... Spacer portion.

Claims (1)

[Claims] A semiconductor substrate of one conductivity type, a pair of high-concentration impurity layers formed separately in the same substrate with impurities of a conductivity type opposite to this substrate and serving as a source and a drain, and at least a channel region between these high-concentration impurity layers. a low concentration impurity layer of a conductivity type opposite to that of the substrate formed near the drain side to be shallower than the high concentration impurity layer; and a low concentration impurity layer provided on the semiconductor substrate via an insulating film, covering the entire surface of the channel region and the low concentration impurity layer. 1. A MOS type semiconductor device comprising a gate electrode provided so as to cover the gate electrode.