JPH03120836A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve the breakdown strength of an element, and restrain the generation of hot carrier affecting the reliability of the element, by forming an LDD structure having a graded junction wherein a low concentration impurity diffusion layer surrounds a high concentration impurity diffusion layer in a source.drain region. CONSTITUTION:The title device is provided with the following; a gate electrode 3 formed, via a gate insulating film 2, on an element forming region formed on a conductivity type semiconductor substrate 1, a first opposite conductivity type low concentration layer 7 formed in the element forming region so as to be matched with the gate electrode 3, a second opposite conductivity type low concentration diffusion layer 6 formed so as to be matched with an insulating film 4 formed on the side wall of the gate electrode 3 and be connected with the first opposite conductivity type low concentration diffusion layer 7 in the element forming region, and an opposite conductivity type high concentration diffusion layer 5 formed in the second opposite conductivity type low concentration diffusion layer 6. For example, phosphorus ion is implanted by using the gate electrode 3 and a side spacer 4 as masks; then arsenic ion is implanted, heat treatment is performed, an N<-> type diffusion layer 6 connected with an N<-> type diffusion layer 7 and an N<+> type diffusion layer 5 shallowly formed in an N<-> type diffusion layer 6 are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having an MIS type field effect transistor.

[Conventional technology]

As the gate length of MIS type field effect transistors becomes shorter, the electric field near the drain becomes extremely large during operation, resulting in serious problems such as an increase in short channel effects and a decrease in reliability due to characteristic deterioration due to hot carrier injection. ing.

In order to prevent this and improve reliability, especially withstand voltage, a highly concentrated diffusion layer is provided offset from the gate electrode.
The LDD structure (Light) has a low concentration diffusion layer in the middle.
tly Doped Drain structure) is known.

FIG. 3 is a sectional view of a conventional semiconductor device.

As shown in FIG. 3, using a gate electrode 3 provided on the surface of the element formation region formed on one principal surface of the P-type silicon substrate 1 via a gate oxide film 2 as a mask, an N-type silicon substrate 1 is formed on the element formation region. Using the diffusion region 7 and the insulating film (hereinafter referred to as side spacer) 4 provided on one side wall of the gate electrode 3 as a mask, an N+ type scattering layer 5 is provided in the element formation region connected to the N− type diffusion layer 7. A semiconductor device having an MIS field effect transistor with an LDD structure is constructed.

[Problem to be solved by the invention]

The above-described conventional semiconductor device has the drawback that the high concentration diffusion layer is provided in direct contact with the semiconductor substrate, and therefore has insufficient breakdown voltage and severe short channel effect.

[Means to solve the problem]

The semiconductor device of the present invention includes a gate electrode provided on an element formation region provided on a conductivity type semiconductor substrate via a gate insulating film, and a gate electrode provided in the element formation region in alignment with the gate electrode. a second opposite conductivity type low concentration diffusion layer provided in alignment with an insulating film provided on a side wall of the gate electrode and connected to the first opposite conductivity type low concentration diffusion layer in the element formation region;
and a reverse conductivity type high concentration diffusion layer provided in the second reverse conductivity type low concentration diffusion layer.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1A to 1C are cross-sectional views of a semiconductor chip shown in the order of steps for explaining the manufacturing method of the first embodiment of the present invention.

First, as shown in FIG. 1(a), a P-type silicon substrate 1
An element isolation region (not shown) is selectively provided on the entire surface to form an element formation region, and the surface of the element formation region is thermally oxidized to form a gate oxide film 2 with a thickness of 20 to 30 nm.

Next, a polycrystalline silicon film doped with phosphorus at a high concentration, a high melting point metal silicide film, or a composite film thereof is deposited to a thickness of 0.4 μm on the gate oxide film 2, and this is selectively etched. Then, gate electrode 3 is formed. Next, using the gate electrode 3 as a mask, phosphorus ions are accelerated with an energy of 4
Ion implantation is performed under the conditions of 0 keV and a dose of 5×10 13 C111-2 to form an N − type diffusion layer 7 .

Next, as shown in FIG. 1(b), a silicon oxide film is deposited to a thickness of 0.3 μm on the surface including the gate electrode 3, and then anisotropically etched by reactive ion etching (RIE). A side spacer 4 having a thickness of 0.3 μm is provided on the side wall of the gate electrode 3.

Next, as shown in FIG. 1(c), using the gate electrode 3 and side spacer 4 as a mask, phosphorus ions are accelerated with an energy of 100 keV and a dose of 1×10 cm-, and then arsenic ions are accelerated with an energy of 100 keV and a dose of 1×10 cm. 70keV,
Sequential ion implantation and heat treatment were performed under the conditions of a dose of 5 x 1015 cm-2 to form an N- type diffusion layer 6 connected to the N- type diffusion layer 7 and an N+ type diffusion layer 6 formed shallowly within the N- type diffusion layer 6. Each layer 5 is provided to constitute a MIS type field effect transistor having an LDD structure.

Here, the N+ type diffused layer 5 is surrounded by the N- type diffused layer 6 formed of phosphorus, forming a sloped junction, and the N
Since the + type scattering layer 5 is located away from directly under the gate electrode 3 and is offset, the internal electric field of the source/drain diffusion layer is weakened and the withstand voltage of the source/drain diffusion layer can be improved. , and it is possible to reduce hot carriers that greatly affect the reliability of the device.

FIG. 2 is a sectional view of a second embodiment of the invention.

As shown in FIG. 2, the side spacers on the source side are selectively removed, and the side spacers 4 are provided only on the side wall of the gate electrode 3 on the drain side, and an N- type diffusion region 7 is formed on the drain side.
It has the same structure as the first embodiment except that an N- type diffusion layer 6 matched with the gate voltage @3 is provided on the source side and an N+ type scattering layer 5 is provided in the N- type diffusion layer 6. ing.

In this embodiment, since only the drain side diffusion layer has an LDD structure, there is an advantage that the parasitic resistance occurring in the low impurity concentration region can be halved compared to the first embodiment.

〔Effect of the invention〕

As explained above, the present invention can improve the withstand voltage of the device by forming an LDD structure having an inclined junction in which a high impurity concentration diffusion layer in the source/drain region is surrounded by a low impurity concentration diffusion layer. In addition, it is possible to suppress the generation of hot carriers that affect the reliability of the device, and it is possible to provide a highly reliable semiconductor device.

[Brief explanation of drawings]

FIGS. 1(a) to (c) are cross-sectional views of a semiconductor chip shown in the order of steps to explain the manufacturing method of the first embodiment of the present invention, and FIG. Sectional view shown, 3rd
The figure is a cross-sectional view of a conventional semiconductor device. 1...P-type silicon substrate, 2...gate oxide film, 3
...Gate electrode, 4...Side spacer, 5...
N+ type diffused layer 6, 7...N- type diffused layer.

Claims (1)

[Claims] A gate electrode provided on an element formation region provided on a semiconductor substrate of one conductivity type via a gate insulating film, and a first opposite conductivity type low concentration provided in the element formation region in alignment with the gate electrode. a second reverse conductivity type low concentration diffusion layer provided in alignment with the diffusion layer and the insulating film provided on the side wall of the gate electrode and connected to the first reverse conductivity type low concentration diffusion layer in the element formation region; and a reverse conductivity type high concentration diffusion layer provided within the second reverse conductivity type low concentration diffusion layer.