JPH06283713A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH06283713A JPH06283713A JP6725693A JP6725693A JPH06283713A JP H06283713 A JPH06283713 A JP H06283713A JP 6725693 A JP6725693 A JP 6725693A JP 6725693 A JP6725693 A JP 6725693A JP H06283713 A JPH06283713 A JP H06283713A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- region
- insulating film
- gate
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 16
- 238000004519 manufacturing process Methods 0.000 title description 8
- 239000000969 carrier Substances 0.000 claims abstract description 5
- 239000012535 impurity Substances 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 238000005468 ion implantation Methods 0.000 claims description 5
- 238000005192 partition Methods 0.000 claims description 5
- 230000000694 effects Effects 0.000 abstract description 10
- 230000005669 field effect Effects 0.000 abstract description 4
- 238000009792 diffusion process Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- -1 cesium ions Chemical class 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052792 caesium Inorganic materials 0.000 description 1
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28176—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the definitive gate conductor
Landscapes
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Physics & Mathematics (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Chemical & Material Sciences (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置及びその製
造方法に関し、特にＭＩＳ型電界効果トランジスタ及び
その製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method, and more particularly to a MIS field effect transistor and its manufacturing method.
【０００２】[0002]
【従来の技術】半導体集積回路の高集積化に伴い、集積
回路を構成するＭＯＳＦＥＴのゲート長の微細化が進ん
でいる。微細ゲート長を有するＭＯＳＦＥＴでは、しき
い値電圧のゲート長依存性が大きい、パンチスルーし易
い等の短チャネル効果が顕在化してきている。2. Description of the Related Art With the high integration of semiconductor integrated circuits, the gate lengths of MOSFETs forming the integrated circuits are becoming finer. In a MOSFET having a fine gate length, short channel effects such as a large gate length dependency of a threshold voltage and easy punch-through are becoming apparent.
【０００３】このような短チャネル効果を防ぐために、
従来種々のデバイス構造が検討されている。その１つと
して、ゲート電極に隣接するソース・ドレイン領域の端
部を覆うように接して形成したソース・ドレイン領域と
異なる導電型の不純物領域を有するポケット構造が、１
９８２年インターナショナル・エレクトロン・デバイス
セス・ミーティング（Ｉｎｔｅｒｎａｔｉｏｎａｌ Ｅ
ｌｅｃｔｒｏｎ Ｄｅｖｉｃｅｓ Ｍｅｅｔｉｎｇ）の
テクニカル・ダイジェスト（Ｔｅｃｈｎｉｃａｌ Ｄｉ
ｇｅｓｔ）第７１８頁から第７２１頁に提案されてい
る。図２は、従来のポケット構造のＭＯＳＦＥＴの代表
的な一例を示す断面図である。In order to prevent such a short channel effect,
Various device structures have been studied so far. As one of them, a pocket structure having an impurity region of a conductivity type different from that of the source / drain region formed so as to contact the end portion of the source / drain region adjacent to the gate electrode is formed.
982 International Electron Device Meeting (International E)
Technical Digest of Technical Devices (Technical Di)
best) proposed on pages 718 to 721. FIG. 2 is a sectional view showing a typical example of a conventional MOSFET having a pocket structure.
【０００４】図２に示すように、ｎ型シリコン基板１に
設けて素子形成領域を区画するフィールド酸化膜２と、
素子形成領域の表面に設けたゲート酸化膜３およびゲー
ト酸化膜３上に設けたゲート電極４と、ゲート電極４に
整合して素子形成領域に設けたｐ型のソース・ドレイン
領域６と、チャネル領域に隣接するソース・ドレイン領
域６の端部を覆うように設けたｎ型シリコン基板よりも
少し不純物濃度の高いｎ型不純物拡散領域８とを有して
構成され、このｎ型不純物拡散領域を存在させることに
より、ドレイン領域からチャネル領域への空乏層の広が
りが抑制され、短チャネル効果を緩和することが可能と
なった。As shown in FIG. 2, a field oxide film 2 is provided on an n-type silicon substrate 1 to partition an element formation region,
A gate oxide film 3 provided on the surface of the element formation region, a gate electrode 4 provided on the gate oxide film 3, a p-type source / drain region 6 provided in the element formation region in alignment with the gate electrode 4, and a channel And an n-type impurity diffusion region 8 having a slightly higher impurity concentration than the n-type silicon substrate provided so as to cover the ends of the source / drain regions 6 adjacent to the region. By making it exist, the spread of the depletion layer from the drain region to the channel region is suppressed, and the short channel effect can be mitigated.
【０００５】[0005]
【発明が解決しようとする課題】この従来の半導体装置
では、ｎ型不純物拡散領域をソース・ドレイン領域の端
部のみに形成することが望ましいが、端部にのみ形成す
るにはマスク工程が必要となり、製造工程が複雑とな
る。In this conventional semiconductor device, it is desirable to form the n-type impurity diffusion regions only at the ends of the source / drain regions, but a mask process is required to form the n-type impurity diffusion regions only at the ends. Therefore, the manufacturing process becomes complicated.
【０００６】また、工程を簡略化するために、ソース・
ドレイン領域の接合面全面に接してｎ型不純物拡散領域
を形成すると、接合容量が増大し、デバイス特性の劣化
を生じるという問題点があった。また、ポケット構造形
成のために、基板内に局所的に不純物を導入する為に、
製造プロセスのマージンが大幅に減少するという問題点
もあった。Further, in order to simplify the process, the source
When the n-type impurity diffusion region is formed in contact with the entire junction surface of the drain region, the junction capacitance increases, which causes a problem of deterioration of device characteristics. Further, in order to locally introduce impurities into the substrate to form a pocket structure,
There is also a problem that the margin of the manufacturing process is significantly reduced.
【０００７】本発明の目的は、短チャネル効果を低減で
きる新規なＭＩＳ型電界効果トランジスタを提供するこ
とにある。An object of the present invention is to provide a novel MIS type field effect transistor capable of reducing the short channel effect.
【０００８】[0008]
【課題を解決するための手段】本発明の半導体装置は、
一導電型半導体の一主面に設けて素子形成領域を区画す
るフィールド絶縁膜と、前記素子形成領域の表面に設け
たゲート絶縁膜と、前記ゲート絶縁膜上に設けたゲート
電極と、前記ゲート電極に整合して前記素子形成領域に
設けた逆導電型のソース・ドレイン領域と、前記ソース
・ドレイン領域に隣接する前記ゲート電極の両端部直下
の前記ゲート絶縁膜内に局所的に設けた前記ゲート電極
下のチャネル領域を通過するキャリアと同じ極性の固有
電荷を有する。The semiconductor device of the present invention comprises:
A field insulating film that is provided on one main surface of one conductivity type semiconductor to partition an element forming region, a gate insulating film provided on the surface of the element forming region, a gate electrode provided on the gate insulating film, and the gate The source / drain regions of the opposite conductivity type provided in the element formation region in alignment with the electrodes, and the locally provided in the gate insulating film immediately below both ends of the gate electrode adjacent to the source / drain regions. It has an intrinsic charge of the same polarity as the carriers passing through the channel region under the gate electrode.
【０００９】本発明の半導体装置の製造方法は、一導電
型半導体基板の一主面に選択的にフィールド絶縁膜を設
けて素子形成領域を区画する工程と、前記素子形成領域
の表面に設けたゲート絶縁膜の上に選択的にゲート電極
を形成する工程と、前記ゲート電極をマスクとして斜め
イオン注入法により前記ゲート電極の両端部直下の前記
ゲート絶縁膜に不純物を注入して前記ゲート電極下のチ
ャネル領域を通過するキャリアと同じ極性の固定電荷を
局所的に形成する工程と、前記ゲート電極に整合して前
記素子領域に逆導電型のソース・ドレイン領域を形成す
る工程とを含んで構成される。The method of manufacturing a semiconductor device according to the present invention comprises a step of selectively providing a field insulating film on one main surface of a one-conductivity-type semiconductor substrate to partition an element forming region, and a step of providing the element forming region on the surface. A step of selectively forming a gate electrode on the gate insulating film; and a step of implanting an impurity into the gate insulating film directly below both ends of the gate electrode by an oblique ion implantation method using the gate electrode as a mask to form the gate electrode And a step of locally forming a fixed charge having the same polarity as that of carriers passing through the channel region, and a step of forming source / drain regions of opposite conductivity type in the element region in alignment with the gate electrode. To be done.
【００１０】[0010]
【作用】本発明によるトランジスタでは、ゲート電極形
成後に、斜めイオン注入法により、ゲート電極の両端部
直下のゲート絶縁膜中に局所的に固定電荷を導入するこ
とによって、トランジスタの閾値電圧を局所的に制御す
ることが可能である。また、イオン注入量と注入エネル
ギーを制御することにより、ソース・ドレイン領域近傍
のゲート電極端部の閾値をゲート電極中央部の閾値より
も高く設定することが可能であり、その結果、トランジ
スタにおいて、短チャネル効果を大幅に抑制することが
できる。In the transistor according to the present invention, after the gate electrode is formed, a fixed charge is locally introduced into the gate insulating film immediately below both ends of the gate electrode by the oblique ion implantation method to locally change the threshold voltage of the transistor. It is possible to control. Further, by controlling the ion implantation amount and the implantation energy, it is possible to set the threshold value of the gate electrode end portion in the vicinity of the source / drain regions higher than the threshold value of the gate electrode central portion, and as a result, in the transistor, The short channel effect can be significantly suppressed.
【００１１】図３は、ＭＯＳトランジスタの閾値電圧の
ゲート長依存性を示す特性図であり、従来のｐチャネル
ＭＯＳＦＥＴと本発明によるｐチャネルＭＯＳＦＥＴと
を比較した結果である。図から明らかなように、本発明
によるトランジスタでは短チャネル効果が大幅に抑制さ
れていることがわかる。FIG. 3 is a characteristic diagram showing the gate length dependence of the threshold voltage of a MOS transistor, which is the result of comparison between the conventional p-channel MOSFET and the p-channel MOSFET according to the present invention. As is clear from the figure, the short channel effect is significantly suppressed in the transistor according to the present invention.
【００１２】[0012]
【実施例】次に、本発明について図面を参照して説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.
【００１３】図１（ａ）〜（ｃ）は本発明の一実施例の
製造方法を説明するための工程順に示した半導体チップ
の断面図である。FIGS. 1A to 1C are sectional views of a semiconductor chip showing the order of steps for explaining a manufacturing method according to an embodiment of the present invention.
【００１４】まず、図１（ａ）に示すように、ｎ型シリ
コン基板１の一主面を選択的に酸化してフィールド酸化
膜２を形成し、素子形成領域を区画する。次に、この素
子形成領域の表面に設けたゲート酸化膜３の上に多結晶
シリコン膜を堆積してパターニングし、ゲート電極４を
形成する。First, as shown in FIG. 1A, one main surface of an n-type silicon substrate 1 is selectively oxidized to form a field oxide film 2 to define an element forming region. Then, a polycrystalline silicon film is deposited on the gate oxide film 3 provided on the surface of the element forming region and patterned to form a gate electrode 4.
【００１５】次に、図１（ｂ）に示すように、ゲート電
極４をマスクとしてセシウムイオンを斜め方向よりイオ
ン注入（斜めイオン注入法）してゲート電極４の両端直
下のゲート酸化膜３中に性の極性を有する固定電荷５を
局所的に発生させる。Next, as shown in FIG. 1B, cesium ions are obliquely ion-implanted (oblique ion-implantation method) using the gate electrode 4 as a mask in the gate oxide film 3 immediately below both ends of the gate electrode 4. A fixed charge 5 having a negative polarity is locally generated.
【００１６】次に、図１（ｃ）に示すように、ゲート電
極４及びフィールド酸化膜２をマスクとして二弗化ホウ
素をイオン注入しｐ型のソース・ドレイン領域６を形成
する。次に、ゲート電極４を含む表面に層間絶縁膜７を
堆積する。Next, as shown in FIG. 1C, boron difluoride is ion-implanted using the gate electrode 4 and the field oxide film 2 as a mask to form p-type source / drain regions 6. Next, the interlayer insulating film 7 is deposited on the surface including the gate electrode 4.
【００１７】本実施例では、ｐチャネルＭＯＳＦＥＴの
場合について説明したが、ｎチャネルＭＯＳＦＥＴの場
合にも同様に構成でき、ゲート電極の両端直下のゲート
酸化膜中にホウ素イオンを斜めイオン注入することによ
り、負の極性を有する固定電荷を局所的に発生できる。In the present embodiment, the case of the p-channel MOSFET has been described, but the same structure can be applied to the case of the n-channel MOSFET, and boron ions are obliquely implanted into the gate oxide film directly below both ends of the gate electrode. A fixed charge having a negative polarity can be locally generated.
【００１８】また、ゲート絶縁膜として酸化シリコン膜
以外に窒化シリコン等を用いても良く、さらに、シング
ル・ドレイン構造のＭＯＳＦＥＴ以外にＬＤＤ（ｌｉｇ
ｈｔｌｙ ｄｏｐｅｄ ｄｒａｉｎ）構造のＭＯＳＦＥ
Ｔに適用しても同様の効果が得られる。Besides the silicon oxide film, silicon nitride or the like may be used as the gate insulating film, and LDD (lig) other than the single drain structure MOSFET may be used.
MOSTE of html doped drain structure
Even when applied to T, the same effect can be obtained.
【００１９】[0019]
【発明の効果】以上説明したように本発明は、ゲート電
極の両端直下のゲート絶縁膜中にチャネル領域を流れる
キャリアと同じ極性の固定電荷を局所的に設けることに
より、ソース・ドレイン領域近傍のゲート電極端部の閾
値をゲート電極中央部の閾値よりも高く設定することが
可能となり、従来のポケット構造のＭＯＳＦＥＴのよう
に半導体基板内の不純物濃度を通常のＭＯＳＦＥＴに対
して変化させることがなく、従って従来のポケット構造
のＭＯＳＦＥＴのようにキャリアの移動度の劣化を生じ
ることなしに短チャネル効果を大幅に改善したＭＩＳ型
電界効果トランジスタを実現できるという効果を有す
る。As described above, according to the present invention, a fixed charge having the same polarity as that of carriers flowing in the channel region is locally provided in the gate insulating film immediately below both ends of the gate electrode, so that the fixed charge in the vicinity of the source / drain region is provided. It is possible to set the threshold value at the end of the gate electrode higher than the threshold value at the center of the gate electrode, without changing the impurity concentration in the semiconductor substrate as compared with the normal MOSFET unlike the conventional pocket structure MOSFET. Therefore, there is an effect that it is possible to realize a MIS type field effect transistor in which the short channel effect is significantly improved without causing deterioration of carrier mobility, unlike the conventional pocket structure MOSFET.
【図１】本発明の一実施例の製造方法を説明するための
工程順に示した半導体チップの断面図。FIG. 1 is a cross-sectional view of a semiconductor chip showing the order of steps for explaining a manufacturing method according to an embodiment of the present invention.
【図２】従来の半導体装置の一例を示す半導体チップの
断面図。FIG. 2 is a sectional view of a semiconductor chip showing an example of a conventional semiconductor device.
【図３】ＭＯＳＦＥＴの閾値電圧のゲート長依存性を示
す特性図。FIG. 3 is a characteristic diagram showing the gate length dependence of a threshold voltage of a MOSFET.
１ ｎ型シリコン基板 ２ フィールド酸化膜 ３ ゲート酸化膜 ４ ゲート電極 ５ 固定電荷 ６ ソース・ドレイン領域 ７ 層間絶縁膜 ８ ｎ型不純物拡散領域 1 n-type silicon substrate 2 field oxide film 3 gate oxide film 4 gate electrode 5 fixed charge 6 source / drain region 7 interlayer insulating film 8 n-type impurity diffusion region
Claims (2)
成領域を区画するフィールド絶縁膜と、前記素子形成領
域の表面に設けたゲート絶縁膜と、前記ゲート絶縁膜上
に設けたゲート電極と、前記ゲート電極に整合して前記
素子形成領域に設けた逆導電型のソース・ドレイン領域
と、前記ソース・ドレイン領域に隣接する前記ゲート電
極の両端部直下の前記ゲート絶縁膜内に局所的に設けた
前記ゲート電極下のチャネル領域を通過するキャリアと
同じ極性の固有電荷を有することを特徴とする半導体装
置。1. A field insulating film provided on one main surface of a semiconductor of one conductivity type to partition an element forming region, a gate insulating film provided on a surface of the element forming region, and a gate provided on the gate insulating film. An electrode, a source / drain region of opposite conductivity type provided in the element formation region in alignment with the gate electrode, and locally in the gate insulating film immediately below both ends of the gate electrode adjacent to the source / drain region. A semiconductor device having an intrinsic charge of the same polarity as that of carriers passing through a channel region under the gate electrode, which is provided in a specific manner.
フィールド絶縁膜を設けて素子形成領域を区画する工程
と、前記素子形成領域の表面に設けたゲート絶縁膜の上
に選択的にゲート電極を形成する工程と、前記ゲート電
極をマスクとして斜めイオン注入法により前記ゲート電
極の両端部直下の前記ゲート絶縁膜に不純物を注入して
前記ゲート電極下のチャネル領域を通過するキャリアと
同じ極性の固定電荷を局所的に形成する工程と、前記ゲ
ート電極に整合して前記素子領域に逆導電型のソース・
ドレイン領域を形成する工程とを含むことを特徴とする
半導体装置の製造方法。2. A step of selectively providing a field insulating film on one main surface of a one conductivity type semiconductor substrate to partition an element forming region, and a step of selectively forming a gate insulating film on the surface of the element forming region. A step of forming a gate electrode on the gate electrode, and a carrier passing through a channel region under the gate electrode by injecting an impurity into the gate insulating film immediately below both ends of the gate electrode by an oblique ion implantation method using the gate electrode as a mask. A process of locally forming fixed charges of the same polarity and a source of opposite conductivity type in the device region in alignment with the gate electrode.
And a step of forming a drain region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6725693A JPH06283713A (en) | 1993-03-26 | 1993-03-26 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6725693A JPH06283713A (en) | 1993-03-26 | 1993-03-26 | Semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06283713A true JPH06283713A (en) | 1994-10-07 |
Family
ID=13339688
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6725693A Pending JPH06283713A (en) | 1993-03-26 | 1993-03-26 | Semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06283713A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6054357A (en) * | 1996-12-20 | 2000-04-25 | Hyundai Electronics Industries Co., Ltd. | Semiconductor device and method for fabricating the same |
| US6521958B1 (en) * | 1999-08-26 | 2003-02-18 | Micron Technology, Inc. | MOSFET technology for programmable address decode and correction |
| US6956772B2 (en) | 2001-02-13 | 2005-10-18 | Micron Technology, Inc. | Programmable fuse and antifuse and method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01174168A (en) * | 1987-12-28 | 1989-07-10 | Fuji Xerox Co Ltd | Picture signal processing circuit |
| JPH01296670A (en) * | 1988-05-25 | 1989-11-30 | Toshiba Corp | Semiconductor device |
| JPH02174168A (en) * | 1988-12-26 | 1990-07-05 | Nippon Telegr & Teleph Corp <Ntt> | Mis field effect transistor |
-
1993
- 1993-03-26 JP JP6725693A patent/JPH06283713A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01174168A (en) * | 1987-12-28 | 1989-07-10 | Fuji Xerox Co Ltd | Picture signal processing circuit |
| JPH01296670A (en) * | 1988-05-25 | 1989-11-30 | Toshiba Corp | Semiconductor device |
| JPH02174168A (en) * | 1988-12-26 | 1990-07-05 | Nippon Telegr & Teleph Corp <Ntt> | Mis field effect transistor |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6054357A (en) * | 1996-12-20 | 2000-04-25 | Hyundai Electronics Industries Co., Ltd. | Semiconductor device and method for fabricating the same |
| US6521958B1 (en) * | 1999-08-26 | 2003-02-18 | Micron Technology, Inc. | MOSFET technology for programmable address decode and correction |
| US6700821B2 (en) | 1999-08-26 | 2004-03-02 | Micron Technology, Inc. | Programmable mosfet technology and programmable address decode and correction |
| US6909635B2 (en) | 1999-08-26 | 2005-06-21 | Micron Technology, Inc. | Programmable memory cell using charge trapping in a gate oxide |
| US6956772B2 (en) | 2001-02-13 | 2005-10-18 | Micron Technology, Inc. | Programmable fuse and antifuse and method thereof |
| US7177193B2 (en) | 2001-02-13 | 2007-02-13 | Micron Technology, Inc. | Programmable fuse and antifuse and method therefor |
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