JPH04127439A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make the concentration grade of impurities in a diffusion layer gentle and to weaken an electric field exerted on the diffusion layer by a method wherein an ion implantation operation in the inclined direction whose angle formed by the normal line of a semiconductor substrate and by the impinging direction of impurity ions is different is executed several times to the semiconductor substrate having a difference in level. CONSTITUTION:A polycrystalline silicon gate electrode 3 is formed on a P-type silicon substrate 1 via a gate oxide film 2; after that, the P-type silicon substrate 1 is tilted in such a way that an angle formed by the advance direction of an implantation beam and by the normal line of the P-type silicon substrate 1 is at 30 deg.; arsenic ions are implanted perpendicularly to the width direction of a gate; diffusion layers 4a, 5a are formed. Then, the P-type silicon substrate is turned by using the normal line of the P-type silicon substrate 1 as an axis; arsenic ions are implanted; diffusion layers 4a, 5b, 5c are formed. An impurity concentration becomes higher in the order of diffusion layers 4f, 4g, 4n, 4p and 4q (5m, 5n, 5s, 5t and 5u); an LDD diffusion layer has a five-step concentration grade in a state immediately after an implantation operation.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a semiconductor device.

[Conventional technology]

FIG. 7 shows an LDD (Lightly
FIG. 3 is a process cross-sectional view showing a method of forming a doped drain. This LDD is a lightly doped diffusion layer provided between the source (train) diffusion layer and the channel portion under the gate, and has the effect of relaxing the electric field in the gate length direction.

Hereinafter, a conventional method for manufacturing a semiconductor device will be explained with reference to FIG.

First, after forming a polycrystalline silicon gate electrode 3 on a P-type silicon substrate 1 via a gate oxide film 2, as shown in FIG. P so that the angle formed by the normal line of is 30°
Tilt the mold silicon substrate 1 and apply arsenic ions perpendicularly to the gate width direction (direction perpendicular to the cross-sectional view) at an acceleration energy of 65K.
eV and a dose of 5EI2 cm-' to form diffusion layers 4a and 5a.

Next, in FIG. 7(b), the P-type silicon substrate l is
The arsenic ions were accelerated at an energy of 65 KeV by rotating the mold silicon substrate 1 by 90 degrees around its normal line.

The diffusion layer 4b is implanted at a dose of 5E12 cm-''.

5b and 5c are formed.

Next, in FIG. 7(C), the P-type silicon substrate 1 is
The silicon substrate 1 is further rotated by 90 degrees about the normal line of the silicon substrate 1, and arsenic ions are implanted at an acceleration energy of 65 KeV and a dose of 5E12 cm-'' to form diffusion layers 4c, 5d,
5e and 5f are formed.

Next, in FIG. 7 fdl, the P type silicon substrate l is
The silicon substrate 1 is further rotated by 90 degrees about the normal line of the silicon substrate 1, and arsenic ions are implanted at an acceleration energy of 65 KeV and a dose of 5E12ao-'' to form diffusion layers 4d, 4e,
5g and 5h are formed, and then heat treatment is performed for 60 minutes in a nitrogen atmosphere at 900°C.

In the conventional LDD structure semiconductor device formed as described above, the diffusion layers 4a and 4d after implantation.

4e (5d, 5g, 5h) impurity concentration ratio or 1:
The ratio will be 3:4. Furthermore, an LDD structure with a gentle concentration gradient can be formed by thermal diffusion after implantation. Therefore, the electric field in the gate length direction is relaxed, the generation of hot carriers is reduced, and deterioration of the MOS transistor characteristics over time can be suppressed.

[Problem to be solved by the invention]

However, in the above configuration, especially in a MOS transistor with a gate length shorter than 1 μm, the effective channel length is shortened due to the diffusion of impurities under the gate, causing problems such as short channel effect and increased leakage current due to punch-through. vinegar. On the other hand, if the diffusion of impurities under the gate is suppressed by lowering the heat treatment temperature or shortening the heat treatment time, it becomes impossible to form a gentle concentration gradient, and as a result, the electric field in the channel length direction of the MOS transistor becomes stronger. Therefore, there was a problem in that the hot carrier reliability of the transistor decreased.

Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device that can reduce the concentration gradient of impurities in a diffusion layer and weaken the electric field applied to the diffusion layer.

[Means to solve the problem]

The method for manufacturing a semiconductor device according to claim (1) is characterized in that ion implantation is performed in a plurality of oblique directions at different angles between the normal line of the semiconductor substrate and the direction of impurity ion incidence into a semiconductor substrate having a step. do.

Further, in the method for manufacturing a semiconductor device according to claim (2), after forming a gate electrode on a semiconductor substrate, while rotating the semiconductor substrate around the normal line of the semiconductor substrate, the normal line of the semiconductor substrate and impurity ions are The method of manufacturing a semiconductor device according to claim 3, characterized in that a diffusion layer which becomes a source and a drain of a MOS transistor is formed by performing oblique ion implantation a plurality of times with different angles of incidence of the ions. After forming an element isolation region on a semiconductor substrate, a step is formed on the element isolation region, and then oblique ion implantation is performed multiple times at different angles between the normal to the semiconductor substrate and the impurity ion incident direction. It is characterized by forming a diffusion layer close to the element isolation region.

[For production]

According to the configuration described in claim 11, impurity ions are implanted diagonally multiple times into a semiconductor substrate having steps at different angles formed by the incident direction of the impurity ions.
The shadow region formed by the step differs depending on the implantation angle, and a plurality of regions with different impurity concentrations are formed in the created diffusion layer.

According to the structure recited in claim (2), the gate electrode on the semiconductor substrate has a step, and impurity ions are implanted obliquely multiple times at different implantation angles into the semiconductor substrate having the step, so that the step is eliminated. The shadow region formed by this method differs depending on the implantation angle, and a plurality of regions having different impurity concentrations are formed in the diffusion layer formed as the source and drain.

According to the structure recited in claim (3), a step is formed on an element isolation region provided in a semiconductor substrate, and impurity ions are obliquely implanted multiple times at different implantation angles into the semiconductor substrate having the step. Since the implantation is performed, a plurality of regions with different impurity concentrations are sequentially formed in the diffusion layer formed adjacent to the element isolation region, depending on the implantation angle, depending on the shadow region created by the step.

C Embodiment] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a process cross-sectional view showing a method of forming a DD diffusion layer of an N-type MOS transistor in a method of manufacturing a semiconductor device according to a first embodiment of the present invention.

The method for manufacturing the semiconductor device of this first embodiment will be described below with reference to FIG.

First, in FIG. 1(a), after forming a polycrystalline silicon gate electrode 3 on a P-type silicon substrate 1 via a gate oxide film 2, the direction of propagation of the implantation beam (indicated by an arrow) and the P-type silicon substrate l are shown. Tilt the P-type silicon substrate I at an angle of 30' between the normal lines of
, is implanted at a dose of 1.25 E I 2 cm-' to form diffusion layers 4a and 5a.

Next, in FIG. 1fbl, the P-type silicon substrate 1 is
The mold silicon substrate 1 is rotated by 90 degrees around the normal line, and arsenic ions are accelerated with an energy of 65 KeV at a dose j11.2.
5 E I 2 cm-', diffusion layers 4b5b, 5
form c.

Next, in FIG. 1 fc), the P-type silicon substrate l is
The substrate is further rotated by 90 degrees about the normal to the silicon substrate l, and arsenic ions are implanted at an acceleration energy of 65 KeV and a dose fi of 1.25 E 12 cm-'' to form diffusion layers 4c, 5d, 5e, and 5f.

Next, in FIG. 1fdl, the P type silicon substrate 1 is
The substrate is further rotated by 90° about the normal to the silicon substrate 1, and arsenic ions are implanted at an acceleration energy of 65 KeV and a dose of 1.25 El 2 cm-' to form diffusion layers 4d, 4e, 5g, and 5h. .

Next, in Fig. 1 fe), the angle between the advancing direction of the implantation beam (indicated by the arrow) and the normal to the P-type silicon substrate l is 4.
The P-type silicon substrate I was tilted at an angle of 5°, and arsenic ions were accelerated at an energy of 80 KeV perpendicular to the gate width direction (direction perpendicular to the cross-sectional view).

It was implanted at a dose of 3.75 E 12 cm-' to form a diffusion layer 4f.

4g, 4h, 4i, and 5i are formed.

Next, in Figure 1), the P-type silicon substrate 1 is rotated 90' around the normal line of the P-type silicon substrate 1, and arsenic ions are accelerated with an energy of 80 KeV.

The diffusion layer 4j is implanted at a dose of 3.75 E 12 cm-''.

Form 4, 5j, 5, and 5f.

Next, in FIG. 1(g), the P-type silicon substrate l is
The substrate was further rotated 90 degrees around the normal to the type silicon substrate I, and arsenic ions were implanted at an acceleration energy of 80 KeV and a dose of 3.75 E I 2 cm-'' to form diffusion layers of 41.4 m, 5 m, 5 n, 5 p, 5q.

Form 5r.

Next, in FIG. 1, the P-type silicon substrate l is
The silicon substrate I is further rotated by 90 degrees around the normal line, and arsenic ions are implanted at an acceleration energy of 80 KeV and a dose of 3.75 E I 2 cm-' to form diffusion layers 4n, 4p, 4q, 5s, 5t, After that, heat treatment is performed for 30 minutes in a nitrogen atmosphere at 850°C.

In the semiconductor device of this embodiment configured as described above,
Diffusion layers 4f, 4g, 4n, 4p, 4q (5m, 5n, 5
s, 5t, 5u), the impurity concentration increases in the order of LDD
The diffusion layer has a five-step concentration gradient immediately after implantation. Therefore, the electric field in the gate length direction becomes gentle, suppressing the generation of hot carriers, and reducing the deterioration of the MOS transistor characteristics over time.

As described above, according to this embodiment, two types of angles between the normal to the semiconductor substrate l and the traveling direction of the incident ion beam are selected, and under each condition, the semiconductor substrate l is centered around the normal to the semiconductor substrate 1. By rotating by 90' and implanting four times, LDD diffusion layers with five types of concentration gradients can be formed.

Figure 2 shows the channel length direction of the LDD diffusion layer formed in the conventional example and the LDD diffusion layer formed in the example when heat treatment after impurity ion implantation was performed for 30 minutes in a nitrogen atmosphere at 850°C. This shows the concentration distribution of arsenic ions.

In the same figure, the broken line shows the concentration distribution of arsenic ions in a conventional example in which impurity ions are implanted only at an angle of 30°, and the solid line shows an example in which impurity ions are implanted at two types of angles: 30° and 45°. shows the concentration distribution of arsenic ions.

As is clear from FIG. 2, compared to the conventional example, in this example, the impurity concentration gradient in the channel length direction becomes gentler, especially under the gate.

Figure 3 shows the LD with the two types of impurity concentration distributions shown in Figure 2.
This is a comparison of the electric field distribution in the channel length direction in a MOS transistor having a D diffusion layer. In the same figure, the broken line shows the electric field distribution in the channel length direction in the conventional example where impurity ions are implanted only at an angle of 30°, and the solid line shows the electric field distribution in the channel length direction.
The electric field distribution in the channel length direction is shown in an embodiment in which impurity ions are implanted at two different angles: 0° and 45°. As is clear from FIG. 3, in this example, the impurity concentration gradient is gentler than in the conventional example, so the electric field is weaker and its distribution is wider under the gate.

Deterioration of transistor characteristics over time occurs when electrons accelerated by the electric field in the channel length direction cause impact ionization, and some of the electrons or holes generated at that time are injected and captured into the gate oxide film, or when the gate oxide film This occurs due to the formation of a level at the interface of the P-type silicon substrate. The number N of electrons and holes generated by impact ionization strongly depends on the electric field in the channel length direction, and is expressed as Noc exp (-b/E) ・--
- (1) E: Electric field in the channel length direction b: Expressed by a constant equation, most of which flows toward the substrate and is observed as a substrate current. However, a small portion is implanted into the gate oxide, and the number is proportional to N. Therefore, there is a strong correlation between the substrate current and the electrons (holes) injected into the gate oxide film, that is, the amount of deterioration of transistor characteristics, and τEX: (1,,b/I,) -... (
2) τ, life lamb: substrate current! , : source-to-train current n: constant. Figure 4 shows this situation.

The characteristics shown in FIG. 4 are when the gate width is 20 μm and the gate length is 1.5 μm. Measurements were made using a czm N-channel MOS transistor with a source-drain voltage of 5V.

Compared to the conventional example, in this example, the substrate current I rub
Since the current is reduced from 25 μA to 22 μA, it is thought that the life span will be extended by about half an order of magnitude.

In the first embodiment, if there are n types of angles between the normal to the semiconductor substrate l and the incident ion beam, the LDD diffusion layer will have (2n+1) types of concentration gradients.
As n becomes larger, the concentration gradient of the LDD diffusion layer can be made gentler. Alternatively, the implantation may be performed while rotating the semiconductor substrate l around the normal line of the semiconductor substrate. Furthermore, the LDD diffusion layer may be formed of phosphorus ions instead of arsenic ions.

FIG. 5 is a process sectional view showing a method of forming an N-type diffusion layer adjacent to an N-channel stopper in a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

The method for manufacturing the semiconductor device of this second embodiment will be described below with reference to FIG.

First, in Fig. 5 fa), 30 mm
After forming a thermal oxide film 6 with a thickness of 150 nm, a silicon nitride film 7 is deposited with a thickness of 150 nm using a well-known vapor phase growth method. Next, the silicon nitride film 7 is etched using a dry etching method using a photoresist as a mask, and then poron ions are etched with an acceleration energy of 100 KeV.
The N-channel stopper diffusion layer 8 is formed by implanting at a dose of 2E13 cm-' as shown by the arrow.

Next, in FIG. 5fb), the oxide film in the portions where the silicon nitride film is not present is selectively grown on the thermal oxide film 6 by pyro-oxidation to form an element isolation oxide film 9 with a thickness of 500 nm.

Next, in FIG. 5 (C1), polycrystalline silicon is deposited to a thickness of 300 nm on a semiconductor substrate l using a well-known vapor phase growth method, and then dry etching is performed using a photoresist as a mask. Etching polycrystalline silicon,
A step IO is formed at the boundary between the element isolation region and the active region. Next, accelerate the arsenic ions with an energy of 40 KeV,
A low concentration N-type diffusion layer 11 is formed by implanting perpendicularly into the semiconductor substrate as shown by the arrow at a dose IE of 13 cm-'.

Next, in FIG. 5(d), the semiconductor substrate l is tilted so that the angle between the normal line of the semiconductor substrate and the implantation beam (indicated by the arrow) is 30 degrees, and the boundary between the element isolation region and the active region is Accelerating arsenic ions in the direction perpendicular to the line with an energy of 65
KeV is implanted at a dose of 5EI4Cm-'' to form an N-type diffusion layer 12.

Next, as shown in FIG. Accelerating arsenic ions in the direction perpendicular to
KeV, injected at t<-sfft5EI5cm-'',
An N-type diffusion layer 13 is formed.

In the semiconductor device of the second embodiment constructed as described above, the impurity concentration increases in the order of diffusion layers II and 12.13, resulting in a three-step concentration gradient.

Figure 6 shows the lateral impurity distribution near the junction between the N-channel stopper and the N-type diffusion layer when the N-type diffusion layer is formed by a single oblique ion implantation at an angle of 30° using the conventional method. N-channels shown by broken lines and formed by a total of three ion implantations: vertical ion implantation and two oblique ion implantations at 30° and 45° angles as in the example. The lateral impurity distribution near the junction of the diffusion layer is shown by a solid line. In the conventional method, an N-type diffusion layer with an impurity concentration on the order of the 20th power and an N-channel stopper, which is a P-type diffusion layer, are in direct contact with each other, or in this embodiment, an N-type diffusion layer with an impurity concentration on the order of the 17th power is in direct contact with each other. Therefore, the electric field distribution near the junction between the N-channel stopper and the N-type diffusion layer becomes gentle.

As described above, according to this embodiment, by selecting three types of angles formed between the normal to the semiconductor substrate 1 and the traveling direction of the incident ion beam and performing ion implantation three times, N A type diffusion layer can be formed, the electric field distribution near the junction between the N-channel stopper and the N-type diffusion layer becomes gentle, and the junction breakdown voltage becomes high.

〔Effect of the invention〕

According to the method for manufacturing a semiconductor device according to claim 11, oblique ion implantation is performed multiple times with different angles formed between the normal line of the semiconductor substrate and the impurity ion incident direction, so that the semiconductor device is formed by implanting impurity ions. By making the concentration gradient of impurities in the diffusion layer gentle, the electric field in that portion can be weakened.

According to the method for manufacturing a semiconductor device according to claim (2), while rotating the semiconductor substrate about the normal line of the semiconductor substrate, the process is performed a plurality of times at different angles formed between the normal line of the semiconductor substrate and the incident direction of impurity ions. MOS by performing oblique ion implantation
Since the diffusion layers that serve as the source and train of the transistor are formed, the concentration gradient of impurities in the diffusion layers that serve as the source and drain can be made gentler, thereby weakening the electric field in those portions, thereby extending the life of the transistor.

According to the method for manufacturing a semiconductor device according to claim (3), a step is formed on an element isolation region provided in a semiconductor substrate, and then a plurality of steps are formed at different angles between the normal line of the semiconductor substrate and the incident direction of impurity ions. Since the diagonal ion implantation is performed twice to form a diffusion layer close to the device isolation region, the impurity concentration gradient in the diffusion layer close to the device isolation region can be made gentler, thereby weakening the electric field in that area. It is possible to increase

[Brief explanation of drawings]

FIG. 1 is a process cross-sectional view showing a method for forming an LDD structure of an N-type MOS transistor in a first embodiment of the present invention;
FIG. 2 is a concentration distribution diagram showing the arsenic concentration distribution in the channel length direction of the N-type MOS transistor in the first embodiment of the present invention, FIG. 3 is an electric field distribution diagram showing the electric field distribution in the channel length direction, and FIG. is a characteristic diagram showing the relationship between maximum substrate current value and hot carrier lifetime in a MOS transistor, and FIG. 5 is a diagram showing the formation of an N-type diffusion layer adjacent to an N-channel stopper of an N-type MOS transistor in a second embodiment of the present invention. 6 is an impurity distribution diagram showing the impurity distribution in the channel length direction, and FIG. 7 is an N-type M
FIG. 3 is a process sectional view showing a conventional example of a method for forming a DD tank structure of an OS transistor. 1...P-type silicon substrate, 2...gate oxide film, 3
...Polycrystalline silicon gate electrode, 4a-4q, 5a-
5u...LDD diffusion layer, 6...thermal oxide film, 7...
Silicon nitride film, 8...N channel stopper, 9...
・Element isolation oxide film, IO...polycrystalline silicon, 11.
1213...N-type diffusion layer (b (C (d)) Figures 1 to 13

Claims (3)

[Claims] (1) A method for manufacturing a semiconductor device, which comprises performing oblique ion implantation multiple times at different angles between the normal line of the semiconductor substrate and the direction of impurity ion incidence into a semiconductor substrate having a step. (2) After forming a gate electrode on a semiconductor substrate, the semiconductor substrate is rotated about the normal line of the semiconductor substrate and rotated multiple times at different angles between the normal line of the semiconductor substrate and the incident direction of impurity ions. 1. A method of manufacturing a semiconductor device, comprising performing oblique ion implantation to form diffusion layers that become a source and a drain of a MOS transistor. (3) After forming an element isolation region on a semiconductor substrate, a step is formed on the element isolation region, and then a plurality of diagonal directions are formed at different angles between the normal line of the semiconductor substrate and the impurity ion incident direction. A method of manufacturing a semiconductor device, comprising forming a diffusion layer close to the element isolation region by performing ion implantation.