JPH05136404A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To obtain a micronized MOS type field-effect transistor which maintains a sufficient power of current drive by balancing reduction of both single channel effect and hot carrier effect even in a low temperature. CONSTITUTION:The following are provided: a first neutral impurity layer 8a from the surface of a semiconductor substrate down to a predetermined depth in a channel region located under a gate electrode 4 sandwiched by source/drain regions 7; and a second neutral impurity layer 8b having a concentration higher than that the first neutral impurity layer 8a so as to surround the source/drain regions except the channel region. Generation of hot carriers is suppressed by dispersion of neutral impurity in the first neutral impurity layer, and diffusion of impurity in the source/drain regions during heat treatment by the second neutral impurity layer.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a MOS (Metal).
The present invention relates to a semiconductor device including an oxide semiconductor type transistor and a method for manufacturing the same, and in particular, by having a neutral impurity layer in a semiconductor substrate,
The present invention relates to a technique for improving the performance and reliability of a MOS transistor.

[0002]

2. Description of the Related Art Conventionally, as a highly reliable MOS type field effect transistor, for example, "IEEE Tra" is used.
nsactions on Electron Dev
ices, ED-27 (1980) p1359 ”and the like, as shown in FIG. 11.
It was common to use the ly Doped Drain) structure. This MOS field effect transistor is
Referring to FIG. 11, gate electrode 4 is patterned on the surface of p well region 2 of semiconductor substrate 1 with gate insulating film 3 interposed. Sidewall spacers 5 and 5 are formed on both left and right side walls of the gate electrode 4, and a low-concentration n-type impurity layer 6 is formed on the surface of the p-well region 2 therebelow.
6 is formed. The low concentration n-type impurity layers 6 and 6
The high-concentration n-type impurity layers 7, 7 are formed in a region outside the gate electrode 4 below. By the way,
The structure shown in FIG. 1 has a problem that a deterioration mode of the current driving ability peculiar to the LDD structure, that is, an increase in parasitic resistance occurs. The cause of this increase in parasitic resistance is that electrons are trapped in the high resistance of the low-concentration n-type impurity layers 6 and 6 themselves and in the sidewall spacers 5 and 5 located above the low-concentration n-type impurity layers 6 and 6. It is due to the effect. Particularly, in the latter mechanism, when electrons are captured by the sidewall spacers 5 and 5 above the low-concentration n-type impurity layers 6 and 6, the electrons in the low-concentration n-type impurity layers 6 and 6 adjacent to the side-wall spacers 5 and 5 repel. That is, the resistance value of the low-concentration n-type impurity layers 6 and 6 is effectively increased, and the current level deteriorates.

As an improved version of this structure, for example, "VLSI SYMPOSIUM 1985 p116".
MLDD (Moderately)
There is a Lightly Doped Drain) structure. This is because when the concentration of the low concentration n-type impurity layers 6 and 6 is such that the substrate current used in the conventional LDD structure becomes the minimum.
By setting the concentration of the type impurities slightly higher, the maximum electric field position can be set closer to the gate electrode 4 side, and the injection and trapping of electrons into the sidewall spacers 5 and 5 can be reduced, thereby suppressing the deterioration mode. Is intended.

As a MOS field effect transistor that more effectively suppresses the deterioration mode, one using a gate overlap type LDD structure as shown in FIG. 12 is disclosed in, for example, "VLSI SYMPOSIUM, 198".
9, p33 ". In this structure, low concentration n
By overlapping the type impurity layers 6 and 6 below the gate electrode 4, the maximum electric field position where hot carriers are generated is moved to directly below the gate electrode 4, and the maximum electric field is relaxed.
This is to prevent the electrons from being trapped in 5.

On the other hand, in a MOS type field effect transistor, neutral impurities such as silicon (Si) and germanium (Ge) are injected before the formation of the impurity layers in the source / drain regions, and as shown in FIG. Forming No. 8 suppresses vertical or horizontal diffusion of n-type impurities in the source / drain regions and suppresses deterioration of characteristics due to the short channel effect.
E Electron Device Letters,
VOL. 9, No. 7, 1988 p343 ". In this document, graphs as shown in FIGS. 14A and 14B are posted as data showing the effect of Ge doping. FIG. 14A shows only phosphorus doping (implantation energy 45 KeV, dose amount 2.5 × 10 ¹⁵ / c).
m ² ) and Ge doping (implantation energy 125 KeV, dose 5.0 × 10 ¹⁵ / cm 2)
The impurity concentration distribution in the depth direction of the semiconductor substrate after annealing at 900 ° C. for 12 minutes is shown for the case where ² ) is added. Further, FIG. 14B shows the effective channel length dependency of the threshold voltage change (ΔV _th ) in each case.

Further, a transistor in which a neutral impurity such as Ge is injected into a channel region or a part thereof is particularly effective in suppressing hot carriers.
EEE Electron Device Letter
rs, VOL. 11, No. 1, 1990 p45 ".

[0007]

The conventional LDD structure is
Since the low-concentration n-type impurity layers 6 and 6 are formed of phosphorus, which is an impurity with a large diffusion coefficient, the concentration gradient becomes gentle and the electric field relaxation effect is large, but the short-channel effect is more remarkable in the miniaturized transistor. There was a problem that there was. That is, the threshold voltage (V _th ) of the transistor
Occurs as the channel length (L) becomes smaller. When the actually used channel length (L) is in the region where this V _th drop phenomenon occurs, the sharper the drop, the more the channel length manufacturing variation causes the transistor characteristics to fluctuate greatly.
Significantly reduce performance yield. Therefore, if we try to reduce the injection amount of phosphorus in order to suppress the short channel effect,
There is also a problem that the resistance (parasitic resistance) of the low-concentration n-type impurity layers 6 and 6 is increased, resulting in deterioration of current driving capability.

Even in the overlap type LDD structure described above, the concentration of the low concentration n-type impurity layer formed of phosphorus cannot be increased so much as to suppress the short channel effect. Therefore, an attempt to form the low-concentration n-type impurity layer with arsenic having a small diffusion coefficient can be considered, whereby the phenomenon of dropping V _th can be significantly improved and the parasitic resistance can be reduced as compared with the case of phosphorus. However, arsenic having a small diffusion coefficient cannot form a sufficient concentration gradient and the electric field relaxation effect is not sufficient, so that it is difficult to sufficiently reduce the substrate current due to hot carriers.

In each of the conventional LDD structures, the generation rate of hot carriers is suppressed by the effect of the relaxed electric field, but at low temperatures, phonon scattering is reduced and the generation rate of hot carriers increases again. come. Therefore, there is a problem that the hot carrier characteristics are still deteriorated.

A single drain transistor in which a neutral impurity such as Ge is injected into a channel region or a part thereof has an effect of suppressing hot carriers, but the effect is about a fraction of the effect of the LDD structure. There is a limit to reducing the hot carrier effect of a submicron level transistor by using only neutral impurities such as Ge.

Further, the Ge implantation amount for suppressing such a short channel effect needs to be about 10 ¹⁹ to 10 ²⁰ / cm ^3, and a channel region of such a high concentration of neutral impurities is required. Implantation causes defects or stress in the channel region, which has a great influence on the transistor characteristics. That is, the optimum injection amount for suppressing the vertical or horizontal diffusion of the n-type impurities in the source / drain regions and suppressing the short channel effect, and the optimum injection amount for injecting into the channel region for suppressing the hot carriers. However, there is a problem that the optimum conditions cannot be satisfied by one injection.

The present invention has been made to solve the problems of both the LDD structure transistor and the Ge carrier injection transistor for hot carrier resistance as described above, and can reduce both the single channel effect and the hot carrier effect. An object of the present invention is to obtain a miniaturized transistor having balanced high performance and high reliability, and to obtain a miniaturized semiconductor device which reduces a hot carrier effect while sufficiently maintaining a current driving capability even at a low temperature. ..

[0013]

In order to solve the above-mentioned problems, a semiconductor device of the present invention comprises a first conductivity type semiconductor substrate having a main surface and a gate insulating film formed on the main surface of the semiconductor substrate. It includes a MOS field effect transistor having a gate electrode and a source / drain region formed of an impurity layer of the second conductivity type, which is formed from the vicinity immediately below the left and right side walls of the gate electrode to the outside. This semiconductor device is characterized by neutral impurities that do not act as any conductivity type so as to surround the lower side of the source / drain region except for the channel region located immediately below the gate electrode sandwiched between the source / drain regions. It has a neutral impurity layer formed by implanting.

It is preferable that the channel region further includes a neutral impurity region having a concentration lower than that of the neutral impurity region, extending from the main surface of the semiconductor substrate to a predetermined depth.

The neutral impurity layer surrounding the source / drain regions has a G concentration of 10 ¹⁹ to 10 ²⁰ / cm ^3.
The neutral impurity layer containing e and having a lower concentration is 10 ¹⁶ to 1
Preferably it contains 0 ^{1 9} / cm ³ concentration of Ge.

In the first neutral impurity layer of the semiconductor device having the above structure, before forming the gate insulating film and the gate electrode, the entire surface of the semiconductor substrate is irradiated with neutral impurities from the surface to a predetermined depth. Is formed by
Then, after the gate electrode is patterned, the second neutral impurity layer is formed by irradiating the surface of the semiconductor substrate with neutral impurities from a direction forming a predetermined tilt angle with the gate electrode as a mask. Next, by using the gate electrode alone or both the gate electrode and the sidewall spacer formed thereon as a mask, the second conductivity type impurity is implanted into the surface of the semiconductor substrate from a predetermined direction to form the source / drain regions. To form.

[0017]

According to the structure of the semiconductor device of the present invention, the source / source
Since the lower side of the drain region is surrounded by the neutral impurity layer, the diffusion of the second conductivity type impurity layer is suppressed, and the decrease in the threshold voltage due to the shortening of the channel can be suppressed. This is because the neutral impurities injected in a sufficiently high concentration make the silicon single crystal or the like constituting the semiconductor substrate amorphous and suppress the channeling during the implantation of the second conductivity type impurities or the diffusion during the heat treatment. Is.

On the other hand, if the diffusion of impurities in the second-conductivity-type impurity layer is suppressed, the concentration gradient in the vicinity of the channel becomes steeper, and the electric field relaxation effect is weakened. In the preferred embodiment of the present invention, the lower-concentration neutral impurity layer additionally doped in the channel region where hot carriers are generated has a weakening effect of the hot carrier suppression effect by an effect different from the electric field relaxation effect. It is to reinforce. That is, the neutral impurities are additionally introduced into the channel region by the neutral impurities, so that the energy is taken from the hot carriers by the scattering of the hot carriers and the bias of the scattering angle of the hot carriers passing through to the oxide film is prevented. Occurrence is suppressed. In particular, it has been reported that, when Ge is used as the neutral impurity, this neutral impurity scattering occurs with a high probability for hot carriers having a relatively long mean free process as compared with the mean free process of the majority of channel carriers. ing. Therefore, the neutral impurities themselves hardly reduce the current driving ability.

Further, the concentration of the neutral impurity layer additionally formed in the channel region should be such that stress is not generated in that region and the transistor characteristics are not significantly affected. 2 is set to an appropriate concentration lower than that of the neutral impurity layer.

Further, generally, the scattering due to neutral impurities has no temperature dependence, and even if the phonon scattering is suppressed and the average energy of the channel carrier is increased after the low temperature operation, the effect still remains effective and the hot carrier It has the effect of suppressing the generation.

In order to effectively generate the above-mentioned effects, the neutral impurity layer surrounding the source / drain regions contains Ge at a concentration of 10 ¹⁹ to 10 ²⁰ / cm ³ , and the channel region contains Ge. The additionally formed neutral impurity layer preferably contains Ge at a concentration of 10 ¹⁶ to 10 ¹⁹ .

In the method of manufacturing a semiconductor device of the present invention,
The first neutral impurity layer is formed by first irradiating the surface of the semiconductor substrate before forming the gate insulating film and the gate electrode with the neutral impurity, to form the first neutral impurity layer in the channel region after forming the gate insulating film. This is because the implantation of Al causes damage to the gate insulating film.

[0023]

EXAMPLE A semiconductor device according to a first example of the present invention will be described below with reference to FIG. The semiconductor device shown in FIG. 1 is an nMO having a gate overlap type LDD structure.
The present invention is applied to an S-type field effect transistor. Referring to FIG. 1, a gate electrode 4 is patterned with a gate insulating film 3 interposed on the surface of a p-well 2 formed on a semiconductor substrate 1 made of silicon single crystal or the like. Low-concentration n-type impurity layers 6 and 6 are formed from the surface of the p-well 2 to a predetermined depth so as to overlap the gate electrode 4 by implanting phosphorus ions. Adjacent to the low-concentration n-type impurity layers 6 and 6, high-concentration n-type impurity layers 7 and 7 in which arsenic ions and the like are implanted are formed from directly below the left and right side walls of the gate electrode 4 to the outside. A high concentration n is formed on the right and left side walls of the gate electrode 4.
Sidewall spacers 5 and 5 serving as masks when implanting arsenic or the like of the type impurity layers 7 and 7 are formed. Further, the low-concentration n-type impurity layers 6 and 6 and the high-concentration n-type impurity layers 7 and 7 are doped with germanium of 10 ¹⁹ to 10 ²⁰ / cm ³ except for the channel region directly below the center of the gate electrode 4. It is surrounded by the second neutral impurity layer 8b. Furthermore, in the channel region sandwiched by the low-concentration n-type impurity layers 6 and 6, 0.1 μm from the surface of the p well 2
Toward the degree of depth, the first neutral impurity layer 8a doped with germanium ^{10 1 6 ~10 1 9 / cm} 3 is formed.

In the semiconductor device including the MOS transistor of the first embodiment described above, the low-concentration n-type impurity layers 6, 6 and the low-concentration n-type impurity layers 6, 6 of the LDD structure are kept low. Since the high-concentration n-type impurity layers 7 and 7 are surrounded by the second neutral impurity layer 8b,
Sudden drop of the threshold voltage of the transistor due to the effect of suppressing the phosphorus ion channeling and diffusion due to the high concentration of neutral elements while maintaining the current drive capability firmly by suppressing the parasitic resistance of the impurity layer The short channel effect of can be suppressed. The graph shown in FIG. 10 compares the effect of the present invention with the channel length dependency of the threshold voltage in the case of the embodiment shown in FIG. 1 and in the case of the conventional gate overlap type LDD transistor shown in FIG. It is shown.

On the other hand, the effect of suppressing the diffusion of the impurity concentration of the low-concentration n-type impurity layers 6 and 6 is, in the LDD structure,
It acts in the direction of abruptly changing the concentration gradient, and the electric field relaxation effect is somewhat weakened. In addition to the channel region where hot carriers are generated, the first neutral impurity layer 8a formed by implanting Ge at a concentration lower than that of the second neutral impurity layer 8b has a weakened effect of suppressing hot carriers. The component is reinforced by an effect different from the electric field relaxation effect. That is, the generation of hot carriers is caused by the effect of absorbing the energy from the hot carriers and preventing the scattering of the scattering angle of the hot carriers leaking to the oxide film due to the scattering of the neutral impurities additionally introduced into the channel region by the Ge element. It is suppressed and reliability is improved. Neutral impurity scattering due to the Ge element occurs with a high probability for hot carriers in a relatively long mean free path, as compared with the mean free path of channel carriers that occupy the majority. Therefore, the Ge element itself hardly lowers the current driving ability. In addition, G of the first neutral impurity layer 8a
The e concentration is made lower than that of the second neutral impurity layer 8b,
This is because stress is not generated on the surface of the semiconductor substrate 1 in the vicinity of the channel so that the transistor characteristics are not significantly changed.

In general, scattering due to neutral impurities is
Even if the average energy of the channel carrier, which has no temperature dependence and suppresses phonon scattering under low temperature operation, increases, it still works effectively and has an effect of suppressing the generation of hot carriers.

Next, a method of manufacturing the semiconductor device of this embodiment will be described with reference to FIGS.

In this embodiment, first, the semiconductor substrate 1
Ge as a neutral impurity is irradiated on the entire surface of the region of the p-well 2 in a concentration of 10 ¹⁶ to 10 ¹⁹ / cm ^{3 over} a depth of about 0.1 μm from the surface of the p-well 2. Forming an impurity layer 8a (FIG. 2).

Next, a gate insulating film 3 is formed on the surface of the p well 2 in which the first neutral impurity layer 8a is formed by a thermal oxidation method, and a polycrystalline silicon layer or the like having a predetermined thickness is further formed thereon. After forming the conductive layer, patterning is performed by photolithography and etching to form the gate electrode 4 (FIG. 3).

Next, while rotating the semiconductor substrate 1 in a plane parallel to the surface of the p-well 2 using the gate electrode 4 as a mask, the surface of the p-well 2 is centered at a direction of, for example, about 45 °. Ge as a conductive impurity is irradiated and the concentration becomes 1 from the surface of the p-well 2 to a predetermined depth.
A second neutral impurity layer 8b of ^{0 19} to 10 ²⁰ / cm ³ is formed (FIG. 4).

Next, with the gate electrode 4 used as a mask, the semiconductor substrate 1 is rotated in a plane parallel to the surface of the semiconductor substrate 1, and the surface of the semiconductor substrate 1 is, for example, 45 °.
Is irradiated with an n-type impurity such as phosphorus from a direction forming a predetermined inclination angle such as to form the low-concentration n-type impurity layers 6 and 6 in the region inside the second neutral impurity layer 8b (FIG. 5). ).

Next, a silicon oxide film is deposited to a predetermined thickness on the entire surface of the semiconductor substrate 1 by a CVD method or the like, and anisotropic etching is applied to the left and right side walls of the gate electrode 4 so that side walls having a predetermined width are formed. Wall spacers 5 and 5 are formed (FIG. 6). After that, while using the side wall spacers 5 and 5 and the gate electrode 4 as a mask, the semiconductor substrate 1 is rotated in a plane parallel to the surface of the semiconductor substrate 1 from a direction that forms a predetermined inclination angle with respect to the surface of the semiconductor substrate 1. N-type impurities such as ions are implanted to form high-concentration n-type impurity layers 7 and 7 inside the region of the second neutral impurity layer 8b (FIG. 7).

In the manufacturing process of this embodiment, the Ge element is implanted into the surface of the p well 2 to form the first neutral impurity layer before the gate insulating film and the gate electrode are formed. The reason is that if Ge is implanted after the gate insulating film is formed, the gate insulating film is damaged.

Next, a second embodiment of the present invention will be described. In this embodiment, as shown in FIG. 9, the source / drain regions have a triple LDD structure. That is, the neutral impurity layers 9 and 9 and the high-concentration n-type impurity layers 10 and 10 adjacent to the neutral impurity layers 9 and 9 are formed in the regions of the high-concentration n-type impurity regions 7 and 7 in the first embodiment. By applying this triple structure, it is possible to effectively suppress the short channel effect.
The effects of the LDD structure transistor having the triple structure have already been reported in various documents.

In the method of manufacturing the semiconductor device of the second embodiment shown in FIG. 9, the steps of FIGS.
This embodiment is the same as the first embodiment, and only the subsequent source / drain region forming process is different. That is, after forming the sidewall spacers 5 and 5, an n-type impurity such as phosphorus or arsenic is obliquely rotated and ion-implanted at a dose lower than that of the step shown in FIG. 7 in the first embodiment. Concentration n-type impurity layers 9 and 9 are formed (FIG. 8).

Next, an n-type impurity such as arsenic is irradiated from a direction perpendicular to the surface of the semiconductor substrate 1 and is injected into the surface of the p-well 2 by using the sidewall spacers 5 and 5 and the gate electrode 4 as a mask to increase the height. Concentration n-type impurity layer 1
0 and 10 are formed, and the structure shown in FIG. 9 is completed.

In each of the above embodiments, the first neutral impurity layer 8a is formed over the entire channel region. However, for example, only in the region near the drain region where the electric field is maximum, a part of the channel region is formed. By forming the same, the same operational effect can be achieved.

In the formation of the second medium-concentration impurity layers 8b, 8b and the low-concentration n-type impurity layers 6, 6, etc., when impurities are implanted from a direction inclined at a predetermined angle with respect to the surface of the semiconductor substrate 1, Although the semiconductor substrate 1 was rotated in a plane parallel to the surface thereof, with the semiconductor substrate 1 stationary, the irradiation direction of impurities was changed from diagonally above one side wall of the gate electrode 4 to the other side wall. A desired impurity layer can also be obtained by injecting impurities from the diagonally upper side for the same time.

Next, a semiconductor device according to a third embodiment of the present invention and a method of manufacturing the same will be described with reference to FIGS.

In this embodiment, the present invention is applied to a transistor having a single source / drain structure. As shown in FIG. 15, the semiconductor device of this example has substantially the same structure as that shown in FIG. 1 except that the low concentration n-type impurity layer 6 does not exist in the source / drain regions. Therefore, detailed description of the structure is omitted.

Although the structure of this embodiment does not have the effect of suppressing the generation of hot carriers due to the electric field relaxation effect, it has a higher concentration of the n-type impurity layers 7 and 7 than the conventional single source / drain structure transistor. Thermal diffusion is suppressed, and the short channel effect can be suppressed.
Further, the first neutral impurity layer 8a formed in the channel region
Has the effect of suppressing the generation of hot carriers by the same operation as described above with reference to FIG.

The semiconductor device of this embodiment is shown in FIG.
Through the steps shown in FIG. First, with reference to FIG. 16, Ge as a neutral impurity is implanted into the entire surface of the region of p well 2 of semiconductor substrate 1 to reach a depth of about 0.1 μm from the surface of p well 2 for 10 ^{1 6} ~
A ^first neutral impurity layer 8a having a concentration of 10 ¹⁹ / cm ³ is formed. Next, referring to FIG. 17, a gate insulating film 3 is formed on the surface of the p well 2 in which the first neutral impurity layer 8a is formed by a thermal oxidation method, and polycrystalline silicon having a predetermined thickness is further formed thereon. After forming a conductive layer including layers, patterning is performed by a photolithography technique and etching to form the gate electrode 4. Up to this point, the first
The manufacturing process of this embodiment is the same as the process described with reference to FIGS.

Then, referring to FIG. 18, Ge as a neutral impurity is implanted perpendicularly to the surface of p well 2 using gate electrode 4 as a mask, and a predetermined depth is formed from the surface of p well 2. Then, the second neutral impurity layers 8b and 8b are formed. After that, an insulating film layer having a predetermined thickness is formed on the entire surface of the semiconductor substrate 1 including the outer surface of the gate electrode 4, and anisotropic etching is further performed to form sidewall spacers 5 and 5 as shown in FIG. To do.

Next, referring to FIG. 20, using the gate electrode 4 and the sidewall spacers 5 and 5 as a mask, n
Injecting phosphorus, which is a type impurity, from the surface of the p-well 2 to a depth shallower than the second neutral impurity layers 8b and 8b,
High-concentration n-type impurity layers 7 and 7 to be source / drain regions
To form. Then, a heat treatment for activating the impurities is performed to complete the single source / drain transistor having the structure shown in FIG.

According to the manufacturing method of this embodiment, a single source / drain structure transistor to which the present invention is applied can be formed in a relatively simple process by only vertical implantation without using oblique implantation. ..

Next, a typical application example of the semiconductor device of the present invention to a device will be described with reference to FIG. FIG. 21 shows a DRAM (Dynamic Random).
A structure in which the present invention is applied to a memory cell of Access Memory is shown.

The memory cell is formed on the surface of the p-well 2 of the semiconductor substrate 1 on the active region separated by the field insulating film 16.
It is composed of a DD transistor and a capacitor. LD
The D transistor includes a gate electrode 4 serving as a word line, low concentration n-type impurity layers 6 and 6 serving as source / drain regions, and high concentration n-type impurity layers 7 and 7, and further includes the first
Similar to the first embodiment, it has a first neutral impurity layer 8a and a second neutral impurity layer 8b. The lower electrode 11 of the capacitor is connected on the surface of the high-concentration n-type impurity layer 7 on the right side, and the upper electrode 13 is formed on the lower electrode 11 with the dielectric layer 12 interposed therebetween. An interlayer insulating film 14 is formed on the gate electrode 4 and the upper electrode 13, and a bit line 15 made of a conductive layer such as aluminum is formed on the surface thereof. The bit line 15 is connected to the surface of the left high-concentration n-type impurity layer 7 through a contact hole formed in the interlayer insulating film 14.

As described above, by applying the LDD transistor according to the present invention to a memory cell of a DRAM, intrusion of hot carriers into the capacitor due to the short channel effect is prevented, and a memory having good characteristics with no soft error. A cell can be realized.

[0049]

As described above, according to the present invention, by additionally implanting one type of concentration of neutral impurities, a high performance that balances the reduction of the short channel effect and the reduction of the hot carrier effect is achieved. Further, a miniaturized transistor having high reliability can be obtained. Further, even at a low temperature, it is possible to obtain the effect of reducing the hot carrier effect while sufficiently maintaining the current driving capability.

[Brief description of drawings]

FIG. 1 is a diagram showing a cross-sectional structure of a gate overlap type LDD transistor according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a first step of the method for manufacturing the semiconductor device of the embodiment shown in FIG.

3 is a cross-sectional view showing a second step of the method for manufacturing the semiconductor device of the embodiment shown in FIG.

FIG. 4 is a cross-sectional view showing a third step of the method for manufacturing the semiconductor device of the embodiment shown in FIG.

5 is a cross-sectional view showing a fourth step of the method for manufacturing the semiconductor device of the embodiment shown in FIG.

6 is a sectional view showing a fifth step of the method for manufacturing the semiconductor device of the embodiment shown in FIG.

FIG. 7 is a cross-sectional view showing a sixth step of the method for manufacturing the semiconductor device of the embodiment shown in FIG. 1.

FIG. 8 is a cross-sectional view showing a step of forming a medium-concentration n-type impurity layer in a method of manufacturing a gate overlap LDD transistor according to a second embodiment of the present invention.

FIG. 9 is a cross-sectional view showing a step of forming a high-concentration n-type impurity layer in the method of manufacturing a gate overlap LDD transistor according to the second embodiment of the present invention.

FIG. 10 is a graph showing the relationship between the threshold voltage and the channel length of the conventional gate overlap type LDD transistor and the gate overlap type LDD transistor in the first embodiment of the present invention.

FIG. 11 is a conventional non-gate overlap type L
It is a figure which shows the cross-section of the MOS field effect transistor which has DD structure.

FIG. 12 is a diagram showing a cross-sectional structure of a conventional gate overlap type LDD structure MOS field effect transistor.

FIG. 13 is a diagram showing a cross-sectional structure of a conventional gate overlap type LDD structure MOS field effect transistor in which a characteristic of a single channel effect is obtained by implanting a neutral impurity such as Si or Ge.

14 (a) is a diagram of the conventional gate overlap LDD structure transistor shown in FIG. 12 and FIG.
The figure which shows the simulation result and the experimental data of the impurity diffusion of the depth direction from a substrate surface, (b) is a figure which showed the effective channel length dependence of both threshold voltages.

FIG. 15 is a sectional view showing the structure of a semiconductor device according to a third embodiment of the present invention.

FIG. 16 is a sectional view showing a first step of a method for manufacturing a semiconductor device according to the third embodiment of the present invention.

FIG. 17 is a cross-sectional view showing the second step.

FIG. 18 is a cross-sectional view showing the same third step.

FIG. 19 is a cross-sectional view showing the same as the fourth step.

FIG. 20 is a cross-sectional view showing the fifth step.

FIG. 21 is a DRAM to which the first embodiment of the present invention is applied.
3 is a cross-sectional view showing the structure of the memory cell of FIG.

[Explanation of symbols]

1 semiconductor substrate 2 p well 3 gate insulating film 4 gate electrode 5 sidewall spacer 6 low concentration n-type impurity layer 7 high concentration n-type impurity layer 8a first neutral impurity layer 8b second neutral impurity layer In the figure, the parts with the same numbers indicate the same or corresponding elements.

Claims (4)

[Claims] 1. A first-conductivity-type semiconductor substrate having a main surface, a gate electrode formed on the main surface of the semiconductor substrate surface via a gate insulating film, and immediately below both left and right side walls of the gate electrode. In a semiconductor device including a MOS transistor having a source / drain region formed of a second conductivity type impurity diffusion layer formed from the vicinity to the outside, a channel sandwiched by the source / drain region immediately below the gate electrode. Neutral formed by implanting a neutral impurity that does not act as either the first conductivity type or the second conductivity type so as to surround the lower part of the source / drain region except the region. A semiconductor device having an impurity layer. 2. A neutral impurity layer having a concentration lower than that of the neutral impurity layer formed in the channel region to a predetermined depth from the main surface of the semiconductor substrate. Semiconductor device. 3. The neutral impurity layer surrounding the lower part of the source / drain regions is 10 ¹⁹ to 10 ²⁰ / cm ^3.
And the low concentration neutral impurity layer contains 1
The semiconductor device according to claim 2, wherein Ge is contained in a concentration of 0 ¹⁶ to 10 ¹⁹ / cm ³ . 4. A neutral impurity is implanted into at least a channel region of a semiconductor substrate having a region of the first conductivity type at least to a predetermined depth from the surface, and a predetermined concentration is provided from the surface of the semiconductor substrate to a predetermined depth. Forming a first neutral impurity layer, and forming a gate electrode having a predetermined pattern on the surface of the semiconductor substrate with a gate insulating film interposed therebetween, and using the gate electrode as a mask, the surface of the semiconductor substrate Forming a second neutral impurity layer at a predetermined concentration from the surface of the semiconductor substrate to a predetermined depth except for the channel region below the gate electrode, and injecting a neutral impurity into the gate electrode. Forming sidewall spacers of a predetermined thickness on both left and right side walls of the second conductive layer, and using the gate electrode and the sidewall spacers as a mask Impurities are implanted into the semiconductor substrate surface, inside of the second neutral impurity layer, said second predetermined concentration of the semiconductor substrate surface to a prescribed depth
And a step of forming a conductivity type impurity layer.