JPS63215075A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable a semiconductor integrated circuit to be provided with high integration, high velocity and high reliability by a method wherein an LDD regions are formed to form a transistor structure taking symmetrical shape without forming a side-wall. CONSTITUTION:A gate insulating film 2 is formed on the surface of a semiconductor substrate 1 and then a polysilicon film is formed while a gate electrode 3 is formed by patterning out of resist. First, ion is implanted using the gate electrode 3 as a mask to form the first source region 5a and a drain region 5d. Second, in order to form the proper source 4s and drain 4d region (n<+> layer), the second source region 4s and drain region 4d as well as an n-MOSLDDFET are formed by the spin-implanting process similar to that forming the first source/drain region. Finally, the whole body is heat treated to form the LDD structured source/drain region taking the shape symmetrical to the gate electrode 3.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method of manufacturing a semiconductor integrated circuit device with high density, high speed, and high reliability.

2. Description of the Related Art In a conventional method for manufacturing MO5O5 type transistors, in order to obtain high reliability with respect to drain breakdown voltage, etc., after forming a gate electrode, impurity ions at a low concentration are implanted using the gate electrode as a mask. forming a drain region and forming a sidewall on a side surface of the gate electrode;
By performing high-concentration ion implantation using the gate electrode and sidewalls as masks, second source and drain regions are formed, and LDD (Lightly
An MO5 transistor having a doped drain structure was formed. [For example, Paul J, Ts
ang etal.

' Fabrication of High-perform
romanceLDDFET's with 0xi
de Sidevrall-3pacerTechno
logy,'IEICE TRANSACTIONS
0NICIJCTRON DKVICKS (Five Actions on Electron Devices).

VOL ID-29, No. 4, APRIL 1
9B2) Below is an example of the process flow from n to M.
O3LDD (Lightly Doped Drai
n) The formation method of FICτ is shown in Figure 2 (IL) to (g).
Explain using.

First, an insulating film and a gate oxide film 22 are formed on a P-type semiconductor substrate 21 by an element isolation process, and then a polysilicon film 23 and a 10th G V D-8in2 film 24 are formed (FIG. 2(a)). After patterning the gate electrode 23 & on the CVD-5i02 film 24 with resist, reactive ion etching (RIIC) Ic, t CV
D-5in. Etch the film 24. Said CVD-
RI the polysilicon 23 using the 5in2 film 24 as a mask.
A gate electrode 232L is formed by etching according to the etching method (FIG. 2(b)).

Next, in order to form a low concentration region 25 (in this case, an n-layer) about 10 -2 to 10 times as large as the original source/drain region, low concentration ion implantation (in this case, phosphorus) is performed using the gate electrode 23 & as a mask. (Figure 2 (C)).

After this, in the second (7) CVD-sio to form the film 26 (Fig. 2(d)), the cVD-3in2 film 26 is subjected to RI.
The fc-2 (7) CVD-5in2 film 26 formed on the flat portion without anisotropic etching is removed (FIG. 2(e)). Through this step, side walls 26 of the CVD-8iO□ film are formed around the gate electrode.

Next, in order to form the original source/drain region (n+ layer) 27, high-concentration ion implantation (here, arsenic) is performed using the gate electrode having the sidewall as a mask (see FIG. 2 (W). At this time, Side wall 2 made of the cvn-3iO2 film
6 prevents ion implantation into the semiconductor substrate surface, causing the source/
A low concentration region 25 is left between the drain region (n+ layer) 27 and the channel. Finally, heat treatment is performed to form an n-ch LDD structure MO5FET as shown in FIG.

As mentioned above, in the conventional MO5 type transistor,
By adopting a structure having an LDD region, the low concentration region 25 plays a role of relaxing the drain electric field, and high reliability with respect to drain breakdown voltage and the like can be obtained.

Problems to be Solved by the Invention However, in the above manufacturing method, the number of steps for forming the sidewall 26 (hereinafter referred to as sidewall) is increased, which not only complicates the process steps, but also increases the number of steps required to form the sidewall 26 (hereinafter referred to as sidewall). The problem was that it was difficult to control the width.

Furthermore, in the process of forming the source/drain regions, in order to avoid the channeling effect of impurities during ion implantation, ions are offset by setting a certain tilt angle (generally around 7 films) with respect to the vertical direction of the semiconductor substrate surface. Perform the injection. Therefore, when ion implantation is performed from the drain/(or source) side to the gate electrode 23&, the portion of the source (or drain) region on the opposite side adjacent to the gate electrode becomes a shadow, and no impurity is implanted. This has the problem that asymmetry occurs in transistor characteristics depending on the direction of the source/drain.

In view of the above, an object of the present invention is to provide a method for manufacturing a semiconductor device in which an LDD region can be formed without forming the sidewall 26, and a transistor structure can be formed in a symmetrical shape.

Means for Solving the Problems The present invention uses a gate electrode formed on a semiconductor substrate as a mask to perform ion implantation evenly while tilting with respect to the surface of the semiconductor substrate and rotating about the center of the semiconductor substrate. and a step of forming second source and drain regions with different impurities and ion implantation conditions in the same manner as the first source and drain regions. This is a method for manufacturing a semiconductor device.

Effect of the Invention The present invention uses the above-described manufacturing method, which does not require an extra process to form sidewalls, which not only simplifies the process of forming the LDD region, but also eliminates the need to control the sidewall width, which reduces the channel length of the gate electrode. The length in the direction can be determined only by the width of the polysilicon.

However, since ions are uniformly implanted from an oblique direction into the source and drain regions of conventional semiconductor devices, the impurity distribution in the source and drain regions can be formed symmetrically with respect to the gate electrode, and the transistor characteristics are also similar to those of the source and drain. It is possible to develop semiconductor devices that have symmetry regardless of orientation, and it is possible to increase the density, speed, and reliability of semiconductor integrated circuits.

Embodiment FIG. 1 shows a process flow of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
It is related to T.

First, a gate insulating film 2 is formed on the surface of a semiconductor substrate (here, PfiSi) 1, a polysilicon film is formed, and a pattern is formed using a resist to form a gate electrode 3 (FIG. 1(a)).

Next, ion implantation is performed using the gate electrode 3 as a mask to form a first source region 5s and a drain region 5d (here, phosphorus (P) having a large diffusion constant is implanted as an impurity to form a single layer). Figure (b)). Here, the phosphorus (P) ion implantation angle is set at θ1 with respect to the normal to the semiconductor substrate surface in order to prevent the channeling effect of impurities.
Drive at an angle (20 degrees here). At this time, the desired impurity ion implantation amount is achieved while rotating the semiconductor substrate 1 about its center (FIG. 1(C)).

Next, in order to form the original source 4S and drain 4d regions (n+ layer), the same rotational implantation process as in the formation of the first source/drain region (FIG. 1(b)) is performed, and the second source 4S and drain 4d regions (n+ layer) are formed. The first region 4g and drain region 4d are formed.
Figure (d)), form n-MO5LDDFKT (first
Finally, heat treatment is performed to form a mace/drain region having an LDD structure symmetrical to the gate electrode 3 as shown in FIG. 1 (0).

Particularly for the formation of the second source/drain regions, arsenic, which has a smaller diffusion constant than phosphorus, is used as an impurity.

This is done at the ion implantation angle θ1 when forming the n single layer in order to reduce the amount of arsenic that enters the channel region under the gate insulating film 2 and to prevent the channeling effect during implantation.
The ion implantation angle θ2 is smaller than that (7° here).
Use.

As described above, according to this embodiment, the LDD structure source and drain regions can be formed without forming sidewalls, and furthermore, they can be formed symmetrically with respect to the gate electrode 3. Therefore, while simplifying the process, the LD
The drain breakdown voltage can be improved by the D structure, and the transistor characteristics can also be symmetrical regardless of the direction of the source or drain.

As described in detail, according to the present invention, an LDD structure MOS transistor can be formed without a sidewall forming process, and the source and drain regions can be formed symmetrically with respect to the gate electrode. It can be done, and its practical effects are great.

[Brief explanation of the drawing]

FIG. 1 is a process diagram of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a process diagram of a conventional semiconductor device. 1...P-type Si substrate, 2...gate insulating film, 3...gate electrode, 4g, 4d...
...Second source. Drain region, 53.5 (1...First source, drain region. Name of agent: Patent attorney Toshio Nakao and 1 other person 1st)
Figure 3 Kateden Oh! Figure 1, 5. , > ct ＼ ゝN
Go to N5

Claims (3)

[Claims] (1) A step of forming a gate electrode on a gate insulating film formed on a portion of the surface of the semiconductor substrate that will become a MOS type transistor region, and using the gate electrode as a mask and tilting the semiconductor substrate with respect to the surface of the semiconductor substrate. A step of uniformly implanting ions while rotating around the center to form a first source and drain region, and a step of forming a second source and drain region with different impurities and ion implantation conditions using the same method as the first source and drain region. 1. A method of manufacturing a semiconductor device, comprising the step of forming source and drain regions. (2) A diffusion constant of impurities forming the first source and drain regions is larger than a diffusion constant of impurities forming the second source and drain regions. A method for manufacturing a semiconductor device. (3) The ion implantation angle in the step of forming the first source and drain regions is larger than the ion implantation angle in the step of forming the second source and drain regions. A method for manufacturing a semiconductor device according to item 1 or 2.