JPH06350040A - Manufacture of transistor - Google Patents

Abstract

PURPOSE:To reduce manufacturing cost by decreasing lithographic processes when transistors having different threshold voltage are formed on the same substrate. CONSTITUTION:Transistors having different threshold voltage are formed by the presence of a pocket diffusion layer in the manufacture of the transistor, first and second gate electrodes 22, 32 are formed to each of first and second transistor forming regions 12, 13 on a semiconductor substrate 11, and a mask pattern 16, in which the upper section of a region separated from the second gate electrode 32 in specified width (b), is formed. Impurities 41 shaping a pocket diffusion layer are introduced into the first transistor forming region 12 while using the first gate electrode 22 as a mask through an oblique ion implantation method. The introduction of impurities 41 into the semiconductor substrate 11 in a specified region (s) from the second gate electrode 32 is prevented by the mask pattern 16 and the second gate electrode 32 at that time. Impurities (not shown) forming an LDD diffusion layer are introduced by using the mask patter 16.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a transistor in which transistors having different threshold voltages are formed on the same substrate.

[0002]

2. Description of the Related Art The threshold voltage (V
th) is normally set to 0.5V to 0.8V.
Further, the MOS transistor tends to have a lower voltage than that at present. Therefore, it is necessary to reduce the threshold voltage of the MOS transistor in order to reduce the voltage.

Therefore, in order to form transistors having different threshold voltages, ion implantation for forming a channel is performed after forming an ion implantation mask for each transistor. The method will be described with reference to the manufacturing process diagram shown in FIG.

As shown in FIG. 5A, the semiconductor substrate 7
In FIG. 1, an element isolation region 74 that divides the transistor formation regions 72 and 73 is formed. First, a conductive impurity 91 is introduced into the semiconductor substrate 71 in both transistor formation regions 72 by the ion implantation method. The dose amount at that time is adjusted when forming a channel region having a normal concentration.

Next, as shown in FIG. 5B, an ion implantation mask 75 is formed on the semiconductor substrate 71 so as to cover the transistor formation region 72 forming the channel region of normal concentration by the coating technique and the lithography technique. To form. Then, by the ion implantation method, a conductivity type impurity 92 for reducing the surface concentration is introduced into the semiconductor substrate 71 in the transistor formation region 73 forming the low concentration channel region. Then, the ion implantation mask 75 is removed. In this way, the transistor formation region 72 becomes a normal concentration channel region and the transistor formation region 73 becomes a low concentration channel region.

Although not shown in the figure, the subsequent annealing process activates the region into which the conductivity type impurity has been introduced to form a channel region. Then, a normal LDD diffusion layer formation, gate insulation film formation, gate electrode formation, source / drain region formation, and other processes are performed to form a transistor having a desired threshold voltage.

[0007]

As described above, in order to form a low-concentration transistor formation region, a photolithography process is performed to form an ion implantation mask covering the normal-concentration transistor formation region, and then a low concentration transistor formation region is formed. Since the ion implantation for forming the transistor formation region of high concentration is performed, a photolithography process using a mask is required. Therefore, the manufacturing cost becomes high.

An object of the present invention is to provide a method of manufacturing a transistor which forms a transistor having different threshold voltages at low cost.

[0009]

The present invention is a method of manufacturing a transistor for forming transistors having different threshold voltages, which has been made in order to achieve the above object. That is, the first transistor having the second conductivity type pocket diffusion layer and the second transistor having no pocket diffusion layer formed on at least the channel region side of the first conductivity type source / drain region are formed on the same semiconductor substrate. In the method for manufacturing a transistor to be formed, in the first step, after forming the first and second gate electrodes in each of the first and second transistor formation regions on the semiconductor substrate, the second gate electrode is formed. A mask pattern is formed in a state in which an area above a predetermined width is opened from both sides. Then, in a second step, an impurity for forming a pocket diffusion layer is introduced into the first transistor formation region by an oblique ion implantation method using the first gate electrode as an ion implantation mask. At that time, the mask pattern and the second gate electrode prevent impurities from being introduced into the semiconductor substrate in the predetermined region from both sides of the second gate electrode.

Further, the mask pattern, the first gate electrode and the second gate electrode are used as an ion implantation mask between the first step and the second step or after the second step is performed. By the ion implantation method described above, impurities for forming the first and second LDD diffusion layers are introduced into the semiconductor substrate on both sides of the first and second gate electrodes, respectively.

[0011]

In the method of manufacturing a transistor described above, the mask pattern is formed in such a manner that an area above a predetermined width from both sides of the second gate electrode is opened. Then, in a second step, an impurity for forming a pocket diffusion layer is introduced into the first transistor formation region by an oblique ion implantation method using the first gate electrode as an ion implantation mask. At that time, the mask pattern and the second gate electrode prevent impurities from being introduced into the semiconductor substrate in the predetermined region from both sides of the second gate electrode. Therefore, the pocket diffusion layer is formed in the first transistor formation region, but the pocket diffusion layer is not formed in the second transistor formation region.

Further, in the third step of introducing the impurities for the first and second LDD diffusion layers into the semiconductor substrate, if the impurities are introduced into the semiconductor substrate on the side of each of the first and second gate electrodes. good. Therefore, by using the mask pattern formed for introducing the impurities for the pocket diffusion layer as the ion implantation mask for introducing the impurities,
It is not necessary to form a new ion implantation mask. That is, since the ion implantation mask can be used also, the photolithography process for forming the ion implantation mask can be reduced.

[0013]

EXAMPLE As a first example of the present invention, an N-channel transistor having a normal threshold voltage (for example, a threshold voltage of about 0.5V to 0.8V) and a low threshold voltage (for example, 0V) are used. A method of forming an N-channel transistor having a threshold voltage of about 0.0 V to 0.3 V) on the same semiconductor substrate will be described with reference to the manufacturing process chart of FIG.

As shown in FIG. 1A, the semiconductor substrate 1
In 1, an element isolation region 14 that separates the first transistor formation region 12 and the second transistor formation region 13 is formed. In addition, by the ion implantation method,
Semiconductor substrate 1 of second transistor forming regions 12 and 13
The first upper layer of the first conductive type (for example, P
Type) well region 15 (hereinafter referred to as P well region 15)
Are formed. In the ion implantation method, for example, the implantation energy is set to several hundred keV and the dose amount is set to 1
T / cm ^{2 to} 100 T / cm ² is set, and, for example, boron (B ⁺ ) is ion-implanted.

Further, the threshold voltage (Vth) of the N-channel transistor to be formed is 0.0V to 0.3V.
In order to adjust the surface concentration to a certain level, for example, boron (B ⁺ ) is ion-implanted by an ion implantation method to adjust the surface concentration. The ion implantation condition at this time, for example, set the implantation energy hundreds keV, to set the dose to 0.1T pieces / cm ² ~1T pieces / cm ^2.

In the first step, an ordinary process for forming a gate insulating film and a gate electrode is performed on the first transistor forming region 12 of the semiconductor substrate 11 to form a gate insulating film and a gate electrode.
First gate electrode 22 via first gate insulating film 21
To form. At the same time, the second semiconductor substrate 11
A second gate electrode 32 is formed on the transistor forming region 13 with the second gate insulating film 31 interposed therebetween.

Then, a resist film (not shown) is formed on the semiconductor substrate 11 by, for example, a photolithography technique to form a resist film (not shown), and then the resist film is patterned to form both sides of the second gate electrode 32. A mask pattern 16 is formed in the second transistor formation region 13 with an opening above a region having a predetermined width b.

As shown in (2) of FIG. 1, the mask pattern 16 (the hatched region) has a second gate electrode 3
A part of the active region on both sides of 2 is formed so as to be opened by a predetermined width b from both sides of the second gate electrode 32. Further, the first transistor formation region 12 is formed to be open.

Next, as shown in FIG. 1C, the second step is performed. In this step, the first gate electrode 32 is used as an ion implantation mask by the oblique ion implantation method,
Impurities (for example, boron) 41 that form a pocket diffusion layer are introduced into the first transistor formation region 13. At this time, the mask pattern 16 and the second gate electrode 42 introduce the impurities 41 into the second transistor formation region 14 on both sides of the second gate electrode 42 and in the predetermined region s below the gate electrode 22. Prevent.

That is, in the oblique ion implantation method, tan θ> b / h is set, where θ is the ion implantation angle and h is the height of the ion implantation mask. Normally,
θ is set to about 45 ° to 60 °. The value of θ is 60
It can be set to a value greater than °. As the ion implantation conditions, for example, the implantation energy is set to several tens keV and the dose amount is 10 / Tcm ² to 10.
For example, boron (B ⁺ ) is ion-implanted by setting it to 0T / cm ² .

If the ion implantation angle θ is set in this way, when the semiconductor substrate 11 is rotated and oblique ion implantation is performed, the first transistor formation region 12 has the first ion implantation angle θ.
Impurities 41 are introduced into the semiconductor substrate 11 on both sides of the first gate electrode 22 and the semiconductor substrate 11 laterally below the first gate electrode 22.

On the other hand, in the second transistor formation region 13, as shown in (4) of FIG. 1, for example, when the impurity (41) is ion-implanted in the direction of arrow A in the drawing,
One side 16a of the mask pattern 16 (hatched area)
Since the impurity (41) that is obliquely ion-implanted is blocked by, the impurity (41) is not introduced into the semiconductor substrate 11 in the opening region S1 on one side of the second gate electrode 32. On the other side of the second gate electrode 32,
Since the second gate electrode 32 blocks the impurity (41), the impurity (41) is introduced into the semiconductor substrate 11 in a region within the predetermined region s1 (region indicated by a broken line with dashed lines) from the second gate electrode 32. Not done. However, the impurity (41) is introduced into the semiconductor substrate 11 except the predetermined region s1 of the opening region S2 on the other side of the second gate electrode 32.

Further, for example, in the drawing, when the impurity (41) is ion-implanted from the direction of arrow a, the other side 16b of the mask pattern 16 blocks the obliquely ion-implanted impurity (41). The impurity (41) is not introduced into the semiconductor substrate 11 in the opening region S2 on the other side of the gate electrode 32. On the one side of the second gate electrode 32, the second gate electrode 32 blocks the impurities (41), so that the impurities (41) in the region within the predetermined region s2 from the second gate electrode 32 are contained in the semiconductor substrate 11. 41) is not introduced. However, the semiconductor substrate 11 in the opening region S1 on the other side of the second gate electrode 32 excluding the region within the predetermined region s2 (region indicated by the dashed diagonal line).
Impurities (41) are introduced into.

Further, for example, in the drawing, when the impurity (41) is ion-implanted in the direction of arrow C, the obliquely ion-implanted impurity (41) is blocked by the mask pattern 16 and the second gate electrode 32. , The semiconductor substrate 11 below the second gate electrode 32 has the impurities (4
1) is not introduced.

Further, for example, when the impurity (41) is ion-implanted in the direction of arrow D in the drawing, the impurity (4) is added to the semiconductor substrate below the second gate electrode 32.
1) is introduced, but the introduced region is usually LD
Since the D diffusion layer is formed and does not serve as the channel region of the transistor, it does not affect the threshold voltage.

In each of the ion implantations described above, boron was used as the impurity 41, but it is possible to use other ones, and as an example, boron difluoride (BF ₂ ⁺ ) can be used.

In the above description, ion implantation was performed while rotating the semiconductor substrate 11, but, for example, when the forming directions of the first and second gate electrodes 22 and 32 are the same,
Instead of rotating the semiconductor substrate 11, ion implantation may be performed in one direction, and then the semiconductor substrate 11 may be rotated 180 ° to perform ion implantation again.

In the above transistor manufacturing method, when the oblique ion implantation method for forming the pocket diffusion layer is performed in the first transistor forming region 12, the mask pattern 16 and the second pattern are formed in the second transistor forming region 13. The second gate electrode 32 prevents the impurities 41 from being introduced into the semiconductor substrate 11 in the predetermined region s from both sides of the second gate electrode 32. Therefore, the pocket diffusion layer is not formed in the second transistor formation region 13.

Further, as a second embodiment, as a third step between the first step and the second step described in FIG. 1 above or after the second step is performed, the LD is set as a third step.
A method of introducing impurities for forming the D diffusion layer will be described with reference to FIG. In the figure, the same components as those described with reference to FIG. 1 are designated by the same reference numerals.

As shown in FIG. 2, the mask pattern 16, the first gate electrode 22 and the second gate electrode 32 formed in the first embodiment are used as an ion implantation mask by the ion implantation method. Semiconductor substrate 11 in the first transistor formation region 12 on both sides of the first gate electrode 22.
An impurity 42 that forms the first LDD diffusion layer is introduced into. At the same time, an impurity 42 that forms a second LDD diffusion layer is introduced into the semiconductor substrate 11 in the second transistor formation region 13 on both sides of the second gate electrode 32.

As the ion implantation conditions, for example, the implantation energy is set to several tens keV and the dose amount is set to 1
The number is set to 0 T / cm ^{2 to} 100 T / cm ² and, for example, arsenic (As ⁺ ) or phosphorus (P ⁺ ) is ion-implanted.

In the second embodiment, the first and second LDs are
In the third step of introducing the impurity 42 for the D diffusion layer into the semiconductor substrate 11, the impurity 42 may be introduced into the semiconductor substrate 11 on the side of each of the first and second gate electrodes 22 and 32. Therefore, by using the mask pattern 16 formed for introducing the impurity 41 for the pocket diffusion layer as an ion implantation mask when introducing the impurity 42, it becomes unnecessary to form a new ion implantation mask. That is, since it is possible to use both the one used for forming the pocket diffusion layer and the one used for forming the LDD diffusion layer, the photolithography process for forming the ion implantation mask is reduced. It

After that, the mask pattern 16 is removed by asher processing or wet etching. Then, as shown in (1) of FIG. 3, the first sidewalls 23 are formed on both sides of the first gate electrode 22 and the both sides of the second gate electrode 32 are formed on the both sides of the first gate electrode 22 by a normal sidewall formation method. , The second sidewall 3
3 is formed.

Then, for example, by chemical vapor deposition,
An insulating film 17 is formed on at least the semiconductor substrate 11 in each of the first and second transistor formation regions 12 and 13. Further, an ion implantation mask (not shown) for forming source / drain regions is formed by photolithography, and then the semiconductor substrate on both sides of each of the first and second gate electrodes 22 and 32 is formed by ion implantation. Impurities 43 that form the first and second source / drain regions are introduced into predetermined regions 11 of the semiconductor device. Then, the ion implantation mask (not shown) is removed by asher processing, wet etching or the like.

Subsequently, as shown in (2) of FIG. 3, activation annealing is performed to form the first LDD diffusion layers 24 and 25 on both sides of the first gate electrode 22 to form a first layer. Source / drain regions 26 and 27 are formed. Further, pocket diffusion layers 28 and 29 are formed in a state of covering the lower side of each of the first source / drain regions 26 and 27. The pocket diffusion layers 28 and 29 may be formed at least on the first channel region 30 side.

At the same time, second source / drain regions 36 and 37 are formed on both sides of the second gate electrode 32 with the second LDD diffusion layers 34 and 35 interposed therebetween. At this time the second
Diffusion layers 38, which are formed by diffusing impurities (not shown) implanted to form the pocket diffusion layers 28, 29 in the lower portions of the source / drain regions 36, 37 of
39 is formed. As described above, the first and second transistors 1 and 2 are formed.

In a transistor having a pocket diffusion layer, the channel length is usually reduced by the width of the pocket diffusion layer. Therefore, the threshold voltage is lowered by the short channel effect, but the threshold voltage of the portion in the pocket diffusion layer is increased, so that the effective reduction of the threshold voltage is suppressed.

In the first transistor 1, the threshold voltage of the pocket diffusion layers 28 and 29 is set to a high value to obtain a threshold voltage higher than that of the second transistor 2. It will be possible. For example, the threshold voltage Vth2 of the pocket diffusion layers 28 and 29 ≧
When set to 1V, the threshold voltage of the first transistor 1 becomes 0.5V to 0.8V.

On the other hand, in the second transistor 2, since the diffusion layers 37 and 38 are not formed in the channel region 39, the pocket diffusion layer is not formed. Therefore, since the diffusion layers 37 and 38 do not affect the threshold voltage, the threshold voltage becomes Vth2 which is the initially set threshold voltage. That is, 0.0 V
It becomes 0.3V.

After that, as shown in FIG. 4, the first and second transistors 1 and 2 are formed by an ordinary chemical vapor deposition method.
An interlayer insulating film 51 is formed so as to cover the. Then, by photolithography technology and etching,
Contact holes 52, 53, 5 are formed in the interlayer insulating film 51 on the second source / drain regions 26, 27, 36, 37.
4, 55 are formed.

Then, a plug 56 is formed inside each of the contact holes 52 to 55 by a normal plug forming technique, for example.
To form 59. Further, the wirings 60 to 63 connected to the plugs 56 to 59 are formed by a normal wiring forming technique. Although not shown, wirings connected to the first and second gate electrodes 22 and 32 are similarly formed.

In the above description, the case of forming the N-channel transistor has been described, but the case of forming the P-channel transistor can also be formed in the same manner as above by changing the conductivity type of the components and impurities. .

[0043]

As described above, according to the present invention,
After forming a mask pattern in a state in which a region having a predetermined width from both sides of the second gate electrode is opened, an impurity for forming a pocket diffusion layer is introduced into the first transistor formation region by an oblique ion implantation method. . At that time, since the mask pattern and the second gate electrode prevented impurities from being introduced into the semiconductor substrate in the predetermined region from both sides of the second gate electrode, pocket diffusion occurs in the first transistor formation region. Although the layer is formed, the pocket diffusion layer is not formed in the second transistor formation region. Therefore, it is possible to form transistors having different threshold voltages depending on the presence or absence of the pocket diffusion layer.

Since the mask pattern used for introducing the impurities for forming the pocket diffusion layer is the ion implantation mask for introducing the impurities for the LDD diffusion layer, the impurities for the LDD diffusion layer are newly added. It is not necessary to form an ion implantation mask for introducing. That is, since the ion implantation mask can also be used, the photolithography process for forming the ion implantation mask can be reduced. Therefore, the manufacturing cost can be reduced.

[Brief description of drawings]

FIG. 1 is a manufacturing process diagram of an example.

FIG. 2 is an explanatory diagram of an impurity introduction method for forming an LDD diffusion layer.

FIG. 3 is a process drawing of forming source / drain regions.

FIG. 4 is a process drawing of forming a wiring.

FIG. 5 is a manufacturing process diagram of a conventional example.

[Explanation of symbols]

1 1st transistor 2 2nd transistor 11 Semiconductor substrate 12 1st transistor formation area 13 2nd transistor formation area 16 Mask pattern 21 1st gate insulating film 22 1st gate electrode 24 1st LDD diffusion layer 25 First L
DD diffusion layer 26 First source / drain region 27 First source / drain region 28 Pocket diffusion layer 29 Pocket diffusion layer 30 First channel region 31 Second gate insulating film 32 Second gate electrode 34 Second L
DD diffusion layer 35 Second LDD diffusion layer b Specified width s Specified region

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁵ Identification code Office reference number FI Technical indication location H01L 29/784 9054-4M H01L 29/78 301 L 9054-4M 301 P

Claims (2)

[Claims] 1. A first transistor having a pocket diffusion layer of a second conductivity type formed on at least a channel region side of a source / drain region of the first conductivity type and a second transistor having no pocket diffusion layer are the same. In a method of manufacturing a transistor formed on a semiconductor substrate, a first gate electrode is formed in a first transistor formation region on a semiconductor substrate via a first gate insulating film, and a second gate electrode on the semiconductor substrate is formed. First, a second gate electrode is formed in the transistor formation region via a second gate insulating film, and then a mask pattern is formed in a state in which regions having a predetermined width from both sides of the second gate electrode are opened. And an oblique ion implantation method, using the first gate electrode as an ion implantation mask to form a pocket on the semiconductor substrate in the first transistor formation region. The impurity that forms the diffusion layer is introduced, and at the same time, the impurities are introduced into the semiconductor substrate in a predetermined region from both sides of the second gate electrode by the mask pattern and the second gate electrode. And a second step of preventing. 2. The method of manufacturing a transistor according to claim 1, wherein the mask pattern and the first pattern are formed between the first step and the second step or after the second step is performed.
Forming a first LDD diffusion layer on the semiconductor substrate in the first transistor formation region on both sides of the first gate electrode by an ion implantation method using the second gate electrode and the second gate electrode as an ion implantation mask. Impurities are introduced into the semiconductor substrate in the second transistor formation region on both sides of the second gate electrode, and second L
A method of manufacturing a transistor, which comprises performing a third step of introducing an impurity forming a DD diffusion layer.