JPH07176634A - Mask rom and fabrication thereof - Google Patents

Abstract

PURPOSE:To shorten TAT in an NAND type mask ROM by forming an impurity region having a conductivity type opposite to that of a source-drain region at least on the channel side on the outside of the source-drain region in a memory transistor which must be enhancement type depending on the information to be stored. CONSTITUTION:A plurality of MOS memory transistors 30 are formed while sharing one source-drain region 22 and impurities of same conductivity type as the source-drain region 22 are introduced into the channel region of each memory transistor 30. An impurity region 24 having conductivity type opposite to that of the source-drain region 22 is formed at least on the channel side on the outside of the source-drain region 22 in a memory transistor 30e which must be enhancement type depending on the information to be stored. For example, P-type diffusion region 24 is not formed on the channel side of the source-drain region 22 in a memory transistor 30d to be rendered depletion type.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a NAND type mask ROM device having a MOS type memory transistor and a manufacturing method thereof.

[0002]

2. Description of the Related Art One type of mask ROM is a NAND type mask ROM. The NAND-type mask ROM is one in which a select transistor and several memory transistors are connected in series, and a series of memory transistors are formed with one source / drain region in common. In the NAND type ROM, since it is not necessary to provide a contact hole in each memory transistor, high integration is easy.

A NAND-type ROM is known in which information is programmed depending on whether the memory transistor is an enhancement type or a depletion type for the purpose of reducing the occupied area per bit of the memory transistor. (See Japanese Patent Publication No. 58-51427).

The process of programming information in the NAND type ROM is shown in FIG. Memory transistor is NMOS
The case of a transistor will be described as an example. (A) A field oxide film 4 is formed on the surface of a P-type silicon substrate 2 so as to have openings in a region where a series of memory transistors are formed, and then a gate oxide film 6 is formed. After that, as a programming step for separately forming the memory transistor into an enhancement type and a depletion type, for example, boron ions are implanted at 1 × 10 ¹³ / cm ² at 30 KeV to adjust the threshold voltage of the enhancement type transistor, A resist pattern 8 having an opening in a region to be a depletion type transistor is formed according to information to be written. Using the resist pattern 8 as a mask, the same conductivity type (N type in this case) impurity as the source / drain regions, for example, arsenic 130
Ion implantation is performed at 4 × 10 ¹² / cm ^{2 with} KeV.

(B) 14 is an N-type diffusion region for depletion transistor in which arsenic is implanted. After removing the resist pattern 8 and the silicon oxide film 6,
A gate oxide film 10 is formed on the exposed surface of the silicon substrate 2. A polysilicon film is deposited on the entire surface and patterned by photolithography and etching to form a polysilicon gate electrode 12. Next, in order to form the source / drain regions, the gate electrode 12 and the field oxide film 4 are formed.
As a mask, arsenic is ion-implanted in a dose of 5 × 10 ¹⁵ / cm ² at 50 KeV in a self-aligning manner.

(C) 16 is a source / drain region. After that, an interlayer insulating film is deposited according to a known process,
A contact hole is formed in a required place and a metal wiring is formed on it.

In the method of FIG. 1, the programming process is performed after the field oxide film is formed and before the gate oxide film is formed, and the programming process is located relatively earlier than the entire wafer process. Therefore, TAT (Turn Around
Time: There is a problem that the time required from the program process to shipping will be long.

As one method for shortening the TAT in the NAND type mask ROM, the entire memory transistor is formed in the enhancement type, and after forming the gate electrode, the source / drain regions are formed from both sides of the gate electrode (source / drain regions).
A method has been proposed in which an impurity of the same conductivity type as that used for the drain region is ion-implanted, and the implanted impurity is diffused by heat treatment to be connected at the lower side of the gate electrode to change to the depletion type. (See JP-A-2-273967).

As another method for shortening the TAT in the NAND type mask ROM, the gate electrode and the source / drain regions are formed so that all memory transistors are formed in the enhancement type and the TAT is stored according to the information to be stored. By including the both sides of the gate electrode of the memory transistor to be a depletion type, removing a part of the gate electrode, and then depositing the PSG film, and performing heat treatment to diffuse phosphorus in the PSG film into the substrate, The memory transistor is changed to a depletion type by shortening the channel length of a specific memory transistor or by short-circuiting the source / drain regions (see Japanese Patent Publication No. 3-34664).

[0010]

The present invention also provides a method of manufacturing a NAND type mask ROM by a method different from the above-mentioned method in order to shorten the TAT, and a semiconductor device formed by the method. It is intended to provide the structure of.

[0011]

In a NAND type mask ROM of the present invention, a plurality of MOS type memory transistors are formed with one source / drain region in common, and the source / drain is formed in the channel region of each memory transistor. An impurity of the same conductivity type as that of the region is introduced, and in the memory transistor which should be an enhancement type according to the information to be stored, the conductivity type opposite to the source / drain region is provided at least on the channel side outside the source / drain region. Impurity region is formed.

One aspect of the method of manufacturing a mask ROM device of the present invention includes the following steps (A) to (E).
(A) a step of introducing an impurity of the same conductivity type as the impurities for the source / drain regions into the semiconductor substrate surface of the entire memory transistor region, (B) a step of forming a gate oxide film,
(C) a step of depositing a polysilicon film on the gate oxide film and patterning it to form a gate electrode, (D) a step of introducing impurities into the semiconductor substrate for forming source / drain diffusion regions using the gate electrode as a mask, (D) After that, a resist pattern having an opening is formed in the memory transistor region to be an enhancement type according to the information to be stored, and the resist pattern is used as a mask on the substrate to have a conductivity type opposite to that of the source / drain region. A step of ion-implanting an impurity having a diffusion coefficient larger than that of the drain region at a concentration lower than that of the source / drain regions, and (E) after removing the resist pattern, heat-treating the source of the memory transistor to be an enhancement type. · Opposite to the source / drain region on at least the channel side of the drain region Forming an impurity region of the conductivity type.

Another aspect of the method for manufacturing a mask ROM device of the present invention includes the following steps (A) to (D).
(A) a step of introducing an impurity of the same conductivity type as the impurities for the source / drain regions into the semiconductor substrate surface of the entire memory transistor region, (B) a step of forming a gate oxide film,
(C) a step of depositing a polysilicon film on the gate oxide film and patterning it to form a gate electrode, (D) a step of introducing impurities into the semiconductor substrate for forming source / drain diffusion regions using the gate electrode as a mask, (D) After that, a resist pattern having an opening is formed in a memory transistor region to be an enhancement type according to the information to be stored, and an impurity having a conductivity type opposite to that of the source / drain region is obliquely formed on the substrate using the resist pattern as a mask. A step of forming an impurity region of a conductivity type opposite to that of the source / drain region on at least the channel side of the source / drain region of the memory transistor to be enhancement type by ion implantation by the rotating ion implantation method.

[0014]

A memory transistor in which an impurity region formed by introducing an impurity of the same conductivity type as the source / drain region into the channel region and connected to the source / drain region is a depletion type. On the other hand, in a memory transistor in which an impurity region having a conductivity type opposite to that of the source / drain region is formed at least on the channel side outside the source / drain region, the threshold voltage becomes high and the memory transistor becomes an enhancement type.

[0015]

FIG. 2 shows an embodiment. This embodiment is an embodiment applied to an N-channel type memory transistor.
The same reference numerals are used for the same parts as in FIG. On the surface of the P-type silicon substrate 2, an active region is formed by the field oxide film 4 in order to form a NAND type memory transistor array. In the active region, a polysilicon gate electrode 12 is formed on the gate oxide film 10 on the substrate, and N-type impurities such as arsenic are implanted into the substrate surface below the gate electrode 10 in each memory transistor. An N type diffusion region 20 is formed. The source / drain regions 22 are formed by self-aligned ion implantation of N-type impurities such as arsenic using the gate electrode 12 and the field oxide film 4 as a mask.

Reference numeral 30 denotes a memory transistor. In this example, the memory transistor indicated by 30d is a depletion type, and the other memory transistor 30e is an enhancement type. In the enhancement type memory transistor 30e, the source / drain region 2
A P-type diffusion region 24 is formed on the outer side of 2. Since the P-type diffusion region 24 is also formed on the channel region side to prevent the N-type diffusion region 20 below the gate electrode and the source / drain region 22 from being connected to each other, those memory transistors 30e have threshold voltages. The voltage is high and it is an enhancement type. On the other hand, the memory transistor 30
In d, the P-type diffusion region 24 is not formed on the channel side of the source / drain region, and the N-type diffusion region 20 and the source / drain region 22 are connected to each other to lower the threshold voltage, resulting in depletion. It is a type.

As impurities for forming the P type diffusion region 24, BF ₂ ion implantation or boron ion implantation is used. Although FIG. 2 shows an example of an N-channel type memory transistor, the present invention can be applied to a P-channel type memory transistor.

Next, a method of manufacturing the embodiment of FIG. 2 will be described with reference to FIG. (A) The field oxide film 4 is formed on the surface of the P-type silicon substrate 2.
To form. The silicon oxide film 6 used when forming the field oxide film or the silicon oxide film formed thereafter is left on the substrate surface in the active region surrounded by the field oxide film 4. Arsenic is ion-implanted into the entire surface of the substrate 2 through the silicon oxide film 6 at 4 × 10 ¹² / cm ² at 130 KeV to make all the memory transistors of the depletion type.

(B) 20 is an N-type diffusion region into which arsenic is implanted. After removing the silicon oxide film 6, the gate oxide film 10 is formed. A polysilicon film is deposited on the gate oxide film 10, and a polysilicon gate electrode 12 is formed by photolithography and etching. Then, the gate electrode 1
2 and the field oxide film 4 are used as masks to form source / drain regions. For example, arsenic is 5 × 1 at 50 KeV.
0 ¹⁵ / cm ² ions are implanted.

(C) 22 is a source / drain region. After that, a resist pattern 32 having an opening in a memory transistor region to be an enhancement type is formed according to the information to be written, and the resist pattern 32 is formed.
With BF ₂ at 70 KeV and 7 × 10
Ion implantation of ¹² to 1 × 10 ¹³ / cm ^{2 is performed} . After removing the photoresist pattern 32, an interlayer insulating film is deposited, a contact hole is opened, and a metal wiring is formed according to a known process.

The BF ₂ ions implanted into the substrate using the gate electrode 12 and the photoresist pattern 32 as a mask,
A P type diffusion region 24 is formed outside the source / drain region 22 by diffusion by heat treatment or the like when forming the interlayer insulating film. The P-type diffusion region 24 blocks the connection between the N-type diffusion region 20 and the source / drain region 22, and shifts the threshold voltage of the memory transistor in the positive direction to make it an enhancement type. A desired threshold voltage can be obtained by adjusting the energy and dose of BF ₂ ion implantation.

In the method of FIG. 3, arsenic in the source / drain region and P-type diffusion are formed in order to form a P-type diffusion region 24 for blocking the connection between the N-type diffusion region 20 in the channel region and the source / drain region 22. The difference in diffusion coefficient from BF ₂ or boron for the region 24 is used, and BF ₂ or boron, which is easily diffused, is diffused to the outside of the source / drain region by heat treatment.

As another method for ensuring that the P-type diffusion region 24 is formed on the channel side of the source / drain region, the oblique rotation ion implantation method can be used when implanting the P-type impurity. . Another embodiment of the manufacturing method of the present invention is a method utilizing such an oblique rotation ion implantation method.

In the step (C) of FIG. 3, when implanting BF ₂ ions, oblique rotation ion implantation having an angle so that the implanted ions can enter the lower side of the gate electrode is performed.
As a result, the P-type diffusion region 24 can more reliably prevent the N-type diffusion region 20 and the source / drain region 22 from being connected to each other, and the enhancement type can be obtained. NAND type RO
When M is composed of CMOS, this programming step may be performed after ion implantation for the source / drain regions of the PMOS transistor.

[0025]

According to the present invention, the source
Impurities of the same conductivity type as the impurities for the drain region are introduced to make all the memory transistors depletion type, and after forming the gate electrode and the source / drain regions,
The diffusion region and source of the channel region of the memory transistor, which should be enhanced according to the information to be stored,
Since the ion implantation is performed to prevent the connection with the drain region, the programming process is performed after the ion implantation for the source / drain regions, and the TAT can be shortened.

[Brief description of drawings]

FIG. 1 is a process sectional view showing a method of manufacturing a conventional NAND ROM.

FIG. 2 is a sectional view showing an example.

FIG. 3 is a process cross-sectional view showing the manufacturing method of the embodiment.

[Explanation of symbols]

 2 P-type silicon substrate 10 Gate oxide film 12 Polysilicon gate electrode 20 N-type diffusion region 22 Source / drain region 24 P-type diffusion region 30e Enhancement type memory transistor 30d Depletion type memory transistor

Claims (3)

[Claims] 1. A plurality of MOS type memory transistors are formed with one source / drain region in common, and an impurity of the same conductivity type as that of the source / drain region is introduced into a channel region of each memory transistor. In the memory transistor to be an enhancement type according to the information to be stored, an impurity region having a conductivity type opposite to that of the source / drain region is formed on at least the channel side outside the source / drain region. Mask ROM device. 2. A method of manufacturing a mask ROM device including the following steps (A) to (E). (A) A step of introducing impurities of the same conductivity type as the impurities for the source / drain regions into the semiconductor substrate surface of the entire memory transistor area, (B) a step of forming a gate oxide film, (C) a poly oxide film on the gate oxide film. A step of depositing and patterning a silicon film to form a gate electrode; (D) a step of introducing impurities into the semiconductor substrate for forming source / drain diffusion regions using the gate electrode as a mask; (D) information to be stored thereafter A resist pattern with an opening is formed in the memory transistor region that should be an enhancement type according to the above, and with the resist pattern as a mask, the substrate has a conductivity type opposite to that of the source / drain region and a diffusion coefficient higher than that of the impurity in the source / drain region Ion implantation of large impurities at a concentration lower than that of the source / drain regions, and (E) removing the resist pattern After forming a opposite conductivity type impurity region between the source and drain regions on at least the channel side of the source-drain region of the memory transistor to be an enhancement type by heat treatment. 3. A method of manufacturing a mask ROM device including the following steps (A) to (D). (A) A step of introducing impurities of the same conductivity type as the impurities for the source / drain regions into the semiconductor substrate surface of the entire memory transistor area, (B) a step of forming a gate oxide film, (C) a poly oxide film on the gate oxide film. A step of depositing and patterning a silicon film to form a gate electrode; (D) a step of introducing impurities into the semiconductor substrate for forming source / drain diffusion regions using the gate electrode as a mask; (D) information to be stored thereafter A resist pattern having an opening is formed in the memory transistor region to be an enhancement type according to the above, and using the resist pattern as a mask, impurities of the opposite conductivity type to the source / drain region are ion-implanted by the oblique rotation ion implantation method. ,
A step of forming an impurity region having a conductivity type opposite to that of the source / drain region on at least the channel side of the source / drain region of the memory transistor to be an enhancement type.