JPH0846055A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To surely form an n-MIS and a p-MIS of narrow channel width each thereof has a plurality of kinds of threshold voltages. CONSTITUTION:In a manufacturing method of a semiconductor integrated circuit wherein a plurality of MIS transistors isolated by an element isolation insulation layer 12 are formed in a common semiconductor substrate 11, a frame part 14 of the same constitution as the gate electrode 13 is formed on the element isolation insulation layer 12 enclosing a formation region of at least some MIS transistors simultaneously with formation of the gate electrode 13. Furthermore, an MIS transistor with different threshold voltages Vth is formed simultaneously by adjusting a threshold voltage of the MIS transistor by performing high energy ion implantation of impurities which changes a substrate surface concentration below the gate electrode 13 through the gate electrode 13 of some MIS transistors.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, particularly a semiconductor integrated circuit for a specific application, so-called ASIC (Applicable
ation Spesific IC), the present invention relates to a method of manufacturing a semiconductor integrated circuit which is suitable for application.

[0002]

2. Description of the Related Art In logic circuits such as ASICs, field effect transistors of first and second conductivity type channels, that is, n-channel type MIS transistors (insulated gate type field effect transistors) (hereinafter referred to as n-MIS) are often used. In each of the p-channel type MIS (hereinafter referred to as p-MIS), it is required to form a plurality of types of n-MIS and p-MIS having different threshold voltages _Vth .

Such selection of the plurality of threshold voltages V _th is usually performed by forming an n-type or p-type in the channel forming portion on the semiconductor surface before forming the required gate insulating film of the MIS transistor.
A method is adopted in which ion implantation of the type impurities is performed and the surface concentration, that is, the substrate concentration, is set to different required concentrations.

However, according to this method, it is necessary to perform ion implantation according to the kind of the required threshold voltage V _th , and at the time of each ion implantation,
Since a mask for performing ion implantation at each limited position is required, the mask forming process, that is, the photolithography process is increased. This photolithography process, that is, the work involving coating, exposing, and developing a photoresist not only significantly impedes mass productivity, but also raises the cost.

As a method of avoiding the increase in the photolithography process, a process after the gate electrode is formed, for example, L
In a DD (Lightly Doped Drain) type MIS transistor, at the time of ion implantation of a low impurity concentration source or drain region, a so-called LDD region, or at high impurity concentration source or drain region (hereinafter referred to as S / D region) ion implantation. , P (phosphorus) is ion-implanted through the gate electrode at a relatively high energy, for example, 100 to 300 keV, to control the substrate surface concentration under the gate electrode to control a plurality of threshold voltages V. There is a way to set _th . That is, in this case, for example, n-
In the MIS, the effective surface concentration of the p-type well region under the gate electrode, that is, the substrate surface concentration, can be lowered by high-energy ion implantation of, for example, P (phosphorus) of the n-type impurity described above through the gate electrode. Since it is possible to reduce the V _th of the n-MIS, it is possible to set a plurality of types of V _th in the n-MIS having the same configuration without forming any special mask. is there.

However, in this method, since the ion implantation for controlling the threshold voltage V _th is performed through the gate electrode, the ion implantation needs to be performed with high energy. From each M on the substrate surface
The inter-element isolation insulating layer usually formed by LOCOS (Local Oxidation of Silicon) is also penetrated in the field portion between each circuit element such as IS transistor, for example, by the above-mentioned P (phosphorus) high energy ion implantation. The problem arises that the impurity concentration of the p-type channel stop region formed under the element isolation insulating layer is lowered, and the parasitic characteristics, particularly the punch-through resistance are deteriorated.

In order to avoid such a decrease in the impurity concentration of the channel stop region, it is possible to preliminarily increase the impurity concentration of the channel stop region sufficiently, or to cover the field portion with a photoresist. Good.

Generally, the formation of the inter-element isolation insulating layer is performed by forming the inter-element isolation insulating layer by LOCOS and then performing high-energy ion implantation for forming the channel-stop region over the entire surface. In the portion, the channel stop region is formed on the surface of the substrate below the element isolation insulating layer, and in the portion where the element isolation insulating layer is not formed, that is, in the element forming portion, the element characteristics are not substantially affected. Ion implantation is performed at a deep position.

However, if the method of forming the channel stop region with a high concentration in advance as described above is adopted, the impurity concentration under the element formation portion becomes large, so that the diffusion of the impurity by, for example, the subsequent heat treatment step is performed. This will increase the substrate density of the element formation part,
Effect of substrate bias on threshold voltage V _th The so-called substrate effect becomes remarkable. Further, as the concentration of the channel stop region is increased, the junction capacitance of the channel stop region is significantly increased.

Further, in the case where the method of covering the field portion with the photoresist is adopted, there arises a problem when the channel width becomes narrow. This will be described with reference to FIG. FIG. 11A shows a cross-sectional view in one step of this conventional method, and FIG. 11B shows a corresponding plan view in this case. In FIG. 11, on the surface of the semiconductor substrate 1,
Depending on the LOCOS, a so-called field portion other than the formation portion of each element such as n-MIS and p-MIS having a thickness of, for example, 25
The element isolation insulating layer 2 having a thickness of 0 nm to 300 nm is formed,
An element forming portion surrounded by the element isolation insulating layer 2,
In the figure, a state is shown in which a gate electrode 4 having a thickness of about 200 nm is formed across a formation portion of the n-MIS, with a tungsten silicide (WSi) layer formed on, for example, a polycrystalline silicon layer via a gate insulating layer 3. Has been done. Further, the low-concentration LDD region 5 in the LDD type MIS transistor is formed by ion implantation using the gate electrode 4 and the element isolation insulating layer 2 as a mask.

In this state, the element isolation insulating layer 2 in the field portion is covered with a resist layer 6 formed by photolithography. Although not shown, other n-MIS and p-MIS are formed in other parts on the common substrate 1.

Then, for example, P (phosphorus) ions are implanted with high energy penetrating the gate electrode 4 of the n-MIS formation portion shown in FIG.
The p-type substrate surface concentration under the lower gate insulating layer 3 is lowered. In this way, the threshold voltage V of the n-MIS
Do not perform high energy ion implantation of P (phosphorus) on _th ,
That is, it can be made lower than other n-MIS covered with the resist layer 4.

According to this method, in order to surely cover the inter-element isolation insulating layer 2 with the resist layer 6, the pattern of the resist layer 6 is, as shown in FIG. 11B, in photolithography at the time of forming this pattern. In order to maintain a margin of misalignment in aligning the exposure mask, it is necessary to form the element isolation insulating layer 6 by entering the element forming portion by the width d from the edge portion 6a. By the way, the width d is not limited to the above-mentioned misalignment of the mask, but also the variation of the resist line width,
Since it is necessary to consider so-called bird's beaks or the like generated at the edge of the element isolation insulating layer 2, it is about 0.4.
It is necessary to set it to μm to 0.5 μm. Therefore, assuming that the minimum interval for forming the resist layer 6 during photolithography is S (approximately 1.5 μm), n-MI in FIG.
The minimum channel width W of S must be the following (Equation 1).

[0014]

[Equation 1] W> S + 2 · d

Therefore, such a low threshold voltage V _th
The channel width of the MIS transistor described above is constrained to be a large channel width exceeding 2.3 μm due to its design.

[0016]

SUMMARY OF THE INVENTION It is an object of the present invention, on a common semiconductor substrate, each have a threshold voltage V _th of the plurality of types, for example, n-MIS of narrow channel widths, p-MI
S that can be reliably formed with S, avoids the influence on the channel stop region described above, and solves the problem of the decrease in the threshold voltage of the parasitic channel due to the low concentration of the channel stop region. Moreover, a method of manufacturing a semiconductor integrated circuit that can avoid increasing the concentration of the channel stop region and avoid the influence of the increasing concentration on the substrate surface concentration of the element forming portion, the increase of the junction capacitance of the channel stop region, etc. It is provided.

[0017]

According to a first aspect of the present invention, as shown in FIG. 5, a plurality of MIS transistors separated by an element isolation insulating layer 12 are formed on a common semiconductor substrate 11. In the method of manufacturing the circuit, in the step of forming the gate electrode 13 of the MIS transistor, at the same time as the formation of the gate electrode 13, the gate electrode 13 is formed on the element isolation insulating layer 12 surrounding the formation region of at least a part of the MIS transistor The frame portion 14 having the same configuration is formed.

After that, the above-mentioned part of the MIS transistor
Through the gate electrode 13 of the substrate under the gate electrode 13
High-energy ion implantation of impurities that change the surface concentration
To adjust the threshold voltage of this MIS transistor
Go to different threshold voltage V _thMIS transition with
The star is formed at the same time.

The second aspect of the present invention relates to a common semiconductor substrate 11
A plurality of MIs separated by the element isolation insulating layer 12.
In a method of manufacturing a semiconductor integrated circuit in which the S transistor has a MIS transistor of the first conductivity type channel and a MIS transistor of the second conductivity type channel, in the step of forming the gate electrode 13, the MIS transistor of the first conductivity type channel is formed. MI of at least some first conductivity type channels
A frame portion 14 having the same structure as the gate electrode 13 is formed on the element isolation insulating layer 12 surrounding the formation region of the S transistor.

After that, as shown in FIG. 5, the second
Opening 1 in the formation part of MIS transistor of conductivity type channel
Simultaneously with the formation of the selective ion implantation resist 16 having No. 5, the opening 17 is formed in the part where the first conductivity type channel MIS transistor is formed.

Thereafter, the gate electrode 1 of the MIS transistor in the opening 17 is passed through the gate electrode 1 through the gate electrode 13.
High-energy ion implantation of impurities for changing the substrate surface concentration under 3 is performed to adjust the threshold voltage of the MIS transistor.

Here, the term "semiconductor substrate" is used not only to refer to a semiconductor substrate as a whole but also to include a substrate having a semiconductor layer formed on an insulating or semi-insulating substrate. .

[0023]

In the manufacturing method of the present invention, as in the conventional method described above,
For at least a part of MIS transistors, high-energy ion implantation of impurities is performed through the gate electrodes to adjust the substrate surface concentration of impurities under the gate electrodes, so that a threshold voltage V different from that of other MIS transistors is obtained.
_In this case, since the frame portion 14 having the same structure as the gate electrode is formed on the inter-element isolation insulating layer, at least this frame portion 1 is adjusted.
In the portion where 4 and the element isolation insulating layer overlap with each other, the impurity ion implantation can be blocked even by the above-mentioned high-energy ion implantation, so high-energy ion implantation is avoided in the pattern of the frame portion 14, The influence of at least the required area of the channel stop area can be avoided.

Further, in the manufacturing method of the present invention, since the so-called mask function of preventing high-energy ion implantation into the necessary region of the channel stop region is formed by the frame portion 14 formed simultaneously with the gate electrode, this mask is formed. A special work for this, in fact, the complicated photolithography for forming this mask can be avoided, and at least the positional relationship between this mask, that is, the frame portion 1 and the gate electrode is automatically aligned. Since the portion 1 need only be formed so as to straddle at least the inter-element isolation insulating layer, that is, to be formed so as to cross between the adjacent elements, the margin d described in FIG. 11 is not necessary. In other words, it is not restricted by the minimum channel width W of the above (Formula 1), and the manufacturing method of the present invention is more effective when W ≦ 2.3 μm.

Therefore, for example, when forming MIS transistors having different channel widths W on the same semiconductor substrate, the above-described method of the present invention is applied when W ≦ 2.3 μm, and the conventional method is applied when W> 2.3 μm. It can also be applied.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the method of the present invention will be described with reference to FIGS. In this method, the above-mentioned first and second
Is used together to form a plurality of first conductivity type channel MIS transistors such as n-MIS and second conductivity type channel MIS transistors such as p-M1S on the common semiconductor substrate 11, and the n-MIS is further formed. part of the n-MIS (hereinafter particular as n-MIS) threshold voltage V _th of the threshold voltage V _th of the other n-MIS of the
1 to 9 in which two n-Ms of a specific n-MIS and another n-MIS are different.
Only IS and the formation part of one p-M1S are illustrated.

As shown in FIG. 1, on a main surface of a common semiconductor substrate, for example, a Si substrate 11, between elements forming portions for forming elements, in this example, finally n-MIS and p-M1S, respectively, The element isolation insulating layer 12 made of thick SiO ₂ having a thickness of 250 nm to 300 nm is formed by selective thermal oxidation, that is, LOCOS. Then, n-M of the substrate 11
A resist 1 serving as a mask for selective ion implantation in which an opening 18 is formed on the IS formation portion and the field portion around the IS formation portion 1.
9 is formed by photolithography, that is, by coating a photoresist, pattern exposure, and development, covering the formation portion of p-M1S and its periphery.

The resist 19 and the element isolation insulating layer 12
Is used as an ion implantation mask to ion-implant p-type impurities such as boron B to form a p-type well region 20 in the formation portion of the n-MIS surrounded by the element isolation insulating layer 12 in the opening 18. Ion implantation work and resist 19
With the mask as a mask, the element isolation insulating layer 12 is penetrated in the opening 18 to similarly implant a p-type impurity such as boron B to form a p-type channel stop region 21 under the element isolation insulating layer 12. Ion implantation work and, if necessary, adjustment of the threshold voltage V _th of the n-MIS (hereinafter referred to as V /
The ion implantation work of phosphorus P, which is an n-type impurity, by low energy for adjusting the substrate surface concentration is performed.

As shown in FIG. 2, the resist 19 is removed by a known method such as a plasma ashing method, and the p-M1S formation portion of the substrate 11 is newly formed on the main surface of the substrate 11 and a field portion around the p-M1S formation portion. A resist 22 having an opening 23 formed therein, that is, for example, serving as a mask for selective ion implantation of the pattern of the above-described resist 19 and the pattern of the front and back, is formed by photolithography.

Then, using the resist 22 and the element isolation insulating layer 12 as an ion implantation mask, for example, P (phosphorus) ions of an n-type impurity are implanted to be surrounded by the element isolation insulating layer 12 in the opening 23. n in the formation part of p-M1S
Of the n-type impurities such as P (phosphorus) by penetrating the element isolation insulating layer 12 in the opening 23 with the resist 23 as a mask.
Ion implantation to form the n-type channel stop region 25 under the inter-element isolation insulating layer 12 and, if necessary, low substrate surface concentration adjustment for V / A of p-M1S. Ion implantation of a low dose amount of p-type impurities such as boron B by energy is performed.

As shown in FIG. 3, the resist 22 is removed, and the MIS transistor formation portion surrounded by the element isolation insulating layer 12 on the substrate 11 is formed of, for example, SiO ₂ having a required thickness. The gate insulating layer 26 is formed by, for example, thermal oxidation, and a low-resistivity polycrystalline silicon layer, for example, is formed on the entire surface, and a refractory metal silicide layer, for example, a WSi layer is further formed on the gate insulating layer 26. Then, patterning is performed by photolithography to form the gate electrode 13 in each of the n-MIS and p-M1S formation portions. And the gate electrode 13
Simultaneously with the formation of the element, as shown in a schematic plan view of a part thereof in FIG. 10, finally, along the periphery of the formation portion of the specific n-MIS, that is, here, the element isolation insulating layer 1 is formed.
2. A frame portion 14 having the same structure as the gate electrode 13 is formed in a ring shape along the inner peripheral edge of 2 and over at least the element isolation insulating layer 12 and on the p-type channel stop region 21 thereunder. .

The thickness of the gate electrode 13 and the frame portion 14, that is, the total thickness including the above-mentioned polycrystalline silicon layer and WSi layer is selected to be 200 nm, for example.

Since the gate electrode 13 and the frame portion 14 are formed at the same time, the positional relationship between them is set accurately. However, the position of the frame portion 14 is, for example, the inner peripheral edge thereof, as shown in the figure, between the elements. It is not necessary to match the edge portion of the isolation insulating layer 12, that is, the tip edge of a so-called bird's beak whose thickness is thinned in a beak-shaped cross section, and outside the edge portion, that is, on the region where the film thickness of the element isolation insulating layer 12 is large. Can be formed.

As shown in FIG. 4, a resist 28 which covers the p-M1S formation portion and has an opening 27 formed in the n-MIS formation portion and serves as a mask for ion implantation is formed by a photoresist by photolithography. . Using this resist 28 as an ion implantation mask in the opening 27,
Further, using the gate electrode 13 in the opening 27 as a mask, n
Type impurities such as P (phosphorus) and As are ion-implanted at low energy to form low-concentration LDD regions 29 on both sides of each gate electrode 13 in the opening 27.

As shown in FIG. 5, the resist 15 is removed, and a resist 16 serving as a mask for selective ion implantation having an opening 15 in the p-M1S formation portion is formed by photolithography as described above. However, in this case, in particular, the required n-MI is formed at the same time when the opening 15 is formed.
The opening 17 is formed in the S forming portion. That is, other n-MI
A resist 16 covers the S forming portion. The positions of the openings 15 and 17 in this case are p−
The M1S formation portion, that is, the gate electrode 13 and the LDD region formation portions on both sides thereof are exposed to the outside, and the opening 17 is accurate enough to expose the gate electrode 13 of the specific n-MIS described above to the outside. , The photolithography mask alignment in resist patterning does not require much precision.

After that, the resist 16 is used as an ion implantation mask and the gate electrode 13 is used as a mask through the opening 15.
-Type impurity P (phosphorus) is ion-implanted to form a low-concentration p-type LDD on both sides of the gate electrode 13 in the opening 15.
A region 30 is formed. Further, in this case, if necessary, the implantation direction is inclined with respect to the substrate 11, or rotated to partially enter the lower portion of the gate electrode 13 from both sides of the gate electrode 13, so-called pocket ion implantation V /
Ion implantation of A is performed as necessary. In this case, the opening 1
The same ion implantation is performed on 7. Then, before or after these low-concentration p-type LDD region 30 is ion-implanted and pocket ion-implanted, P (phosphorus) ion-implantation is performed at a high energy of, for example, 100 to 300 keV, which penetrates the gate electrode 13. In particular, the substrate surface concentration under the gate electrode 13 of a specific n-MIS formation portion in which the opening 17 is formed is set to another n-M in which the opening 17 is not formed.
The concentration is different from the substrate surface concentration under the gate electrode 13 in the IS formation portion.

By this high-energy ion implantation, ion implantation of impurities of the same conductivity type as that of the well region 24 of the p-M1S forming portion in the opening 15 is also performed under the gate electrode 13.

In this high-energy ion implantation, the penetration of impurity ions occurs in the portion where the inter-element isolation insulating layer 12 directly faces the outside, but at least the above-mentioned specific n-MIS formation portion is formed. A frame portion 14 having the same configuration as the gate electrode 13 is formed in a ring shape on the inter-element isolation insulating layer 12 around the element. In this portion, the inter-element isolation insulating layer 12 and the frame portion 14 are stacked. Since the resistist 16 exists over the width of a part of it,
Around the specific n-MIS, the p-type channel stop region 21 can be stably left in a ring shape without being influenced by the implantation of P (phosphorus) as an n-type impurity.

Next, as shown in FIG. 6, the resist 16 is removed, and a side wall 31 is formed on each gate electrode 13. The sidewall 31 can be formed by a known method. That is, for example, Si on the substrate 11
An insulating layer such as O ₂ is formed over the entire surface to a required thickness by, for example, a CVD (Chemical Vapor Deposition) method, and then this insulating layer is subjected to anisotropic etching such as RIE (Reactive Ion Etching). Etching back is performed and etching is stopped when the insulating layer on the flat surface (the surface along the substrate surface) is removed. By doing so, a portion of the insulating layer having a large thickness in the etching direction of the anisotropic etching formed on the vertical surfaces of the end faces of the gate electrode 13, the frame portion 14 and the like is left, and as a result, the sidewall 31 is formed. Is formed.

As shown in FIG. 7, a resist serving as an ion implantation mask having an opening 32 that covers one conductivity type channel such as a p-M1S formation portion and exposes the other conductivity type channel such as an n-MIS formation portion to the outside. 33 is formed by photolithography or the like. The resist 33 is used as an ion implantation mask to be exposed through the opening 32.
In the MIS formation portion, the gate electrode 13, the side wall 31, and the element isolation insulating layer 11 are used as masks for n.
Ion implantation of a type impurity such as P (phosphorus) is performed to form a high-concentration S / D region 34.

As shown in FIG. 8, the resist 33 is removed, and the resist 33 has a reverse pattern, that is, n-M1.
A resist 36 serving as an ion implantation mask is formed by photolithography or the like to cover the S formation portion and have an opening 35 that exposes the p-MIS formation portion to the outside. By using this resist 36 as an ion implantation mask, the gate electrode 1 is further formed in the n-MIS formation portion exposed through the opening 35.
3, p-type impurity boron B is ion-implanted using the side walls 31 and the element isolation insulating layer 12 as a mask to form a high-concentration S / D region 37.

As shown in FIG. 9, the resist 36 is removed, and an insulating layer such as an interlayer insulating layer 38 is entirely covered with, for example, CV.
And an opening 3 is formed in each electrode or wiring lead-out portion.
9 is formed and, for example, Al is vapor-deposited on the entire surface and is sputtered, and is patterned by photolithography to form a wiring or an electrode 40 which makes ohmic contact with the electrode or a wiring lead-out portion, and an integrated circuit having a plurality of target MIS transistors. For example, an ASIC can be formed. That is, as shown in FIG. 9, a common substrate 11 is provided with p-M1S and a specific n-MIS (n-MIS.
₁ ) is formed at a threshold voltage different from that of other n-MISs (shown as n-MIS ₂ ).

That is, in this case, with respect to n-MIS ₂ , the substrate surface concentration which is one factor that determines the threshold voltage V _th is specified in comparison with the initial surface concentration in the p-type well region 20. The substrate surface concentration for n-MIS ₁ is determined by the surface concentration in the same p-type well region 20 and the concentration by pocket ion implantation and high energy ion implantation in the process shown in FIG. , The required threshold voltage V _th different from n-MIS ₂ is taken into consideration.
Can be set to. For example, n-MIS can be made lower than the threshold voltage of n-MIS ₂ by high-energy ion implantation of n-type impurities.

High-energy ion implantation through the gate electrode 13 for this specific n-MIS ₁ is performed by the resist 16 of the ion-implantation mask for forming p-M1S, as shown in the step of FIG. By doing so through the opening 17 formed together with the opening 15 of
Since a special mask (resist) forming step for performing this high-energy ion implantation is avoided, an increase in the number of steps can be avoided.

Then, in this case, a common resist, that is, an ion implantation mask, is used to reduce the p-M1S low-concentration LDD.
Ion implantation and pocket ion implantation for forming the region 30 will be performed for n-MIS _{1 and} high energy ion implantation will also be performed for p-M1S, but at p-M1S. Is, for example, n in consideration of doping of n-type impurities by high-energy ion implantation according to the target threshold voltage V _th.
By selecting the concentration of the mold well 24 in advance,
Also in n-MIS ₁ , p-M1S and n-MIS ₁ are selected by selecting the doping concentration of impurities by high-energy ion implantation in consideration of the influence on the threshold voltage V _th by pocket ion implantation. On the other hand, the same ion implantation does not cause any inconvenience. In addition, the resistance of the n-MIS ₁ is increased by doping the p-type impurity into the n-type source or drain region or the p-type is increased.
Regarding mold formation, high concentration S with sufficiently high concentration in the process of FIG.
By forming the / D region 29, no problem occurs.
Further, the high-energy ion implantation through the gate electrode 13 has a low dose amount, for example, about 10 ¹⁵ cm ⁻² , and the influence on each north / drain region is not a problem.

As described above, in the manufacturing method of the present invention, the function of a mask for preventing the implantation of high-energy ions into the channel stop region is formed by the frame portion 14 formed at the same time as the gate electrode 13, so that the mask is formed. A special work for doing so, in fact, complicated photolithography for forming this mask can be avoided, and at least this mask, that is, the frame portion 14 and the gate electrode 13
Since the positional relationship with
No. 4 does not require the tolerance d described in FIG. 11, since it is formed so as to straddle at least the element isolation insulating layer, that is, it only needs to be formed so as to cross between the adjacent elements. There is no restriction on the minimum channel width W of (Formula 1), and the manufacturing method of the present invention is W ≦ 2.3 μm.
And it will be more effective.

Therefore, for example, when forming MIS transistors having different channel widths W on the same semiconductor substrate, the above-described method of the present invention is applied when W ≦ 2.3 μm and the conventional method is applied when W> 2.3 μm. It can also be applied.

In the above-mentioned example, the high-energy ion implantation through the gate electrode for controlling the threshold voltage V _th of the specific n-MIS ₁ is performed by the p-M1S low-concentration LDD region 30.
This is the case where the opening 17 is formed simultaneously with the formation of the opening 15 in the resist 16 of FIG. 8A, and the resist 36 in the selective ion implantation of the high concentration S / D region 37 of p-M1S in the step shown in FIG. In addition, the above-mentioned opening 17 may be formed together with the opening 35 so that the above-mentioned high-energy ion implantation is performed.

Further, in the above-mentioned example, the threshold voltages of the n-MISs are different from each other. For example, in a plurality of p-M1Ss, at least a part of the threshold voltages _{Vth is set} to another value. The present invention can be applied to the case where the threshold voltage is different from that of p-M1S, and the threshold voltage is different in each of n-MIS and p-M1S.

Further, in the above-mentioned example, n-type P (phosphorus) is used as an impurity for high-energy ion implantation for adjusting the threshold voltage, but other impurities such as p-type impurity ions are used. Threshold voltage V
You can also adjust _th .

As described above, according to the manufacturing method of the present invention, MI having two different threshold voltages V _th.
The present invention is not limited to the case of forming the S transistor, and the MIS transistor of the first conductivity type channel having two or more kinds of threshold voltages V _th and the MIS transistor of the other conductivity type channel can be formed. It goes without saying that the present invention can be applied to the case of obtaining semiconductor integrated circuits having various configurations.

[0052]

As described above, in the manufacturing method of the present invention, high-energy ion implantation of impurities is performed through the gate electrode of at least a part of the MIS transistor to adjust the substrate surface concentration of the impurity under the gate electrode. ,
Although the threshold voltage V _th is adjusted to be different from that of the other MIS transistors, particularly in the present invention, the frame portion 14 having the same structure as the gate electrode 13 is formed on the element isolation insulating layer. Therefore, at least this frame portion 14,
In the portion where the element isolation insulating layer 12 overlaps, the impurity ion implantation can be blocked even by the above-mentioned high-energy ion implantation. Therefore, in the pattern of the frame portion 14, high-energy ion implantation is avoided and the channel stop is performed. It is possible to avoid the influence of at least the required area of the area.

In the manufacturing method of the present invention, the mask portion is formed because the frame portion 14 formed at the same time as the gate electrode has a so-called mask function of preventing high-energy ion implantation into the necessary region of the channel stop region. A special work for this, in fact, the complicated photolithography for forming this mask can be avoided, and at least the positional relationship between this mask, that is, the frame portion 1 and the gate electrode is automatically aligned. Since the part 1 need only be formed so as to straddle at least the element isolation insulating layer, that is, it may be formed so as to cross between the adjacent elements, the margin d described in FIG. 11 is not required. However, there are advantages such as not being restricted by the minimum channel width W of (Formula 1).

[Brief description of drawings]

FIG. 1 is a sectional view of a step of an embodiment of the manufacturing method of the present invention.

FIG. 2 is a sectional view of a step of an embodiment of the manufacturing method of the present invention.

FIG. 3 is a sectional view of a step of an embodiment of the manufacturing method of the present invention.

FIG. 4 is a sectional view of a step of an embodiment of the manufacturing method of the present invention.

FIG. 5 is a sectional view of a step of an embodiment of the manufacturing method of the present invention.

FIG. 6 is a sectional view of a step of an embodiment of the manufacturing method of the present invention.

FIG. 7 is a sectional view of a step of an embodiment of the manufacturing method of the present invention.

FIG. 8 is a sectional view of a step of an embodiment of the manufacturing method of the present invention.

FIG. 9 is a sectional view of a step of an embodiment of the manufacturing method of the present invention.

FIG. 10 is a plan view of an essential part of a step of an embodiment of the manufacturing method of the present invention.

FIG. 11A is a cross-sectional view of a main part in one step in a conventional manufacturing method. FIG. 6B is a plan view of a main part in the same process.

[Explanation of symbols]

 11 semiconductor substrate 12 element isolation insulating layer 13 gate electrode 14 frame portion 15 opening 16, 22, 28, 33 resist 17, 18, 23, 27, 32, 35 opening 20, 24 well region 21, 25 channel stop region 26 gate Insulating layer 29,30 Low concentration source or drain region 34,37 High concentration source or drain region

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical display location H01L 29/78 21/336 H01L 27/08 321 E 29/78 301 Y

Claims (2)

[Claims] 1. A method of manufacturing a semiconductor integrated circuit in which a plurality of insulated gate field effect transistors separated by an element isolation insulating layer are formed on a common semiconductor substrate, wherein a gate electrode of the insulated gate field effect transistor is formed. In the forming step, at the same time as forming the gate electrode, a frame portion having the same configuration as the gate electrode is formed on the element isolation insulating layer surrounding the formation region of at least a part of the insulated gate field effect transistor, and thereafter, Adjusting the threshold voltage of the insulated gate field effect transistor by performing high-energy ion implantation of impurities for changing the substrate surface concentration under the gate electrode through the gate electrode of the part of the insulated gate field effect transistor. A method of manufacturing a semiconductor integrated circuit, which is characterized by carrying out. 2. A plurality of insulated gate field effect transistors separated by an element isolation insulating layer on a common semiconductor substrate, wherein an insulated gate field effect transistor of a first conductivity type channel and a plurality of insulated gate field effect transistors of a second conductivity type channel are provided. An insulated gate field effect transistor, wherein in the step of forming the gate electrode, the insulated gate field effect transistor of the first conductivity type channel of at least a part of the insulated gate field effect transistor of the first conductivity type channel is provided. A selective ion having a frame portion having the same structure as the gate electrode is formed on the element isolation insulating layer surrounding the formation region, and then an opening is formed in the formation portion of the insulated gate field effect transistor of the second conductivity type channel. At the same time as the formation of the implantation resist, the insulated gate field effect of the first conductivity type channel in the part of the resist An opening is formed in the formation part of the transistor, and high-energy ion implantation of impurities for changing the substrate surface concentration under the gate electrode is performed through the gate electrode of the part of the insulated gate field effect transistor in the opening to perform the insulation. A method of manufacturing a semiconductor integrated circuit, comprising adjusting a threshold voltage of a gate type field effect transistor.