KR0133028B1 - Manufacturing method of cmos transistor - Google Patents

Abstract

The present invention relates to a method of manufacturing a highly reliable and highly integrated CMOS transistor. According to the present invention, after a first heat treatment is performed on each gate electrode and each gate electrode of an N-channel transistor and a P-channel transistor formed on a semiconductor substrate having a gate insulating film, the gate electrode of the N-channel transistor is used as a mask. After the second heat treatment at a lower temperature than the first heat treatment is performed on the N-type high concentration diffusion layer and the N-type high concentration diffusion layer serving as the source or the drain of the N-channel transistor, the P-channel transistor is used as a mask using the gate electrode of the P-channel transistor as a mask. A P-type high concentration diffusion layer and a P-type high concentration diffusion layer serving as a source or a drain of a transistor are subjected to a third heat treatment at a lower temperature than a second heat treatment.

Description

Manufacturing Method of CMOS Transistor

1A to 1G are cross-sectional views showing respective steps of a method of manufacturing a CMOS transistor according to the first embodiment of the present invention.

2A to 2J are cross-sectional views showing respective steps of a method of manufacturing a CMOS transistor according to a second embodiment of the present invention.

3A to 3I are cross-sectional views showing respective steps of a method of manufacturing a CMOS transistor according to a third embodiment of the present invention.

4A to 4G are cross-sectional views showing respective steps of a method of manufacturing a CMOS transistor according to a fourth embodiment of the present invention.

5A to 5J are cross-sectional views showing respective steps of a method of manufacturing a CMOS transistor according to a fifth embodiment of the present invention.

6 shows a schematic process of a method of manufacturing a CMOS transistor having a single gate electrode according to the first, second and third embodiments of the present invention and each of the modifications of the first, second and third embodiments. Cross-section.

FIG. 7 shows heat treatment applied to each component in the method of manufacturing the CMOS transistor shown in FIG.

FIG. 8 shows a schematic process of a manufacturing method of an XMOS transistor having dual gate electrodes in accordance with the fourth and fifth embodiments and the variations of the fourth and fifth embodiments.

FIG. 9 is a diagram showing a heat treatment applied to each component in the method of manufacturing a CMOS transistor shown in FIG.

FIG. 10 shows the relationship between the gate length of a CMOS transistor and the gate electrode of the CMOS transistor, the low diffusion layer and the high concentration diffusion layer of the N-channel transistor, and the heat treatment temperature necessary for forming the low concentration diffusion layer and the high concentration diffusion layer of the P-channel transistor as optimal ones, respectively. Figure.

FIG. 11 shows the relationship between the heat treatment temperature for the gate electrode of a CMOS transistor and the depletion of the gate electrode. FIG.

12 shows the relationship between the heat treatment temperature for the gate electrode of a CMOS transistor and the resistance of the gate electrode.

FIG. 13 shows the relationship between the gate length and the threshold value with the voltage when the heat treatment temperature applied to the gate electrode of the CMOS transistor is changed.

* Explanation of symbols for the main parts of the drawings *

1: Silicon substrate (semiconductor substrate) 2: P-type diffusion layer

3: N-type diffusion layer 4: LOCOS oxide film

5: gate oxide film 6: polycrystalline silicon layer

7: high melting point metal silicide layer 8: insulating film (first insulating film)

9: insulating film (second insulating film)

10: N type low concentration diffusion layer (N type LDD diffusion layer)

11: P-type low concentration diffusion layer (P-type LDD diffusion layer) 12: Sidewall (third insulating film)

13: N-type high concentration diffusion layer 14: P-type high concentration diffusion layer

15: interlayer insulating film, 16: metallization pattern.

[Industrial use]

The present invention relates to a method of manufacturing a highly integrated CMOS transistor with high reliability.

[Prior art]

In recent years, with the high integration of LSI, more precise manufacture of a CMOS transistor is desired. With this refinement,

1) Deterioration of transistor characteristics due to short channel effect caused by shortening of channel length of transistor

2) increase in parasitic and contact resistance caused by the formation of shallow sources and drains;

3) Increase of electrode resistance caused by miniaturization of gate electrode

Such problems are emerging.

In order to realize a finer transistor, the above problem must be solved.

However, conventionally, the heat treatment of the gate electrode and the diffusion layer doped with N-type or P-type impurities is performed at the final stage of the manufacturing process, which is a process after forming each component such as the gate electrode and the diffusion layers of the N-type and P-type impurities. The heat treatment has been performed for both the activation of the components and the planarization of the interlayer insulating film.

[Problems that the invention tries to solve]

By the way, if the heat treatment that combines the activation of each component and the planarization of the interlayer insulating film in the final manufacturing process step as described above, there is a problem as described below.

For example, in the case of a typical CMOS transistor having a polyside structure in which a high melting metal silicide layer is deposited on a polycrystalline silicon layer as a gate electrode,

1) As shown in FIG. 11, when the heat treatment temperature for the gate electrode is low, the gate electrode is depleted. Therefore, in order to activate the gate impurity, the heat treatment temperature is preferably set to a relatively high temperature (for example, 900 占 폚). As shown in FIG. 12, when the heat treatment temperature for the gate electrode is low, the sheet resistance of the gate electrode increases, so that a relatively high temperature heat treatment is also preferable to lower the resistance of the gate electrode. If the heat treatment temperature is low, there is a problem that depletion of the gate electrode occurs or the resistance of the electrode increases, resulting in deterioration of transistor characteristics.

2) Also, as shown in FIG. 13, in order to prevent the short channel effect of the transistor and the deterioration of the punch through voltage, the impurity diffusion layer forming the source or the drain is sufficiently activated and the transistor A heat treatment temperature is required such that the effective channel length does not decrease.

3) On the other hand, to form a surface channel type P channel transistor (dual gate transistor), when the gate electrode of the P channel transistor is doped with a P type impurity such as, for example, boron, the diffusion coefficient of the P type impurity is Because of the large size, when the heat treatment temperature is high, the P-type impurity penetrates through the gate oxide film and diffuses into the substrate, causing variation in the threshold voltage.

As mentioned above, in order to meet the contradictory demand for the heat treatment temperature, it is very important to perform heat treatment at the optimum heat treatment temperature for each component of the transistor.

However, the conventional gate length (design rule) does not cause any problem even if the collective heat treatment is performed. However, with the miniaturization of the CMOS transistor, there is a difference between the heat treatment temperature suitable for each component and the heat treatment temperature when the heat treatment is performed collectively. Became remarkable.

In order to improve the reliability and electrical characteristics of micro CMOS transistors whose channel length is sub-micron or less,

1) preventing depletion of the gate electrode by inactivation of gate impurities,

2) preventing the increase of short channel effect and the deterioration of punch draw voltage by reducing the effective channel length,

3) Problems such as preventing impurities of the P-type gate electrode from passing through the gate oxide film must be solved.

In the future, the above-described problems related to the miniaturization of design rules for half-micron or quarter-micron and the miniaturization of CMOS transistors have to be overcome.

The present invention provides a method of manufacturing a CMOS transistor in which the gate electrode is depleted, the short channel effect is increased, the punch draw voltage is deteriorated, and impurities of the P-type gate electrode do not penetrate the gate oxide film even when the CMOS transistor is miniaturized. It aims to provide.

[Means for solving the problem]

In order to achieve the above object, the present invention performs heat treatment for each gate electrode, heat treatment for the N-type high concentration diffusion layer and heat treatment for the P-type high concentration diffusion layer in a plurality of processes according to the design rules, The required components are subjected to high temperature heat treatment first, and the components that require relatively low temperature heat treatment are subjected to heat treatment at low temperature after the high temperature heat treatment is completed.

Specifically, the first method of manufacturing the CMOS transistor of the present invention comprises the steps of: forming a gate electrode of an N-channel transistor and a gate electrode of a P-channel transistor via a gate insulating film on a semiconductor substrate; Forming a N-type high concentration diffusion layer serving as a source or a drain of the N-channel transistor, forming a P-type high concentration diffusion layer serving as a source or a drain of the P-channel transistor, and performing an N-type heat treatment on the gate electrodes. And a step of performing at least two heat treatments, which are a heat treatment for the high concentration diffusion layer and a heat treatment for the P-type high concentration diffusion layer, independently of each other, and characterized in that the heat treatment performed later is performed at a lower temperature than the heat treatment performed first.

With this arrangement, the heat treatment for each gate, the heat treatment for the N-type high concentration diffusion layer, and the heat treatment for the P-type high concentration diffusion layer are each performed at an optimum heat treatment temperature, and depletion of the gate electrode accompanying deactivation of the gate impurities, The increase in the short channel effect due to the decrease in the effective gate channel length, the degradation of the punch draw voltage, and the tunneling of the P-type impurity into the gate oxide film can be prevented, respectively.

In addition, since the heat treatment to be performed later is performed at a lower temperature than the heat treatment to be performed first, it is possible to avoid a situation in which a high temperature heat treatment is performed after a low heat treatment is performed on a component requiring a low heat treatment temperature.

According to the first manufacturing method of the CMOS transistor, it is possible to manufacture a micro CMOS transistor of less than half micron or quarter micron having excellent electrical characteristics and reliability without failure.

A second method of manufacturing a CMOS transistor of the present invention comprises the steps of forming a gate electrode of an N-channel transistor and a gate electrode of a P-channel transistor on a semiconductor substrate with a gate insulating film interposed therebetween; Performing a heat treatment of the N-type transistor, forming a N-type high concentration diffusion layer serving as a source or a drain of the N-channel transistor using the gate electrode of the N-channel transistor as a mask, and performing the first heat treatment on the N-type high concentration diffusion layer. Performing a second heat treatment at a lower temperature, forming a P-type high concentration diffusion layer serving as a source or a drain of the P-channel transistor using the gate electrode of the P-channel transistor as a mask, and forming the P-type high concentration diffusion layer in the And performing a third heat treatment at a temperature lower than the second heat treatment. It shall be.

Therefore, since a relatively high temperature heat treatment is performed on each gate electrode that requires a relatively high temperature heat treatment for activation, depletion of the gate electrode can be prevented.

Since the heat treatment is performed at a lower temperature than that of the gate electrode in the N-type high concentration diffusion layer, deterioration of the punch draw voltage between the source and the drain of the N-channel transistor can be prevented. In addition, since the heat treatment is performed at a higher temperature than that of the P-type high concentration diffusion layer, the N-type high concentration diffusion layer can be activated even though the diffusion coefficient of the N-type impurities is relatively small.

Since the P-type high concentration diffusion layer is subjected to a lower temperature heat treatment than that of the N-type high concentration diffusion layer, deterioration of the punch draw voltage between the source and the train of the P-channel transistor can be prevented even though the diffusion coefficient of the P-type impurity is large. According to the second manufacturing method of the CMOS transistor, the micro CMOS transistor having a single drain structure can be improved in electrical characteristics and reliability.

A third method of manufacturing a CMOS transistor of the present invention comprises the steps of forming an N-channel transistor gate electrode and a gate electrode of a P-channel transistor on a semiconductor substrate via a gate insulating film, and masking the gate electrode of the N-channel transistor. Forming a N-type high concentration diffusion layer serving as a source or a drain of the N-channel transistor using the same method, performing a first heat treatment on the gate electrodes and the N-type high concentration diffusion layer, and using the gate electrode of the P-channel transistor. Forming a P-type high concentration diffusion layer serving as a source or a drain of a P-channel transistor using a mask; and performing a second heat treatment at a temperature lower than the first heat treatment of the P-type high concentration diffusion layer. It features.

Therefore, heat treatment is performed at a relatively high temperature for each gate electrode and the N-type high concentration diffusion layer that require a relatively high heat treatment temperature for activation, thereby preventing depletion of the gate electrode and activating the N-type high concentration diffusion layer.

Since a relatively low temperature heat treatment is performed on the P-type high concentration diffusion layer, deterioration of the punch draw voltage between the source and the train of the P-channel transistor can be prevented even though the diffusion coefficient of the P-type impurity is large.

According to the third manufacturing method of the CMOS transistor, the electrical characteristics and the reliability of the micro CMOS transistor having a single drain structure can be improved.

A fourth method of manufacturing a CMOS transistor of the present invention comprises the steps of forming a gate electrode of an N-channel transistor and a gate electrode of a P-channel transistor on a semiconductor substrate with a gate insulating film interposed therebetween; Heat-treatment of the N-channel transistor, forming a N-type low concentration diffusion layer serving as a source or a drain of the N-channel transistor using the gate electrode of the N-channel transistor as a mask, and performing the first heat treatment on the N-type low concentration diffusion layer. Performing a second heat treatment at a lower temperature, forming a P-type low concentration diffusion layer serving as a source or a drain of the P-channel transistor using the gate electrode of the P-channel transistor as a mask; Forming sidewalls and masking gate electrodes and sidewalls of the N-channel transistor Forming a N-type high concentration diffusion layer serving as a source or a drain of the N-channel transistor, and forming a P-type high concentration diffusion layer serving as a source or a drain of the P-channel transistor by using the gate electrodes and sidewalls of the P-channel transistor as a mask. And performing a third heat treatment to the P-type low concentration diffusion layer, the N-type high concentration diffusion layer, and the P-type high concentration diffusion layer at a lower temperature than the second heat treatment.

With this configuration, since the relatively high heat treatment is performed on each gate electrode that requires a relatively high heat treatment temperature for activation, depletion of the gate electrode can be prevented.

The N-type low concentration diffusion layer is heat-treated at a higher temperature than the P-type low concentration diffusion layer, the N-type high concentration diffusion layer, and the P-type high concentration diffusion layer, so that the impurities in the N-type low concentration diffusion layer are activated, thereby reducing the channel resistance of the N-channel transistor.

The P-type low concentration diffusion layer, the N-type high concentration diffusion layer, and the P-type high concentration diffusion layer are treated at lower temperatures than those of the N-type low concentration diffusion layer, thereby preventing deterioration of the punch draw voltage between the source and drain of the N-channel transistor and the P-channel transistor. In this way, the impurity diffusion layer can be activated.

According to the fourth method of manufacturing a CMOS transistor, an ultra-small CMOS transistor comprising an N-channel transistor and a P-channel transistor having an LDD structure excellent in electrical characteristics and reliability can be manufactured.

A fifth method of manufacturing a CMOS transistor of the present invention comprises the steps of forming a gate electrode of an N-channel transistor and a gate electrode of a P-channel transistor on a semiconductor substrate via a gate insulating film, and forming a gate electrode of the N-channel transistor. Forming a N-type low concentration diffusion layer serving as a source or a drain of the N-channel transistor using a mask, performing a first heat treatment on the gate electrodes and the N-type low concentration diffusion layer of the N-channel transistor, and P Forming a P-type low concentration diffusion layer serving as a source or a drain of the P-channel transistor using the gate electrode of the channel transistor as a mask, and forming sides on the side of the gate electrode of the N-channel transistor and the gate electrode of the P-channel transistor; Masking gate electrodes and sidewalls of the N-channel transistor Forming an N-type high concentration diffusion layer serving as a source or a drain of the N-channel transistor, and using a gate electrode and sidewalls of the P-channel transistor as a mask to form a P-type high concentration diffusion layer serving as a source or a drain of the P-channel transistor. And a step of performing a second heat treatment on the P-type low concentration diffusion layer, the N-type high concentration diffusion layer, and the P-type high concentration diffusion layer at a lower temperature than the first heat treatment.

With this configuration, since the relatively high heat treatment is performed on each gate electrode and the N-type low concentration diffusion layer that require a relatively high heat treatment temperature for activation, the depletion of the gate electrode can be prevented and the N-type low concentration diffusion layer is activated. The channel resistance of the channel transistor is reduced.

The P-type low concentration diffusion layer, the N-type high concentration diffusion layer, and the P-type high concentration diffusion layer are treated at lower temperatures than those of the N-type low concentration diffusion layer, thereby preventing deterioration of the punch draw voltage between the source and drain of the N-channel transistor and the P-channel transistor. The impurity activation of the diffusion layer can be achieved.

According to the fifth method of manufacturing a CMOS transistor, it is possible to manufacture an ultra-small CMOS transistor made of an LD-channel N-channel transistor and a P-channel transistor having excellent electrical characteristics and reliability.

A sixth method of manufacturing a CMOS transistor of the present invention comprises the steps of forming a gate electrode of an N-channel transistor and a gate electrode of a P-channel transistor on a semiconductor substrate with a gate insulating film interposed therebetween; Heat-treatment of the N-channel transistor, forming a N-type low concentration diffusion layer serving as a source and a drain of the N-channel transistor using the gate electrode of the N-channel transistor as a mask, and performing the first heat treatment on the N-type low concentration diffusion layer. Performing a second heat treatment at a lower temperature, forming a P-type high concentration diffusion layer serving as a source or a drain of the P-channel transistor using a gate electrode of the P-channel transistor as a mask, and a gate of the N-channel transistor Forming sidewalls on the side of the electrode, the gate electrode of the N-channel transistor, Forming a N-type high concentration diffusion layer serving as a source or a drain of the N-channel transistor using the walls as a mask, and performing a third heat treatment at a lower temperature than the second heat treatment for the N type high concentration diffusion layer and the P type high concentration diffusion layer. It is characterized by including the process of performing.

With this configuration, since the relatively high heat treatment is performed on each gate electrode requiring a relatively high heat treatment temperature, depletion of the gate electrode can be prevented.

The N-type low concentration diffusion layer is subjected to a second heat treatment at a higher heat treatment temperature than the third heat treatment to activate impurities in the N-type low concentration diffusion layer, thereby reducing the channel resistance of the N-channel transistor.

Since the low temperature heat treatment is performed on the N-type high concentration diffusion layer and the P-type high concentration diffusion layer than the N-type low concentration diffusion layer, it is possible to prevent deterioration of the punch draw voltage between the source and the drain of the P channel transistor and to activate impurities in the diffusion layer. have.

According to the sixth method of manufacturing the CMOS transistor, the electrical characteristics and the reliability of the ultra-small CMOS transistor including the N-channel transistor of the LDD structure and the P-channel transistor of the single drain structure are improved.

A seventh method of manufacturing a CMOS transistor of the present invention comprises the steps of forming a gate electrode of an N-channel transistor and a gate electrode of a P-channel transistor on a semiconductor substrate via a gate insulating film, and forming a gate electrode of the N-channel transistor. Forming a N-type low concentration diffusion layer serving as a source or a drain of an N-channel transistor using a mask, performing a first heat treatment on the gate electrodes and the N-type low concentration diffusion layer, and a gate of the P-channel transistor Using an electrode as a mask to form a P-type high concentration diffusion layer serving as a source or a drain of the P-channel transistor, forming sidewalls on a surface of the gate electrode of the N-channel transistor, and forming a gate electrode of the N-channel transistor. And the sidewalls as a mask, so that the source or de For the N-type process for forming a high-concentration diffusion layer and the P-type high-concentration diffusion layer and the N type high-concentration diffusion layer which is characterized in that it comprises a step of performing heat treatment of a second to a temperature lower than the heat treatment of the first.

With this configuration, since each gate electrode and the N-type low concentration diffusion layer which require a relatively high heat treatment temperature for activation are subjected to a relatively high temperature heat treatment, depletion of the gate electrode can be prevented and impurities of the N-type low concentration diffusion layer are prevented. It is activated to reduce the channel resistance of the N-channel transistor.

Since the heat treatment is performed at a lower temperature than the N-type low concentration diffusion layer for the N-type high concentration diffusion layer and the P-type high concentration diffusion layer, the deterioration of the punch draw voltage between the source and drain of the N-channel transistor and the P-channel transistor is prevented, It can be activated.

According to the seventh method of manufacturing the CMOS transistor, the electrical characteristics and the reliability of the micro CMOS transistor including the N-channel transistor of the LDD structure and the P-channel transistor of the single drain structure can be improved.

In the first to seventh manufacturing methods of CMOS transistors, the gate electrode has a laminated structure composed of polycrystalline silicon doped with N-type or P-type impurities and high melting point metal silicide loaded on the polycrystalline silicon. Micro CMOS transistors having side gate electrodes can be manufactured.

An eighth method of manufacturing the present CMOS transistor includes a step of depositing a polycrystalline silicon layer on a semiconductor substrate via a gate insulating film and then depositing a high melting metal silicide layer on the polycrystalline silicon layer, and the high melting point metal. Forming a gate electrode of an N-channel transistor and a gate electrode of a P-channel transistor by dry etching the high melting point metal silicide layer and the first insulating film after depositing a first insulating film on the silicide layer; Depositing a second insulating film on both sides of the upper surface of the field, forming a N-type low concentration diffusion layer serving as a source or a drain of the N-channel transistor using the gate electrode of the N-channel transistor as a mask, the gate electrode and Performing a first heat treatment on the N-type low concentration diffusion layer, and the P-channel transistor Using a gate electrode as a mask to form a P-type low concentration diffusion layer serving as a source or a drain of the P-channel transistor, forming sidewalls on side surfaces of the gate electrodes, and masking the gate electrode and sidewalls of the N-channel transistor Forming an N-type high concentration diffusion layer serving as a source or a drain of the N-channel transistor, and using a gate electrode and sidewalls of the P-channel transistor as a mask to form a P-type high concentration diffusion layer serving as a source or a drain of the P-channel transistor. And a step of performing a second heat treatment on the P-type low concentration diffusion layer, the N-type high concentration diffusion layer, and the P-type high concentration diffusion layer at a temperature lower than that of the first heat treatment.

With this arrangement, since the first heat treatment at a relatively high temperature is performed on the gate electrode and the N-type low concentration diffusion layer which require a relatively high heat treatment for activation, the depletion of the gate electrode can be prevented and the N-type low concentration diffusion layer is formed. Since it is activated, the channel resistance of the N-channel transistor is reduced. In this case, the first heat treatment is performed after the second insulating film is formed on the upper surface and both side surfaces of the gate electrode. In other words, the high melting point metal silicide layer constituting the polyside gate electrode is covered with the second insulating film. Therefore, abnormal oxidation to the high melting point metal silicide layer is prevented.

For the N type high concentration diffusion layer and the P type high concentration diffusion layer, the heat treatment is performed at a lower temperature than that of the N type low concentration diffusion layer, so that impurities in the diffusion layer are activated and the punch draw voltage between the source and drain of the N channel transistor and the P type transistor is activated. Deterioration can be prevented.

According to the eighth method of manufacturing the CMOS transistor, the electrical characteristics and the reliability of the ultra-small CMOS transistor having the N-channel transistor, the P-channel transistor, and the polyside gate of the LDD structure can be improved.

A ninth method of manufacturing a CMOS transistor of the present invention comprises the steps of depositing a polycrystalline silicon layer on a semiconductor substrate via a gate insulating film and then depositing a high melting point metal silicide layer on the polycrystalline silicon layer, and the high melting point metal. After depositing a first insulating film on the silicide layer, dry etching the high melting point metal silicide layer and the first insulating film to form a gate electrode of an N-channel transistor and a gate electrode of a P-channel transistor; Depositing a second insulating film on an upper surface and both sides, forming an N-type low concentration diffusion layer serving as a source or a drain of the N-channel transistor using a gate electrode of the N-channel transistor as a mask, the gate electrodes, and Performing a first heat treatment on the N-type low concentration diffusion layer, and the gate Forming sidewalls on the sides of the electrodes; forming an N-type high concentration diffusion layer serving as a source or a train of the N-channel transistor using the gate electrode and the sidewalls of the N-channel transistor as a mask; and a gate of the P-channel transistor. Forming a P-type high concentration diffusion layer serving as a source or a drain of the P-channel transistor using electrodes and sidewalls as a mask, and forming the P-type high concentration diffusion layer, the N-type high concentration diffusion layer, and the P-type high concentration diffusion layer as And performing a second heat treatment at a temperature lower than that of the heat treatment.

This configuration prevents depletion of the gate electrode and abnormal oxidation of the high melting point metal silicide because the first heat treatment is performed at the gate electrode and the N-type low concentration diffusion layer which require a relatively high heat treatment for activation. As in the above method, the channel resistance of the N-channel transistor can be reduced.

In addition, for the N-type high concentration diffusion layer and the P-type high concentration diffusion layer, a lower temperature heat treatment is performed than for the N-type low concentration diffusion layer, so that deterioration of the punch draw voltage between the source and drain of the N-channel transistor and the P-channel transistor is prevented, Impurities can be activated.

According to the ninth method of manufacturing the CMOS transistor, the electrical characteristics and the reliability of the micro CMOS transistor including the P-channel transistor of the single-drain structure, the N-channel transistor of the LDD structure, and the polyside gate electrode can be improved.

A tenth method of manufacturing a CMOS transistor comprises the steps of forming a gate electrode of an N-channel transistor and a gate electrode of a P-channel transistor via a gate insulating film on a semiconductor substrate, and an N-type high concentration on the gate electrode of the N-channel transistor. Forming an N-type gate electrode by doping an impurity, and forming an N-type high concentration diffusion layer by doping an N-type high concentration impurity in a region serving as a source or a drain of the N-channel transistor using a gate electrode of the N-channel transistor as a mask And performing a first heat treatment on the N-type gate electrode and the N-type high concentration diffusion layer, and doping a P-type high concentration impurity into the gate electrode of the P-channel transistor to form a P-type gate electrode. Using the transistor's gate electrode as a mask, the source or drain of the P-channel transistor Is a step of forming a P-type high concentration diffusion layer by doping a P-type high concentration impurity in the region, and performing a second heat treatment on the P-type gate electrode and the P-type high concentration diffusion layer at a lower temperature than the first heat treatment. It is characterized by including.

With such a structure, relatively high temperature heat treatment is performed on the N-type gate electrode and the N-type high concentration diffusion layer doped with the N-type impurity having a relatively small diffusion coefficient, so that the N-type impurities can be sufficiently activated.

In addition, the P-type gate electrode doped with a P-type impurity having a relatively large diffusion coefficient is subjected to a relatively low temperature heat treatment, so that the P-type impurity penetrates through the gate oxide film and diffuses into the N-type diffusion layer, causing the threshold voltage to fluctuate. I can prevent it.

In addition, since a relatively low temperature heat treatment is performed on the P-type high concentration diffusion layer doped with a P-type impurity having a relatively large diffusion coefficient, the punch draw voltage between the source and the drain of the P-channel transistor can be prevented.

According to the tenth method of manufacturing a CMOS transistor, the electrical characteristics and the reliability of the CMOS transistor having a single drain structure having dual gate electrodes are improved.

An eleventh method of manufacturing a CMOS transistor of the present invention comprises the steps of forming a gate electrode of an N-channel transistor and a gate electrode of a P-channel transistor on a semiconductor substrate via a gate smoke film; Forming an N-type low concentration diffusion layer serving as a source or a drain of an N-channel transistor using a mask, performing a first heat treatment on the N-type low concentration diffusion layer, and using a gate electrode of the P-channel transistor as a mask Forming a P-type low concentration diffusion layer serving as a source or a drain of the P-channel transistor, forming sidewalls on the side surfaces of the gate electrodes, and doping N-type impurities to the gate electrode of the N-channel transistor with high concentration. A gate electrode and sidewalls of the N-channel transistor Forming a N-type high concentration diffusion layer by doping N-type impurities at a high concentration in a region serving as a source or a drain of the N-channel transistor using a mask, the P-type low concentration diffusion layer, the N-type gate electrode, and the N-type high concentration diffusion layer Performing a second heat treatment at a temperature lower than that of the first heat treatment, and forming a P-type gate electrode by doping P-type impurities in a high concentration to the gate electrode of the P-channel transistor, and forming a gate of the P-channel transistor. Forming a P-type high concentration diffusion layer by doping P-type impurities at a high concentration in a region serving as a source or a drain of the P-channel transistor using electrodes and sidewalls as a mask, and for the P-type gate electrode and the P-type high concentration diffusion layer And performing a third heat treatment at a temperature lower than the second heat treatment. .

With this arrangement, since the first heat treatment at a relatively high temperature is performed for the N-type low concentration diffusion layer, the impurities in the N-type low concentration diffusion layer are fully activated and the channel resistance of the N-channel transistor is reduced. P type impurities with relatively large diffusion coefficients are doped, but P type low concentration diffusion layers with low impurity concentrations and N type impurities with relatively small diffusion coefficients are doped, and the N type gate electrode and the N type diffusion layers are slightly heated. Therefore, it is possible to accurately activate impurities in the P-type low concentration diffusion layer, the N-type gate electrode, and the N-type high concentration diffusion layer.

Since the P-type gate electrode and the P-type high concentration diffusion layer doped with P-type impurities having a relatively high diffusion coefficient are heat treated at a relatively low temperature, the P-type impurities penetrate the gate oxide film and diffuse into the N-type diffusion layer to limit the threshold voltage. This fluctuation can be prevented. At the same time, the degradation of the punch draw voltage between the source and the drain of the P-channel transistor can be prevented.

According to the eleventh method of manufacturing the CMOS transistor, the electrical characteristics and the reliability of the LDD structure CMOS transistor having dual gate electrodes can be improved.

In particular, relatively low temperature heat treatment is performed on the P-type gate electrode and the P-type high concentration diffusion layer doped with a high concentration of the P-type impurity having a relatively high diffusion coefficient, so that the P-type impurities penetrate the gate oxide film and diffuse into the N-type diffusion layer. As a result, it is possible to prevent the threshold voltage from fluctuating and to prevent the deterioration of the punch draw voltage between the source and the drain of the P-channel transistor.

EXAMPLE

Hereinafter, each embodiment of the method for manufacturing a CMOS transistor according to the present invention will be described.

The present invention is characterized in that the heat treatment at the optimum temperature is applied to each component by dividing the heat treatment process for each component of the CMOS transistor into a plurality of processes.

FIG. 6 shows the flow of each process in the method of manufacturing a CMOS transistor having a single gate (corresponding to the first, second, and third embodiments) of the CMOS transistor manufacturing method described below, and FIG. Fig. 1 shows the flow of each process in the method of manufacturing a CMOS transistor having a dual gate (corresponding to the fourth and fifth embodiments). FIG. 8 shows a heat treatment process for each component of a CMOS transistor having a single gate, and FIG. 9 shows a heat treatment process for each component of a CMOS transistor having a dual gate. FIG. 10 shows heat treatment conditions in which each component of the CMOS transistor is optimized. The relationship between the gate length indicating the fineness of the CMOS transistors and the optimum heat treatment temperature for each component is shown. For example, in this figure, the LDD structure with the gate length of 0.5 micron is 900 ° C for the LDD (low concentration diffusion layer) of the gate electrode and the N-channel transistor, and the optimum heat treatment temperature for the CMOS transistor, and the source and drain of the N-channel transistor. (High concentration diffusion layer), LDD (low concentration diffusion layer) of the P-channel transistor, and source and drain (high concentration diffusion layer) of the P-channel transistor indicate that 850 ° C is the lowest heat treatment temperature.

In the case of a CMOS transistor having a dual gate, N-type impurities are doped into the gate electrode of the N-channel transistor and P-type impurities are doped into the gate electrode of the P-channel transistor. In the heat treatment for activating the impurities doped in each gate electrode, the optimum heat treatment temperature is different depending on the N-channel transistor and the P-channel transistor.

Example 1

Hereinafter, a method of manufacturing a CMOS transistor according to a first embodiment will be described with reference to the drawings.

1 (a) to (g) are cross-sectional views showing main steps of a method of manufacturing a CMOS transistor having a single drain structure having a single gate composed of polyside gate electrodes.

First, as shown in FIG. 1A, a P type diffusion layer 2 and an N type diffusion layer 3 are respectively formed on a P type silicon substrate 1, and then a LOCOS oxide film 4 having a film thickness of about 700 nm is formed. ) And a gate oxide film 5 having a film thickness of about 20 nm are formed in predetermined regions, respectively.

Next, as shown in FIG. 1 (b), the polycrystalline silicon layer 6 is deposited to a film thickness of 250 nm by the reduced pressure CVD method. After depositing a high melting point metal silicide layer 7 such as tungsten silicide on the polycrystalline silicon layer 6 by, for example, reduced pressure CVD, N-type impurities such as arsenic are accelerated by ion implantation. 40 KeV and doped with a high melting point metal silicide layer 7 having 4 × 10 15 cm ⁻² doses. This N-type impurity diffuses and is activated in the polycrystalline silicon layer 6 in every process performed in a later process. Thereafter, a first insulating film 8 is deposited on the high melting point metal silicide layer 7 at a film thickness of 150 nm.

Next, after forming a predetermined resist pattern (not shown in the figure), gate patterning is performed using a dry etching technique as shown in FIG. At this time, the high melting point metal silicide layer 7 is exposed on the side of the gate electrode, and if the heat treatment is performed in this state, the high melting point metal silicide layer 7 causes abnormal oxidation, and thus heat treatment cannot be performed at this time.

Next, as shown in FIG. 1 (d), the second insulating film 9 is deposited to a film thickness of 20 nm. Thereafter, using the gate electrode, the first insulating film 9 (vertical portion) and the resist pattern (not shown) as a mask in the N-type channel transistor region, arsenic ions, which are N-type impurities, are accelerated by ion implantation. After forming the N-type high concentration diffusion layer 13 on the P-type diffusion layer 2 by injecting at 40 KeV and the dose amount 5 × 10 15 cm ⁻² , the first electrode for activating the gate electrode and the N-type high concentration diffusion layer 13 is performed. Heat treatment is carried out at 900 ° C. for about 20 minutes.

Next, as shown in Fig. 1 (e), ion implantation is performed using a gate electrode, a second insulating film 9 (vertical portion), and a resist pattern (not shown) as a mask in the P-type channel transistor region. In this manner, boron ions, which are P-type impurities, are implanted at an acceleration energy of 20 KeV and a dose of 5 x 10 15 cm ^-2 to form the P-type high concentration diffusion layer 14.

Next, as shown in FIG. 1 (f), after forming the interlayer insulating film 15 on the second insulating film 9, the second heat treatment is performed at 850 ° C. for activation and planarization of the interlayer insulating film 15. It is performed for 30 minutes at temperature.

Finally, as shown in FIG. 1 (g), a contact hole and a metal wiring pattern 16 are formed to obtain a single-drain CMOS transistor having a polyside gate electrode.

In order to activate the gate impurity to the extent that the depletion of the gate electrode can be prevented, a relatively high heat treatment of about 900 ° C. is required. However, after the interlayer insulating film 15 is formed, that is, after the P-type high concentration diffusion layer 14 is formed, relatively high temperature heat treatment is performed, so that a thin junction is formed because the diffusion coefficient of boron in the P-type high concentration diffusion layer 14 is large. As a result, the punch-draw voltage between the source and the drain deteriorates, making it impossible to realize a micro CMOS transistor.

Therefore, in the first embodiment, particularly, the second insulating film 9 is formed so that the high melting point metal silicide layer 7 is not exposed to the surface, and then the N-type transistor becomes the source and drain of the N-channel transistor by the first heat treatment. The high concentration diffusion layer 13 is activated and the gate electrode is activated. Thus, since the high temperature heat processing is performed after forming the 2nd insulating film 9, abnormal oxidation of the high melting metal silicide layer 7 is prevented, and an impurity activation is attained.

In addition, since the second heat treatment activates impurities in the P-type high concentration diffusion layer 14, the micro CMOS transistor can be realized.

Furthermore, as shown in FIG. 6, as a modification of the first embodiment, the first N-type high concentration diffusion layer 13 is subjected to relatively high temperature treatment after the gate electrode is formed and before the N-type high concentration diffusion layer 13 is formed. After the formation, the second heat treatment may be performed at a slightly lower temperature than the first heat treatment. In this case, the second heat treatment for the first embodiment inevitably becomes the third heat treatment.

When the gate length becomes further finer, the punch-draw voltage between the source and the drain deteriorates even in the N-type high concentration diffusion layer 13 serving as the source / drain of the arsenic-doped N-channel transistor having a relatively small diffusion coefficient. Therefore, heat treatment for forming the N-type high concentration diffusion layer 13 and heat treatment for activating the gate electrode are performed separately. After the first heat treatment, an N-type high concentration diffusion layer 13 is formed, and the heat treatment for activating the N-type high concentration diffusion layer 13 is performed at a temperature lower than that of the first heat treatment and higher than that of the third heat treatment. CMOS transistors can be realized.

Example 2

Hereinafter, a method of manufacturing a CMOS transistor according to a second embodiment will be described with reference to the drawings.

2 (a) to (j) are main cross-sectional views showing the respective steps of a method of manufacturing a LDD structure CMOS transistor having a single gate serving as a polyside gate electrode.

First, as in the first embodiment, as shown in (a), (b), and (c) in FIG. 2, the P-type diffusion layer 2 and the N-type diffusion layer 3 are formed on the P-type silicon substrate 1. , LOCOS oxide film 4, gate oxide film 5, polycrystalline silicon layer 6, high melting point metal silicide layer 7, and first insulating film 8, respectively.

Next, as shown in FIG. 2 (d), the second insulating film 9 is deposited to a film thickness of 20 nm. Next, as shown in FIG. 2E, a predetermined resist pattern (not shown) is formed, and then the resist pattern, the gate electrode, and the P-type diffusion layer 2 made of an N-channel MOS transistor are formed. Using an ion implantation method using the second insulating film 9 (vertical portion) as a mask, for example, N-type impurities such as phosphorus (p) ions are accelerated to 40KeV in dose and 4 × 1013cm in dose. After implanting at −2 to form the N type low concentration diffusion layer 10 on the P type diffusion layer 2, the first heat treatment for activation is performed at 900 ° C. for 20 minutes.

A relatively high temperature heat treatment for 20 minutes at a temperature of about 900 ° C. requires a P-type low concentration diffusion layer 11 (see FIG. 5 (c)), an N-type high concentration diffusion layer 13 (FIG. 6) It is preferable to avoid performing after the formation of a) and the P-type high concentration diffusion layer 14 (see FIG. 6 (b)). This is because the heat treatment temperature is limited to a lower temperature in the subsequent heat treatment process. At a relatively high temperature of 900 ° C., the impurities in the N-type low concentration diffusion layer 10 are activated by heat treatment for 20 minutes to reduce channel resistance, and at the same time recover the crystallinity disturbed by ion implantation, thereby improving mobility.

In particular, the gate electrode is reduced because the resistance of the gate electrode to the polycrystalline silicon layer 6 and the high melting point metal silicide layer 7 is reduced and the gate impurities are activated by a relatively high temperature heat treatment of 20 minutes at a temperature of 900 ° C. Can also prevent depletion. After a predetermined resist pattern (not shown) is formed, the resist pattern and the gate are formed on the N-type diffusion layer 3 made of a P-type channel MOS transistor as shown in FIG. 2 (f). P-type impurities such as boron ions, such as boron ions, are injected with an acceleration energy of 20 KeV and a dose of 2 x 10 13 cm ^-2 by ion implantation using the electrode and the second insulating film 9 (vertical portion) as a mask. The diffusion layer 11 is formed.

Next, an oxide film is deposited on the surface of the second insulating film 9 at a film thickness of 200 cm, and then the oxide is etched using the etch back method to the side of the gate electrode as shown in FIG. The side wall 12 is formed. At this time, since the first insulating film 8 is formed on the upper surface of the high melting point metal silicide layer 7, the upper surface of the high melting point metal silicide layer 7 is not exposed by the over-etching of about 20%. .

And the N-channel gate electrode to the transistor region, the side wall 12 and a resist pattern (not Posey in the figure) to the N-type impurity of arsenic ion is implanted by ion implantation using as a mask an acceleration energy of 40KeV, dose 5 × 1015cm ^{- The} N type high concentration diffusion layer 13 is formed by injecting ² . Next, as shown in FIG. 2 (h), a P-type impurity is formed by ion implantation using a gate electrode, sidewall 12, and resist pattern (not shown) as a mask in the P-type channel transistor region. P-type high concentration diffusion layer 14 is formed by injecting boron ions at an acceleration energy of 200 KeV and a dose of 5 × 10 15 cm ⁻² .

Next, after forming the interlayer insulating film 15 as shown in FIG. 2 (i), a second heat treatment is performed at 850 ° C. for 30 minutes for activation and planarization of the interlayer insulating film 15. Finally, as shown in FIG. 2 (j), a contact hole and a metal wiring pattern 16 are formed to obtain a LDD structure CMOS transistor having a polyside gate electrode.

In order to activate the gate impurity to the extent that the depletion of the gate electrode can be prevented, a relatively high temperature heat treatment of about 900 ° C. is required. However, in the case of a polyside gate, abnormal oxidation occurs when heat treatment is performed while the high melting point metal silicide layer 7 is exposed to the surface. Thus, according to the conventional method, heat treatment for activation of gate impurities is performed to the sidewall 12. It should not be done after the formation of the oxide film or after the formation of the interlayer insulating film 15.

In addition, when the heat treatment is performed at a relatively high temperature of about 900 ° C., the diffusion coefficient of boron in the P-type low concentration diffusion layer 11 and the P-type high concentration diffusion layer 14 is large, so that a shallow junction is not formed. This is deteriorated.

Further, when the gate length becomes less than half micron or less, even in an N-type high concentration diffusion layer 13 that is a source and drain of arsenic having a relatively small diffusion coefficient, the punch-draw voltage between the source and drain is deteriorated and is very small. CMOS transistors are impossible to realize.

In the second embodiment, in particular, the second insulating film 9 is formed so that the high melting point metal silicide layer 7 is left unexposed to the surface, so that the gate electrode is heat treated at a relatively high temperature. It is possible to prevent abnormal oxidation of the silicide layer 7 and to activate gate impurities.

In addition, since a relatively high temperature heat treatment is performed on the N-type low concentration diffusion layer 10 serving as the source and drain of the N-channel transistor, impurities in the N-type low concentration diffusion layer 10 can be sufficiently activated, thereby reducing the channel resistance. On the other hand, the activation of the P-type low concentration diffusion layer 11, the N-type high concentration diffusion layer 13, and the P-type high concentration diffusion layer 14 is performed by the second heat treatment at a relatively low temperature, so that the source of the N-channel transistor and the P-channel transistor. The punch draw voltage is not deteriorated and the micro CMOS transistor can be realized.

As shown in FIG. 6, as a modification of the second embodiment, after forming the gate electrode and before forming the N-type low concentration diffusion layer 10, a relatively high temperature of the first heat treatment is performed to activate the gate impurities to form the N-type low concentration. The diffusion layer 10 may be formed, and the N-type low concentration diffusion layer 10 may be subjected to a second heat treatment slightly lower than the first heat treatment. In this case, the second heat treatment for the second embodiment inevitably becomes the third heat treatment.

If the gate length becomes further finer, formation of a shallower junction is limited even in the N-type low concentration diffusion layer 10 serving as the source / drain of the N-channel transistor, and the punch-draw voltage between the source and the drain deteriorates. Therefore, the heat treatment for forming the N-type low concentration diffusion layer 10 and the heat treatment for activating the gate electrode are separately performed, and after the first heat treatment, the N-type low concentration diffusion layer 10 is formed, and the N-type low concentration diffusion layer is formed. Since the heat treatment for activating (10) is performed at a temperature lower than that of the first heat treatment, lower than that of the first heat treatment, the micro CMOS transistor can be realized.

Example 3

Hereinafter, a method of manufacturing a CMOS transistor according to a third embodiment will be described with reference to the drawings.

(A)-(i) is a cross-sectional view showing main steps of a method of manufacturing a CMOS transistor having a single gate serving as a polyside electrode, an N-channel transistor having an LDD structure, and a P-channel transistor having a single drain structure. .

As shown in Fig. 3 (a), (b), (c), (d) and (e), the P-type diffusion layer 2 is formed on the P-type silicon substrate 1 in the same manner as in the second embodiment. ), N-type diffusion layer 3, LOCOS oxide film 4, gate oxide film 5, polycrystalline silicon layer 6, high melting point metal silicide layer 7, first insulating film 9 and N-type low concentration diffusion layer ( 10) were respectively formed, and then the first heat treatment for activation was performed at 900 DEG C for 20 minutes.

Next, an oxide film is deposited on the surface of the second insulating film 9 at a film thickness of 200 nm, and then the oxide film is etched by using an etching method to lateral the gate electrode as shown in FIG. 3 (f). The side wall 12 is formed in the. At this time, since the first insulating film 8 is formed on the upper surface of the high melting point metal silicide layer 7, the upper surface of the high melting point metal silicide layer 7 is exposed by over-etching of about 20%. There is no work. Subsequently, a gate electrode, sidewalls 12, and a resist pattern (not shown) are used as masks in the N-type channel transistor region, and arsenic ions, which are N-type impurities, are accelerated to 40KeV and dose 5 × by ion implantation. It is injected into 1015cm ^-2 to form an N-type high concentration diffusion layer (13).

Next, as shown in Fig. 3G, a P-type impurity is formed by ion implantation using a gate electrode, sidewalls 12, and a resist pattern (not shown) as a mask in the P-type channel transistor region. Phosphorus boron ions are implanted with an acceleration energy of 20 KeV and a dose of 5 × 10 15 cm ⁻² to form a P-type high concentration diffusion layer 14.

Next, as shown in FIG. 3 (h), after the interlayer insulating film 15 is formed, a second heat treatment that combines activation and leveling of the interlayer insulating film 15 is performed at 850 ° C. for 30 minutes. Thereafter, contact holes and metal wiring patterns 16 are formed to obtain CMOS transistors as shown in FIG. 3 (i).

In order to activate the gate impurities to the extent that depletion of the gate electrode can be prevented, a relatively high temperature heat treatment of about 900 ° C is required. For example, in the case of the polyside gate, abnormal oxidation occurs when heat treatment is performed while the high melting point metal silicide layer 7 is exposed to the surface. Therefore, according to the conventional method, the second heat treatment for activation is performed by the sidewall ( 12) or after the formation of the interlayer insulating film 15.

When the heat treatment at a relatively high temperature of about 900 ° C. is performed, boron in the P-type high concentration diffusion layer 14 has a large diffusion coefficient, so that a shallow junction is not formed and the punch draw voltage between the source and the drain is deteriorated. In addition, when the gate length becomes less than half micron, the punch-draw voltage between the source and the drain deteriorates even in the N-type high concentration diffusion layer 13 which becomes the source and drain of the arsenic-doped N-channel transistor having a relatively small diffusion coefficient. This makes it impossible to realize an ultra-compact CMOS transistor.

In the third embodiment, since the second insulating film 9 is formed so that the high melting point metal silicide layer 7 is not exposed to the surface, heat treatment is performed at a relatively high temperature on the gate electrode. Abnormal oxidation of the melting point metal silicide layer 7 is prevented, and activation of gate impurities is enabled.

Since the activation of the P-type high concentration diffusion layer 14 and the N-type high concentration diffusion layer 13 is performed by a second heat treatment at a relatively low temperature, it is possible to realize a micro CMOS transistor.

As shown in FIG. 6, as a modification of the third embodiment, after the gate electrode is formed and before the N-type low concentration diffusion layer 10 is formed, the first impurities are subjected to relatively high temperature to activate the gate impurities. The type low concentration diffusion layer 10 may be formed, and the N type low concentration diffusion layer 10 may be heat treated at a slightly lower temperature than the first heat treatment. In this case, the second heat treatment for the third embodiment inevitably becomes the third heat treatment.

When the gate length becomes further finer, even in the N-type low concentration diffusion layer 10 serving as the source / drain of the N-channel transistor, the formation of a shallower junction is limited and the punch-draw voltage between the source and the drain deteriorates. Therefore, the heat treatment for forming the N-type low concentration diffusion layer 10 and the heat treatment for activating the gate electrode are separately performed, and after the first heat treatment, the N-type low concentration diffusion layer 10 is formed, and the N-type low concentration diffusion layer ( By performing a heat treatment for activating 10) at a temperature lower than that of the first heat treatment and higher than that of the third heat treatment, a more compact CMOS transistor can be realized.

Example 4

Hereinafter, a method of manufacturing a CMOS transistor according to a fourth embodiment will be described with reference to the drawings.

4 (a) to 4 (g) are cross-sectional views of main parts showing the manufacturing steps of a single-drain CMOS transistor having a dual gate serving as a polyside gate electrode.

As shown in Fig. 4A, after forming the P-type diffusion layer 2 and the N-type diffusion layer 3 on the P-type silicon substrate 1, the LOCOS oxide film 4 having a film thickness of about 700 nm is formed. ) And a gate oxide film 5 having a film thickness of about 20 nm are formed in predetermined regions, respectively.

Next, as shown in FIG. 4 (b), the polycrystalline silicon layer 6 is deposited to a thickness of 250 nm by the reduced pressure CVD method, and then, for example, tungsten silicide on the polycrystalline silicon layer 6. ) Layer 7 is formed to a film thickness of 20 nm by vacuum CVD.

After the predetermined resist pattern is formed (not shown), gate patterning is performed using a dry etching technique as shown in Fig. 4C.

Next, as shown in FIG. 4 (d), the insulating film 9 is deposited to a film thickness of 20 nm. Thereafter, an insulating film 9 (vertical portion) and a resist pattern (not shown) are used as masks in the N-type channel transistor region and the gate electrode, and arsenic ions, which are N-type impurities, are accelerated to 40KeV, By implanting at a dose of 5 x 10 15 cm ^-2 , the N-type high concentration diffusion layer 13 is formed and doping of the N-type impurity to the gate electrode of the N-channel transistor is performed.

Next, the first heat treatment for activation is performed at 900 ° C. for 20 minutes. The relatively high heat treatment for 20 minutes at the temperature of 900 ° C. cannot be doped after the P-type high concentration diffusion layer 14 is formed which requires shallow bonding. This is because, when the heat treatment is performed after the P-type high concentration diffusion layer 14 is formed, the heat treatment temperature of this heat treatment is restricted to a low temperature.

For example, if an impurity having a large diffusion coefficient, such as boron, is doped to the gate electrode of the P-channel transistor and then subjected to a relatively high temperature heat treatment, boron penetrates through the gate oxide film and diffuses into the N-type diffusion layer 3 to change the threshold voltage. This will occur. The polycrystalline silicon layer 6 is activated by performing a relatively high temperature heat treatment of about 20 minutes at a temperature of 900 DEG C for only the impurities doped in the gate electrode of the P-channel transistor, but not the impurities doped in the gate electrode of the N-channel transistor. And the resistance of the gate electrode constituted by the high melting point metal silicide layer 7 can be reduced and the depletion of the electrode can be prevented.

Next, as shown in Fig. 4E, P is implanted by ion implantation using a vertical portion of the insulating film 9 and a resist pattern (not shown) as a mask in the P-type channel CMOS transistor region and the gate electrode. P-type high concentration diffusion layer 14 is formed by injecting boron ions, which is a type impurity, with an acceleration energy of 20 KeV and a dose of 5 x 10 15 cm ^-2 .

Next, as shown in FIG. 4 (f), after forming the interlayer insulating film 15, a second heat treatment that combines activation and planarization of the interlayer insulating film 15 is performed at 850 DEG C for 30 minutes.

Finally, as shown in FIG. 4 (g), a contact hole and a metal wiring pattern 16 are formed to obtain a single-drain CMOS transistor having a dual gate serving as a polyside electrode. Since impurities such as boron introduced into the P-type high concentration diffusion layer 14 and the gate electrode of the P-type channel transistor have a large diffusion coefficient, impurities doped in the gate electrode of the P-type channel transistor are included in the N-type high concentration diffusion layer 13. And when activated by the temperature of the heat treatment for activating the doped impurities in the gate electrode of the N-type channel transistor, it becomes impossible to form a shallow junction and at the same time, the gate impurities penetrate the gate oxide film of the P-type transistor and the N-type diffusion layer. (3) is spread.

In the fourth embodiment, however, a shallow junction can be formed to activate the gate impurity of the P-type channel transistor by the second heat treatment at a relatively low temperature, so that the gate impurity does not penetrate the gate oxide film. As a result, an ultra-small dual-gate CMOS transistor having excellent characteristics in both the N-channel and the P-channel can be realized.

Example 5

Hereinafter, a method of manufacturing a CMOS transistor according to a fifth embodiment will be described with reference to the drawings.

5A to 5J are cross-sectional views of principal parts of an LDD structure CMOS transistor having a dual gate serving as a polyside gate electrode.

First, as shown in FIG. 5 (a) (b) (c), a P-type diffusion layer 2, an N-type diffusion layer 3, a LOCOS oxide film 4, and a gate oxide film on the P-type silicon substrate 1 5) After the polycrystalline silicon layer 6 and the high melting point metal silicide layer 7 are formed, gate patterning is performed using a dry etching technique.

Next, as shown in FIG. 5 (d), the insulating film 9 is deposited to a film thickness of 20 nm.

Next, as shown in FIG. 5E, a predetermined resist pattern (not shown) is formed, and then an insulating film 9 (vertical) is formed on the P-type diffusion layer 2, which is an N-type channel CMOS transistor. A) N-type impurities such as (P) ions, which are phosphorus (P) ions, are implanted with an acceleration energy of 40 KeV and a dose amount of 4 × 10 13 cm ⁻² by using the gate electrode and the resist pattern as masks, thereby forming a phase on the P-type diffusion layer 2 After the N-type low concentration diffusion layer 10 is formed in the film, the first heat treatment for activation is performed at 900 ° C for 20 minutes.

Doping after the formation of the P-type low concentration diffusion layer 11, the N-type high concentration diffusion layer 13, and the P-type high concentration diffusion layer 14, which requires a shallow junction, is performed at a relatively high temperature of 20 minutes under the temperature of 900 ° C. It is preferable. This is because when the heat treatment is performed after these diffusion layers are formed, the heat treatment temperature in this heat treatment is limited to low temperature.

For example, when a large diffusion coefficient such as boron is introduced into the gate electrode of the P-channel transistor and subjected to a relatively high temperature heat treatment, boron penetrates through the gate oxide film and diffuses into the N-type diffusion layer 3, thereby reducing the threshold voltage. Fluctuations occur. Therefore, the first heat treatment is preferably performed before impurities are introduced into the gate electrode of the P-channel transistor.

In addition, the impurity of the N-type low concentration diffusion layer 10 is activated by a relatively high temperature heat treatment of 20 minutes at a temperature of 900 ° C., thereby reducing channel resistance and restoring the crystallinity disturbed by ion implantation, thereby improving mobility.

Next, as shown in FIG. 5 (f), after forming a predetermined resist pattern (not shown), the insulating film 9 (vertical) is formed on the N-type diffusion layer 3 made of a P-type channel CMOS transistor. A) P-type low concentration diffusion layer 11 is formed by ion implantation using, for example, a gate electrode and the resist pattern as a mask, such that P-type impurities such as boron ions are made to have an acceleration energy of 20 KeV and a dose amount of 2 × 10 13 cm ⁻² . Form.

Next, an oxide film is deposited on the surface of the insulating film 9 at a film thickness of 200 cm, and then the etched film is etched using an etch back method to form sidewalls on the side surfaces of the gate electrodes as shown in FIG. (12) is formed. Subsequently, arsenic ions, which are N-type impurities, are accelerated to 40KeV by ion implantation using a gate electrode, an insulating film 9 (vertical portion), and a resist pattern (not shown) as masks in the N-type channel transistor region and the gate electrode. By implanting at a dose of 5 × 10 15 cm ⁻² , the N-type high concentration diffusion layer 13 is formed and doping of the N-type impurity to the gate electrode of the N-channel transistor is performed.

Next, a second heat treatment for activation is performed at 875 ° C. for 20 minutes. The heat treatment at a high temperature of 20 minutes under the temperature of 875 ° C cannot be doped after the P-type high concentration diffusion layer 14 is formed, which requires shallow bonding. This is because when the heat treatment is performed after the P-type high concentration diffusion layer 14 is formed, the heat treatment temperature is limited to a lower temperature in this heat treatment.

For example, if a large diffusion coefficient such as boron is doped to the gate electrode of the P-channel transistor and then subjected to a slightly high temperature heat treatment, boron penetrates through the gate oxide film and diffuses into the N-type diffusion layer 3, thereby preventing variation in the marginal voltage. Occurs. 20 minutes under the temperature of 875 DEG C, the polycrystalline silicon layer 6 is formed by only the impurities introduced into the N-channel transistor gate electrode without being activated by the impurity doped to the gate electrode of the P-channel transistor. The resistance of the gate electrode constituted by the high melting point metal silicide layer 7 can be reliably reduced and depletion of the gate electrode can be prevented.

As shown in FIG. 5 (h), the ion implantation method uses a gate electrode, an insulating film 9 (vertical portion), and a resist pattern (not shown) as a mask in a P-type channel CMOS transistor region and a gate electrode. The P-type high concentration diffusion layer 14 is formed by injecting boron ions, which are P-type impurities, at an acceleration energy of 20 KeV and a dose of 5 x 10 15 cm ^-2 .

Next, as shown in FIG. 5 (i), after the interlayer insulating film 15 is formed, a third heat treatment that combines activation and planarization of the interlayer insulating film 15 is performed at 850 ° C. for 30 minutes.

Finally, as shown in FIG. 5 (j), a contact hole and a metal wiring pattern 16 are formed to obtain a single-drain CMOS transistor having a dual gate serving as a polyside gate electrode.

Since impurities such as boron doped in the P-type high concentration diffusion layer 14 and the gate electrode of the P-type channel transistor have a large diffusion coefficient, the impurities doped in the gate electrode of the P-channel transistor are replaced with the N-type high concentration diffusion layer 13 and N. When activated by the heat treatment temperature for activating the doped impurities in the gate electrode of the type channel transistor, it is impossible to form a shallow junction, and the gate impurities penetrate the gate oxide film of the P type channel transistor and diffuse into the N type diffusion layer 3. do. By the way, in the fifth embodiment, since the gate impurities of the P-type channel transistor are activated by a slightly high temperature second heat treatment, a shallow junction can be formed, and the gate impurities do not penetrate the gate oxide film. As a result, an ultra-small dual-gate CMOS transistor having excellent characteristics in both the N-channel and the P-channel can be realized.

In the first to fifth embodiments, a CMOS transistor having a polyside gate electrode is used. Alternatively, a CMOS transistor having a polysilicon gate electrode that is usually used may be used. The same applies to a CMOS transistor having a salicide gate electrode.

Claims (18)

Forming a gate electrode of an N-channel transistor and a gate electrode of a P-channel transistor via a gate insulating film on a semiconductor substrate, forming an N-type high concentration diffusion layer serving as a source or a drain of the N-channel transistor, and a P-channel transistor Forming a P-type high concentration diffusion layer serving as a source or a drain of the N-type high concentration diffusion layer and a heat treatment of the P-type high concentration diffusion layer during heat treatment of the gate electrodes. A method of manufacturing a miniature transistor, comprising the step of performing the step, and the step of performing a later heat treatment at a lower temperature than the first heat treatment. Forming a gate electrode of an N-channel transistor and a gate electrode of a P-channel transistor through a gate insulating film on a semiconductor substrate, performing a first heat treatment on the gate electrodes, and a gate electrode of the N-channel transistor Forming an N-type high concentration diffusion layer serving as a source or a drain of an N-channel transistor using a mask, performing a second heat treatment at a temperature lower than the first heat treatment of the N-type high concentration diffusion layer, and Forming a P-type high concentration diffusion layer serving as a source or a drain of the P-channel transistor using the gate electrode of the P-channel transistor as a mask; and performing a third heat treatment at a temperature lower than that of the second heat treatment for the P-type high concentration diffusion layer. A method of manufacturing a CMOS transistor, comprising the step of performing a. Forming an N-channel transistor gate electrode and a P-channel transistor gate electrode through a gate insulating film on a semiconductor substrate, and an N-type transistor serving as a source or a drain of the N-channel transistor using the gate electrode of the N-channel transistor as a mask Forming a high concentration diffusion layer; performing a first heat treatment on the gate electrodes and the N-type high concentration diffusion layer; and using a gate electrode of the P channel transistor as a mask, P being a source or a drain of the P channel transistor. And forming a second type of high concentration diffusion layer, and performing a second heat treatment on the P-type high concentration diffusion layer at a temperature lower than that of the first heat treatment. Forming a gate electrode of an N-channel transistor and a gate electrode of a P-channel transistor via a gate insulating film on a semiconductor substrate, performing a first heat treatment on the gate electrodes, and a gate electrode of the N-channel transistor Forming an N-type low concentration diffusion layer serving as a source or a drain of an N-channel transistor using a mask, performing a second heat treatment at a temperature lower than the first heat treatment of the N-type low concentration diffusion layer, and Forming a P-type low concentration diffusion layer serving as a source or a drain of the P-channel transistor using the gate electrode of the P-channel transistor as a mask, forming sidewalls on the sides of the gate electrodes, and forming a gate electrode of the N-channel transistor; And using sidewalls as a mask, the source or drain of the N-channel transistor Is a process of forming an N-type high concentration diffusion layer, a process of forming a P-type high concentration diffusion layer serving as a source or a drain of the P-channel transistor using the gate electrodes and sidewalls of the P-channel transistor as a mask, the P-type low concentration diffusion layer, And performing a third heat treatment to the N-type high concentration diffusion layer and the P-type high concentration diffusion layer at a temperature lower than that of the second heat treatment. Forming a gate electrode of an N-channel transistor and a gate electrode of a P-channel transistor through a gate insulating film on a semiconductor substrate; and N being a source or a drain of the N-channel transistor using the gate electrode of the N-channel transistor as a mask. Forming a low concentration diffusion layer of the type, performing a first heat treatment on the N type low concentration diffusion layer of the gate electrodes and the N channel transistor, and using a gate electrode of the P channel transistor as a mask for the P channel transistor. Forming a P-type low concentration diffusion layer serving as a source or a drain, forming sidewalls on side surfaces of the gate electrode of the N-channel transistor and the gate electrode of the P-channel transistor, masking the gate electrode and sidewalls of the N-channel transistor As the source or drain of an N-channel transistor Forming a N-type high concentration diffusion layer, a process of forming a P-type high concentration diffusion layer serving as a source or a drain of the P-channel transistor using a gate electrode and sidewalls of the P-channel transistor as a mask, and the P-type low concentration diffusion layer And performing a second heat treatment on the N-type high concentration diffusion layer and the P-type high concentration diffusion layer at a temperature lower than that of the first heat treatment. Forming a gate electrode of an N-channel transistor and a gate electrode of a P-channel transistor through a gate insulating film on a semiconductor substrate, performing a first heat treatment on the gate electrodes, and a gate electrode of the N-channel transistor Forming an N-type low concentration diffusion layer serving as a source or a drain of an N-channel transistor using a mask, performing a second heat treatment at a temperature lower than the first heat treatment of the N-type low concentration diffusion layer, and Forming a P-type high concentration diffusion layer serving as a source or a drain of the P-channel transistor using the gate electrode of the P-channel transistor as a mask, forming sidewalls on the side of the gate electrode of the N-channel transistor, and The gate electrode and sidewalls of the transistor are used as a mask to Forming a N-type high concentration diffusion layer serving as a drain or a drain, and performing a third heat treatment on the N-type high concentration diffusion layer and the P-type high concentration diffusion layer at a lower temperature than the second heat treatment. Method for manufacturing a transistor. Forming a gate electrode of the N-channel transistor and a gate electrode of the P-channel transistor by interposing a gate insulating film on the semiconductor substrate; and N, which is a source or a drain of the N-channel transistor, using the gate electrode of the N-channel transistor as a mask. Forming a type low concentration diffusion layer, performing a first heat treatment on the gate electrodes and the N type low concentration diffusion layer, and using a gate electrode of the P channel transistor as a mask to obtain a source or a drain of the P channel transistor. Forming a P-type high concentration diffusion layer; forming sidewalls on a side surface of the gate electrode of the N-channel transistor; and using a gate electrode and sidewalls of the N-channel transistor as a mask. Forming an N-type high concentration diffusion layer to be P-type high-concentration diffusion layer and for the N-type high concentration diffusion layer of the CMOS transistor manufacturing method comprising the step of performing a heat treatment at a second temperature lower than the heat treatment of the first. The method of claim 1, wherein the gate electrodes have a stacked structure including polycrystalline silicon doped with N-type or P-type impurities and high melting point metal silicide stacked on the polycrystalline silicon. Depositing a high-crystalline metal silicide layer on the polycrystalline silicon layer after depositing a polycrystalline silicon layer on the semiconductor substrate via a gate insulating film; and depositing a first insulating film on the high-melting metal silicide layer after the high melting point Dry etching the metal silicide layer and the first insulating film to form a gate electrode of an N-channel transistor and a gate electrode of a P-channel transistor, depositing a second insulating film on upper and both sides of the gate electrodes; Forming an N-type low concentration diffusion layer serving as a source or a drain of the N-channel transistor using the gate electrode of the N-channel transistor as a mask, performing a first heat treatment on the gate electrode and the N-type low concentration diffusion layer, and P-channel transistor using the gate electrode of the P-channel transistor as a mask Forming a P-type low concentration diffusion layer serving as a source or a drain, forming sidewalls on side surfaces of the gate electrodes, and using a gate electrode and sidewalls of the N-channel transistor as a mask, Forming a N-type high concentration diffusion layer, a process of forming a P-type high concentration diffusion layer serving as a source or a drain of the P-channel transistor using a gate electrode and sidewalls of the P-channel transistor as a mask, the P-type low concentration diffusion layer, And performing a second heat treatment on the N-type high concentration diffusion layer and the P-type high concentration diffusion layer at a temperature lower than that of the first heat treatment. Optimizing a high melting point metal silicide layer on said polycrystalline silicon layer after depositing a polycrystalline silicon layer on said semiconductor substrate via a gate insulating film; and depositing a first insulating film on said high melting point metal silicide layer, and then Dry etching the metal silicide layer and the first insulating film to form a gate electrode of an N-channel transistor and a gate electrode of a P-channel transistor, depositing a second insulating film on upper and both sides of the gate electrodes; Forming an N-type low concentration diffusion layer serving as a source or a drain of the N-channel transistor using the gate electrode of the N-channel transistor as a mask, and performing a first heat treatment on the gate electrodes and the N-type low concentration diffusion layer. And forming sidewalls on side surfaces of the gate electrodes; Forming an N-type high concentration diffusion layer serving as a source or a drain of the N-channel transistor by using the gate electrode and sidewalls of the null transistor as a mask; and a source of the P-channel transistor using the gate electrode and the sidewall of the P-channel transistor as a mask. Or forming a P-type high concentration diffusion layer to be drained, and performing a second heat treatment on the P-type low concentration diffusion layer, the N-type high concentration diffusion layer, and the P-type high concentration diffusion layer at a lower temperature than the first heat treatment. A method of manufacturing a CMOS transistor, characterized in that. Forming a gate electrode of the N-channel transistor and a gate electrode of the P-channel transistor through a gate insulating film on the semiconductor substrate, and forming an N-type gate electrode by doping N-type high concentration impurities into the gate electrode of the N-channel transistor; Forming an N-type high concentration diffusion layer by doping an N-type high concentration impurity in a region serving as a source or a drain of the N-channel transistor using a gate electrode of the N-channel transistor as a mask, the N-type gate electrode and the N-type Performing a first heat treatment on the high concentration diffusion layer, doping a P-type high concentration impurity into the gate electrode of the P-channel transistor to form a P-type gate electrode, and using the gate electrode of the P-channel transistor as a mask P-type high concentration impurities are doped in the region serving as the source or drain of the transistor to Forming a high concentration diffusion layer, and performing a second heat treatment on the P-type gate electrode and the P-type high concentration diffusion layer at a lower temperature than the first heat treatment. . Forming a gate electrode of an N-channel transistor and a gate electrode of a P-channel transistor through a gate insulating film on a semiconductor substrate; and N serving as a source or a drain of the N-channel transistor by using the gate electrode of the N-channel transistor as a mask. A step of forming a type low concentration diffusion layer, a step of performing a first heat treatment on the N type low concentration diffusion layer, and a P type low concentration diffusion layer serving as a source or a drain of the P channel transistor using a gate electrode of the P channel transistor as a mask Forming an N-type gate electrode by doping N-type impurities at a high concentration into the gate electrode of the N-channel transistor, and forming a gate electrode of the N-channel transistor. And using the sidewalls as a mask, the source of the N-channel transistor or Forming a N-type high concentration diffusion layer by doping N-type impurities at a high concentration in a region to be a lane, and a temperature lower than that of the first heat treatment for the P-type low concentration diffusion layer, the N-type gate electrode, and the N-type high concentration diffusion layer. Performing a second heat treatment, and doping P-type impurities to the gate electrode of the P-channel transistor at a high concentration to form a P-type gate electrode, and using the gate electrode and sidewalls of the P-channel transistor as a mask. Using a gate electrode and sidewalls of the transistor as a mask to form a P-type high concentration diffusion layer by doping a P-type impurity at a high concentration in a region serving as a source or a drain of the P-channel transistor, the P-type gate electrode and the P-type high concentration Including a step of subjecting the diffusion layer to a third heat treatment at a lower temperature than the second heat treatment. Method of manufacturing a CMOS transistor of a gong. 3. The method of claim 2, wherein the gate electrodes have a stacked structure consisting of polycrystalline silicon doped with N-type or P-type impurities and high melting point metal silicide deposited on the polycrystalline silicon. The method of claim 3, wherein the gate electrodes have a stacked structure including polycrystalline silicon doped with N-type or P-type impurities and high melting point metal silicide loaded on the polycrystalline silicon. 5. The method of claim 4, wherein the gate electrodes have a stacked structure consisting of polycrystalline silicon doped with N-type or P-type impurities and high melting point metal silicide stacked on the polycrystalline silicon. 6. The method of claim 5, wherein the gate electrodes have a stacked structure consisting of polycrystalline silicon doped with N-type or P-type impurities and high melting point metal silicide deposited on the polycrystalline silicon. The method of claim 6, wherein the gate electrodes have a stacked structure including polycrystalline silicon doped with N-type or P-type impurities and high melting point metal silicide stacked on the polycrystalline silicon. 8. The method of claim 7, wherein the gate electrodes have a stacked structure comprising polycrystalline silicon doped with N-type or P-type impurities and high melting point metal silicide stacked on the polycrystalline silicon.