JPH06275788A - Manufacture of dual gate cmos semiconductor device - Google Patents

Abstract

PURPOSE:To suppress the diffusion of boron by lowering process temperature and also, prevent the partial cavity growth or resistance increase of a p-type polysilicon gate electrode when manufacturing a dual gate CMOS type semiconductor device. CONSTITUTION:An n-type conductive polysilicon film 15, where n-type impurities exist uniformly within a film, is formed on the gate oxide film 14 on a silicon substrate 10, and it is changed into a p-type polysilicon film by implanting ions of boron into the polysilicon film 15 in a PMOSFET type region. Gate electrodes 17a and 17b are formed by patterning the polysilicon films 15a and 15b. Then, for both MOSFETs, impurities are implanted into a board with gate electrodes as masks. The temperature of activation of implanted impurities is set rather low at 800-900 deg.C.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a MOS type semiconductor device, and more particularly to a P channel type MOS (hereinafter referred to as PMO).
A dual-gate CMOS semiconductor device in which an S-type element has a P-type conductive polysilicon gate electrode, and an N-channel type MOS (hereinafter referred to as NMOS) element has an N-type conductive polysilicon gate electrode. C having a fine pattern of, for example, submicron or less
The present invention relates to a method for manufacturing a MOS semiconductor device.

[0002]

2. Description of the Related Art Generally, semiconductor integrated circuit devices (hereinafter referred to as L
The process called SI) tends to increase in the number of steps as miniaturization progresses. Further, in the process of MOS type LSI, various problems such as a short channel effect and a hot carrier effect occur as miniaturization progresses.

NMOSFET and PMOSFE on the same substrate
In a T-formed CMOS device, an N ⁺ polysilicon gate electrode is widely used as a polysilicon gate electrode. This is a polysilicon gate electrode in which phosphorus glass is deposited on a polysilicon film and phosphorus is diffused into the polysilicon film by heat treatment to reduce the resistance.
In such a CMOS device, the NMOSFET side is often a surface channel type and the PMOSFET side is a buried channel type in many cases.

However, when the miniaturization progresses and the process becomes submicron or less or half micron or less, it becomes difficult to suppress the short channel effect in the buried type structure.
The PMOSFET side is also in a situation where it has no choice but to shift to the surface type. In that case, P is newly added for the PMOSFET side.
⁺ Polysilicon gate electrode (reduction of resistance of the polysilicon gate electrode by acceptor injection), and adoption of salicide structure for connecting N ⁺ polysilicon gate electrode and P ⁺ polysilicon gate electrode, etc. The number is increasing.

Further, in adopting the P ⁺ polysilicon gate electrode, the resistance of the gate electrode must be reduced by using an impurity implantation method. However, during implantation or activation of the implanted impurity, implantation into the gate electrode is performed. The generated impurities may penetrate the gate oxide film and enter the channel portion of the substrate. If impurities enter the channel portion, the threshold voltage shifts and various problems such as breakdown voltage deterioration occur, and desired MOSFET characteristics cannot be obtained.

[0006]

Boron introduced for the P-type polysilicon gate electrode has a large diffusion coefficient in the gate oxide film and changes the channel concentration of the MOSFET.
It changes the threshold voltage. In order to solve the problem, a method of lowering the process temperature to suppress the diffusion of boron is effective. However, when the process temperature is lowered, the diffusion of arsenic and phosphorus introduced into the N-type polysilicon gate is suppressed to more than boron, and there is a problem that the N-type polysilicon gate electrode is partially depleted or the resistance is increased.
As a result, the threshold voltage of the NMOSFET is changed and the high speed operation of the CMOS device is hindered.

The problems associated with lowering the process temperature are:
In particular, in the process of forming the source region and the drain region by self-alignment using the gate electrode of the NMOSFET as a mask, it becomes more important in the process of simultaneously introducing the impurity into the gate electrode and the impurity into the substrate. This is because it is desired to realize a shallower impurity concentration profile in the source region and the drain region, and the requirements conflict with the introduction into the gate electrode. SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a dual gate CMOS type semiconductor device capable of suppressing the diffusion of boron by lowering the process temperature and preventing partial depletion and high resistance of the N type polysilicon gate electrode. It is what

[0008]

The present invention includes the following steps (A) to (D). (A) A step of forming an N-type conductive polysilicon film on a silicon substrate through a gate oxide film, (B) a resist covering the N-channel MOS type element forming region, Introducing a P-type impurity into the silicon film to form the P channel
Changing the polysilicon film in the OS type element formation region to P type conductivity; and (C) patterning the polysilicon film to form an N channel type MOS element formation region and a P channel type MOS.
A step of forming a gate electrode in each of the element formation region,
(D) A step of introducing impurities of respective conductivity types in order to form at least the source region and the drain region on the substrate of the N-channel type MOS element forming region and the P-channel type MOS element forming region.

In a preferred embodiment, the N-type impurity concentration of the N-type conductive polysilicon film formed in the above step (A) is set lower than the concentration required for the gate electrode,
In the above step (B), a small amount of P-type impurities is injected when the polysilicon film in the P-channel MOS type element formation region is changed to P-type conductivity. In the N-channel MOS type element forming region, N type impurities are further injected into the polysilicon film to increase the concentration to a level required as a gate electrode.

In another preferred embodiment, the above step (A)
The N-type impurity concentration of the N-type conductive polysilicon film formed in step 1 is set to a concentration lower than that required for the gate electrode, the polysilicon film is patterned to form a gate electrode pattern, and then the source region and the drain are formed. At the same time as the impurity is injected into the substrate for forming the region, the impurity is also injected into the gate electrode to reduce the resistance of the gate electrode.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a first embodiment. (A) P well 11 and N well 1 on the silicon substrate 10
2. A field oxide film 13 and a gate oxide film 14 are formed. An N-type conductive polysilicon film 15 is formed on the gate oxide film 14. The polysilicon film 15 can be formed by the CVD method in which phosphorus or arsenic is added to the reaction gas. Another method of forming the N-type conductive polysilicon film 15 is to use a CV method for a polysilicon film into which impurities are not introduced.
This is a method of depositing by the D method, ion-implanting phosphorus or arsenic, and then sufficiently activating it. Polysilicon film 15
Has N-type impurities uniformly present in the film. The amount of N-type impurities at this time is a concentration necessary to prevent depletion of the N-type polysilicon gate electrode, and is a level that can be changed to P-type conductivity by introducing P-type impurities in a later step. Is the concentration of. Therefore, although the optimum range of the N-type impurity concentration in the polysilicon film 15 varies depending on the selection of process conditions, it is 1 × 10 ¹⁹ to 2 × 10 ²⁰ / cm.
A range of ³ is suitable. An example of the N-type polysilicon film 15 is LPCVD using disilane and phosphine as reaction gases.
It is a phosphorus-doped polysilicon film formed by the method and has a film thickness of about 3500Å.

(B) The NMOSFET formation region is covered with a photoresist film 16, and boron is ion-implanted into the polysilicon film 15 in the PMOSFET formation region. The boron implantation amount at this time is set to be at least twice, preferably about four times, the amount of impurities in the polysilicon film 15. As a result, the polysilicon film 15 is divided into an N-type polysilicon film 15a in a region covered with the photoresist film 16 and a P-type polysilicon film 15b converted to P-type.

(C) After removing the photoresist film 16, the photoresist film is formed again, and the polysilicon films 15a and 15b are patterned by photolithography and etching to form the gate electrodes 17a and 17b. Then, according to a known process, N-type impurities such as arsenic or phosphorus are introduced into the substrate by self-alignment using the gate electrode 17a as a mask for the NMOSFET, and P-type self-alignment by using the gate electrode 17b as the mask for the PMOSFET.
Boron, a type impurity, is introduced into the substrate.

The impurities introduced into the gate electrodes 17a and 17b may be activated by a heat treatment before being patterned in the step (C) or may be activated after being patterned. Further, it may be performed simultaneously with the activation of the impurities introduced into the source region / drain region. Activation temperature is 8
The temperature is from 00 to 900 ° C, preferably from 800 to 850 ° C.

FIG. 2 shows a second embodiment. (A) A polysilicon film 25 is formed as in FIG. In this case, the impurity concentration of the polysilicon film 25 is at least 1 × 10 ¹⁹ , preferably 5 × 10 ¹⁹ / cm ³ . In this case also, the impurities are uniformly present in the polysilicon film 25. (B) The polysilicon film 25 is patterned by known photolithography and etching to form a gate electrode 27.

(C) The PMOSFET formation region is covered with the photoresist film 26, and N-type impurities are ion-implanted into the NMOSFET formation region. As a result, impurities are simultaneously introduced into the gate electrode 27a and the source / drain region 28 of the NMOSFET, so that the resistance of the gate electrode 27a is lowered and the source / drain region 28 is formed at the same time. After removing the photoresist film 26, activation is performed. A shallow impurity introduction region is formed in the source / drain region 28, while the impurities introduced into the gate electrode 27a are unevenly distributed only in the vicinity of the surface if the gate electrode 27a has a normal film thickness. From the beginning has N-type conductivity, the threshold voltage fluctuation of NMOSFET and CMOS
There is no problem with the operating speed of the device.

(D) Contrary to the above step (C), the NMO
The SFET formation region is covered with a photoresist film 29, and P-type impurities are ion-implanted to simultaneously reduce the resistance of the gate electrode 27b of the PMOSFET and form the source / drain regions 30. After removing the photoresist film 29, activation is performed. At this time, since the polarity of the P-type impurity implantation is required to determine the polarity of the gate electrode 27b from the initial N-type conductivity to the P-type conductivity, at least twice as much as the N-type impurity amount of the polysilicon film 25, Preferably 4
Set to double. Since the P-type impurity, boron, diffuses quickly in the polysilicon film, the gate electrode 27b uniformly exhibits P-type conductivity. However, if the activation temperature is too high, the problem of change in the channel concentration of the MOSFET occurs, so the activation temperature is 800 to 900 ° C., preferably 800.
~ 850 ° C or lower.

FIG. 3 shows a CMOS having a dual gate structure formed by using the process shown in FIG. C in FIG.
In order to manufacture a MOS device, a P well 11, an N well 12, a field oxide film 13 and a gate oxide film 14 are formed according to FIG. 2, and then an N type polysilicon film 25 is formed. The polysilicon film 25 has a thickness of 3500 formed by the LPCVD method using disilane and phosphine as reaction gases.
Å This is a phosphorus-doped polysilicon film having a phosphorus concentration of 5 × 10 ¹⁹ / cm ^{3 in} the film. The polysilicon film 25 is patterned to form a gate electrode 27.

Next, using the photoresist film as a mask, N
The gate electrode 27a and the source / drain region 28 of the MOSFET and the substrate contact region 36 of the N well 12
Arsenic is ion-implanted into the substrate. Injection energy is 30 Ke
V and dose amount is 1 × 10 ¹⁵ / cm ² . 90 after this
Perform activation for 30 minutes at 0 ° C. Next, the photoresist film is re-formed, and BF ₂ is ion-implanted into the gate electrode 27b and the source / drain region 30 of the PMOSFET and the substrate contact region 37 of the P well 11 using the photoresist film as a mask. Injection energy is 2
The dose is 0 KeV and the dose is 3 × 10 ¹⁵ / cm ² . Thereafter, activation is performed at 850 ° C. for 30 minutes.

Next, titanium silicide 38 is formed on the gate electrode, source region, drain region and substrate contact of both MOSFETs by a salicide self-alignment process by a known process. Next, after forming the interlayer insulating film 39, a contact hole is opened and a metal electrode 40 is formed.

As a comparative example, a CMOS device was formed by the same process as described with reference to FIG. 3, using a non-doped polysilicon film into which impurities were not introduced. The process of the comparative example is a conventional process. Figure 3
FIG. 4 shows the result of comparing the threshold voltages of the example of FIG.
Shown in. In PMOSFET, there is no difference between the example and the comparative example. However, in the case of NMOSFET, the comparative example has a larger value, and it is expected that the N-type polysilicon gate electrode of the comparative example is partially depleted.

Therefore, an NMOSFE having a large gate area
A high frequency CV measurement was performed using T at a frequency of 1 MHz. In the case of the example, an oxide film capacity that matches the calculated value was detected. On the other hand, in the case of the comparative example, only about half the calculated value of the oxide film capacity was detected. From this, it is considered that the polysilicon gate electrode of the comparative example is partially depleted, and therefore the response to high frequencies is deteriorated.

[0023]

The dual gate C manufactured according to the present invention
Since the process temperature of the MOS device is kept low, the problem that the channel concentration of the MOSFET changes due to the diffusion of boron in the P-type polysilicon gate electrode and the threshold voltage changes does not occur. Further, since impurities are made to exist uniformly in the N-type polysilicon gate electrode in advance, the problem of insufficient diffusion due to the low process temperature does not occur.

[Brief description of drawings]

FIG. 1 is a process sectional view showing a first embodiment.

FIG. 2 is a process sectional view showing a second embodiment.

FIG. 3 is a cross-sectional view showing a CMOS device manufactured by the process of FIG.

FIG. 4 is a diagram of a threshold voltage comparing an example with a conventional example.

[Explanation of symbols]

 10 Silicon Substrate 11 P Well 12 N Well 14 Gate Oxide Film 15, 15a, 25 N-type Polysilicon Film 15b P-type Polysilicon Film 17a, 27a N-type Polysilicon Gate Electrode 17b, 27b P-type Polysilicon Gate Electrode 28,30 Source / drain regions

Claims (3)

[Claims] 1. A method of manufacturing a dual-gate CMOS semiconductor device including the following steps (A) to (D). (A) A step of forming an N-type conductive polysilicon film on a silicon substrate through a gate oxide film, (B) a resist covering the N-channel MOS type element forming region, A step of introducing a P-type impurity into the silicon film to change the polysilicon film in the P-channel MOS type element formation region into a P-type conductivity; (C) patterning the polysilicon film to form an N-channel type MOS element formation region A step of forming a gate electrode in each of the P-channel type MOS element forming region, and (D) in order to form at least a source region and a drain region on the substrate of the N-channel type MOS element forming region and the P-channel type MOS element forming region, A step of introducing impurities of each conductivity type. 2. A method for manufacturing a dual gate CMOS semiconductor device, which includes the following steps (A) to (E). (A) A step of forming an N-type conductive polysilicon film having a concentration lower than that required for a gate electrode on a silicon substrate through a gate oxide film, (B) a P-channel MOS type element forming region is covered with a resist A step of introducing an N-type impurity into the polysilicon film in the N-channel MOS type element formation region to make the polysilicon film in the N-channel MOS type element formation region a N-type conductivity of a required concentration as a gate electrode, C) The N-channel MOS type element formation region is covered with a resist, P-type impurities are introduced into the polysilicon film of the P-channel MOS type element formation region, and the polysilicon film of the P-channel MOS type element formation region is used as a gate electrode. Changing the P-type conductivity to a required concentration, (D) patterning the polysilicon film to form an N-channel type MOS element forming region and a P-channel type MOS element A step of forming a gate electrode in the formation region, and (E) forming at least a source region and a drain region on the substrate of the N-channel type MOS element forming region and the P-channel type MOS element forming region, respectively. Step of introducing impurities. 3. A method of manufacturing a dual gate CMOS semiconductor device, which includes the following steps (A) to (D). (A) A step of forming an N-type conductive polysilicon film having a concentration lower than that required for a gate electrode on a silicon substrate via a gate oxide film, (B) patterning the polysilicon film to form an N-channel type A step of forming a gate electrode in each of the MOS element formation region and the P-channel type MOS element formation region, and (C) implantation of N-type impurities into the substrate for forming a source region and a drain region of the N-channel type MOS device. At the same time, a step of injecting N-type impurities into the gate electrode of the N-channel type MOS device to make the gate electrode of the N-channel type MOS device have N-type conductivity of a required concentration as a gate electrode, (D) P-channel type At the same time when P-type impurities are implanted into the substrate for forming the source region and the drain region of the MOS element, the P-type impurity is also implanted into the gate electrode of the P-channel type MOS element. Step of changing the gate electrode of the P-channel type MOS device in the P-type conductivity required concentration as a gate electrode by implanting,