KR19980030449A - Manufacturing Method of CMOS Transistor - Google Patents

Abstract

The present invention relates to a method of manufacturing a CMOS transistor that can reduce the defects caused by the process by reducing the process step, thereby increasing the manufacturing yield of the device and significantly improving productivity. Providing a semiconductor substrate having a type well formed therein and a device isolation film formed on an upper predetermined portion thereof, sequentially forming a polysilicon film containing a gate insulating film and a first conductivity type impurity on the device isolation film and the semiconductor substrate, Converting the polysilicon film on the first conductivity type well region to the second conductivity type, etching the polysilicon film and the gate insulating film to form respective gate electrodes on the first and second well regions, and Forming each junction region in a second well region.

Description

Manufacturing Method of CMOS Transistor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a CMOS transistor that can improve manufacturing yield and productivity by reducing process steps.

1A to 1D are cross-sectional views illustrating a method of manufacturing a conventional CMOS transistor.

First, as shown in FIG. 1A, in order to optimize PMOS and NMOS transistors in the semiconductor substrate 1, P-wells 2 and N-wells 3 are formed by known methods, and P-wells ( 2) and a field oxide film 4 for separation between the junction portion of the N-well 3 and other elements is formed by a known LOCOS (LOCal Oxidation of Silicon) method.

Subsequently, the gate oxide film 5 and the polysilicon film 6 which is a gate electrode material are sequentially deposited on the field oxide film 4 and the semiconductor substrate 1. Then, the first mask pattern 7 is formed to mask the polysilicon film 6 on the P-well 2 region through photolithography, and the polysilicon film on the exposed N-well 3 region ( Inject p-type impurity in 6).

As shown in FIG. 1B, the first mask pattern 7 is removed by a known method, and then the second mask pattern 7 is masked to mask the polysilicon film 6 over the N-well 3 region through photolithography. 8) and n-type impurities are implanted into the polysilicon film 6 on the exposed P-well 2 region.

As shown in FIG. 1C, a polysilicon film, which is a gate electrode material into which n-type and p-type impurities are implanted, is removed by removing the second mask pattern 8 by a known method and then performing a predetermined first annealing. 6) improve the conduction characteristics.

Subsequently, the polysilicon layer 6 and the gate oxide layer 5 are patterned by photolithography and etching to form gate electrodes 6A and 6B on the P-well 2 and N-well 3 regions, respectively. .

As shown in FIG. 1D, a third mask pattern (not shown) is formed over the N-well 3 region, and the gate electrode 6A is formed as an ion implantation mask in the exposed P-well 2 region. The third mask pattern is removed after implanting n-type low concentration impurities. Subsequently, a fourth mask pattern (not shown) is formed on the P-well 2 region, and the p-type low concentration impurity is formed using the gate electrode 6A as an ion implantation mask in the exposed N-well 3 region. After injection, the fourth mask pattern is removed.

Then, a thick oxide film is deposited on the entire structure, and the oxide film is anisotropically blanket-etched to form spacers 9A and 9B on both sidewalls of each of the gate electrodes 6A and 6B.

Then, a fifth mask pattern (not shown) is formed on the N-well 3 region again, and the n-type high concentration impurity is formed by using the spacer 9A as an ion implantation mask in the exposed P-well 2 region. After the injection of the fifth mask pattern is removed. Subsequently, a sixth mask pattern (not shown) is formed on the P-well 2 region, and a spacer 9B is used as an ion implantation mask in the exposed N-well 3 region to form a high p-type impurity. After the injection, the sixth mask pattern is removed.

Then, a predetermined second annealing is performed to form junction regions 10A and 10B having a lightly doped drain (LDD) structure in the P-well 2 and N-well 3 regions, thereby forming PMOS and NMOS transistors. Complete the CMOS transistor.

However, the above-described conventional method for manufacturing a CMOS transistor has the following problem.

In order to inject n-type and p-type impurities into the gate electrode, a two-step mask process is performed according to the formation of the first and second mask patterns, and an impurity and a junction region formed in the gate electrode material are formed. Each annealing process is performed on impurities implanted into the N-well and P-well regions. Accordingly, the residue of the mask pattern, which is not removed by the repeated mask process, remains in the polysilicon film to generate defects after annealing, thereby reducing the manufacturing yield of the device.

In addition, due to the complexity of the process according to the repeated mask process and annealing process as described above there is a problem that the productivity is greatly reduced.

Accordingly, the present invention has been made in view of the above-described problems, and by reducing the process step, the CMOS transistor can reduce the defects caused by the process, thereby increasing the manufacturing yield of the device and greatly improving productivity. The purpose is to provide a manufacturing method.

1A to 1D are cross-sectional views for explaining a method of manufacturing a conventional CMOS transistor.

2A to 2D are cross-sectional views illustrating a method of manufacturing a CMOS transistor according to an embodiment of the present invention.

3A and 3B are cross-sectional views illustrating a method of manufacturing a CMOS transistor according to another embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

11 semiconductor substrate 12 P-well

13: N-well 14: field oxide film

15 gate insulating film 16 polysilicon film

17 silicide film 19 spacer

20: junction area

According to an aspect of the present invention, there is provided a method of fabricating a CMOS transistor, the method comprising: providing a semiconductor substrate having a first and a second conductivity type well formed therein and an element isolation layer formed on an upper predetermined portion thereof; Sequentially forming a polysilicon film containing a gate insulating film and a first conductivity type impurity on the semiconductor substrate, converting the polysilicon film over the first conductivity type well region into a second conductivity type, the polysilicon film and Etching the gate insulating film to form respective gate electrodes on the first and second well regions, and forming respective junction regions on the first and second well regions.

The converting of the polysilicon film into the second conductive type may include: masking the polysilicon layer on the second conductive well region and forming a mask pattern to expose the polysilicon layer on the first conductive well region; And implanting a second conductivity type impurity into the exposed polysilicon layer on the exposed first conductivity type well region and removing the mask pattern.

In the forming of the junction region, annealing of the gate electrode material into which the first and second conductivity-type impurities are injected may be performed simultaneously.

According to the present invention having the above structure, the annealing is simultaneously performed after the ion implantation according to the junction region formation without performing annealing on the impurity-injected gate electrode material, and the mask process according to the impurity implantation of the gate electrode material Can be reduced to step 1.

EXAMPLE

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.

2A to 2D are cross-sectional views illustrating a method of manufacturing a CMOS transistor according to an embodiment of the present invention.

First, as shown in FIG. 2A, in order to optimize PMOS and NMOS transistors in the semiconductor substrate 11, P-wells 12 and N-wells 13 are formed by known methods, and P-wells ( 12) and a field oxide film 14 for separation between the junction portion of the N-well 13 and other elements is formed by a known LOCOS (LOCal Oxidation of Silicon) method.

Subsequently, the gate oxide film 15 and the polysilicon film 16 which is a gate electrode material are sequentially deposited on the field oxide film 14 and the semiconductor substrate 11, and the polysilicon film 16 is improved to improve the conductivity of the gate electrode. ) Is doped with n-type impurities using POCl ₃ gas.

As shown in FIG. 2B, the first mask pattern 18 is formed to mask the polysilicon layer 16 on the P-well 12 region through photolithography, and the exposed N-well 13 region. The p-type impurity, preferably B, is injected into the upper polysilicon film 16 to convert the n-type injected polysilicon film 16 to the p-type. In other words, since B has a smaller amount of activity than P, which is an n-type source, and has a high activity, the n-type doped polysilicon film 16 can be easily converted to p-type.

As shown in FIG. 2C, the P-well 12 is removed by removing the first mask pattern 18 by a known method, and patterning the polysilicon layer 16 and the gate oxide layer 15 by photolithography and etching processes. And gate electrodes 16A and 16B are formed on the N-well 13 region, respectively.

As shown in FIG. 2D, a second mask pattern (not shown) is formed on the N-well 13 region, and the gate electrode 16A is formed as an ion implantation mask in the exposed P-well 12 region. The second mask pattern is removed after implanting a low concentration of n-type impurities. Subsequently, a third mask pattern (not shown) is formed on the P-well 12 region, and the p-type low concentration impurity is formed using the gate electrode 16A as an ion implantation mask in the exposed N-well 13 region. After injection, the third mask pattern is removed.

Then, a thick oxide film is deposited on the entire structure, and the oxide film is anisotropically blanket-etched to form spacers 19A and 19B on both sidewalls of each of the gate electrodes 16A and 16B.

Then, a fourth mask pattern (not shown) is formed on the N-well 13 region again, and the n-type high concentration impurity is formed by using the spacer 19A as an ion implantation mask in the exposed P-well 2 region. After injection, the fourth mask pattern is removed. Subsequently, a fifth mask pattern (not shown) is formed on the P-well 12 region, and the p-type high concentration impurity is formed by using the spacer 19B as an ion implantation mask in the exposed N-well 13 region. After the injection, the sixth mask pattern is removed.

Then, a predetermined annealing is performed to diffuse the p-type and n-type impurities injected into the respective gate electrodes 16A and 16B, and LDD in the P-well 12 and N-well 13 regions. By forming the junction regions 20A and 20B of the structure, a CMOS transistor composed of PMOS and NMOS transistors is completed.

In addition, the above method may be applied to a CMOS process having a gate electrode having a silicide formed on a polysilicon layer, which will be described through another embodiment of the present invention.

3A and 3B are cross-sectional views illustrating a method of manufacturing a CMOS transistor having a gate electrode having a polyside structure according to another exemplary embodiment of the present invention. The description will be omitted.

First, as shown in FIG. 3A, the field oxide film 14 is formed on the semiconductor substrate 11 on which the P-well 12 and the N-well 13 are formed, and then the field oxide film 14 and the semiconductor substrate ( 11) A gate oxide film 15 is formed on the top.

Subsequently, the polysilicon layer 16 is first deposited on the gate oxide layer 15 using a gate electrode material, and the polysilicon layer 16 is impurity doped using POCl ₃ gas to improve conductivity. The silicide film 17 is deposited on the silicon film 16.

Then, the mask pattern 17 is formed to mask the silicide layer 17 on the P-well 12 region and the p-type impurity is implanted.

As shown in FIG. 3B, gate electrodes are formed on the P-well 12 and N-well 13 regions, respectively, and low and high concentration impurities are formed using the gate electrodes and spacers 19A and 19B. Inject into well 12 and N-well 13 regions, respectively.

Then, a predetermined annealing is performed to diffuse the p-type and n-type impurities injected into the respective gate electrodes, and lightly doped drain (LDD) in the P-well 12 and N-well 13 regions. By forming the junction regions 20A and 20B of the structure, a CMOS transistor including a gate electrode having a polyside structure composed of PMOS and NMOS transistors is completed.

According to the above embodiment, the annealing is simultaneously performed after the ion implantation following the formation of the junction region without separately performing annealing on the impurity-injected gate electrode material, and the mask process according to the impurity implantation of the gate electrode material is performed in one step. It is possible to reduce the defects generated by the repeated process by reducing the, thereby improving the manufacturing yield of the device.

In addition, as the mask process and the annealing process are reduced compared to the conventional process, it is possible to greatly improve the productivity.

In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.

As described above, according to the present invention, it is possible to realize a method of manufacturing a CMOS transistor which can improve manufacturing yield and productivity by reducing the process steps.

Claims (6)

Providing a semiconductor substrate having a first and a second conductivity type well formed therein and having an element isolation film formed in an upper predetermined portion; a poly-containing film including a gate insulating film and a first conductivity type impurity on the device isolation film and the semiconductor substrate Sequentially forming a silicon film, converting a polysilicon film on the first conductivity type well region to a second conductivity type, etching the polysilicon film and the gate insulating film on the first and second well regions, respectively Forming a gate electrode and forming a junction region in said first and second well regions, respectively. The method of claim 1, wherein the converting of the polysilicon film to the second conductivity type comprises: masking a polysilicon film over the second conductivity type well region and exposing a polysilicon film over the first conductivity type well region; Forming a second conductive impurity into the exposed polysilicon layer on the exposed first conductive well region; and removing the mask pattern. The method of claim 1, wherein the forming of the junction region comprises simultaneously annealing the gate electrode material into which the first and second conductivity type impurities are respectively implanted. The method of claim 1, further comprising forming a silicide layer on the gate electrode material between the implanting the first conductivity type impurity and forming the mask pattern. Way. The method of claim 1, wherein the implantation of the impurity is performed using POCl ₃ gas when the conductivity type is n-type. The method of claim 1, wherein the impurity is B when the conductivity type is p-type.