JP2000208640A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manufacture a semiconductor device in less processes with high accuracy wherein a pMOS transistor and nMOS transistor are provided on the same substrate with a first conductive type transistor's gate electrode which is a first conductive type, while a second conductive type transistor's gate electrode which is a second conductive type. SOLUTION: After a first silicon film 16 is deposited with boron which is a doped p-type impurity, a non-doped second silicon film 17 is deposited, forming a two-layer gate electrode. Then, arsenic ions are implanted with a POS side masked with a resist, while boron ions are implanted with an NMOS side masked with a resist, and thermally processed for diffusing impurities in a gate/drain region and gate electrode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device in which transistors of a first conductivity type and a transistor of a second conductivity type are formed on the same substrate, and more particularly, to a method of manufacturing a gate electrode of a transistor of the first conductivity type. The present invention relates to a method for manufacturing a semiconductor device in which a transistor of the first conductivity type is used and a gate electrode of a transistor of the second conductivity type is used in the second conductivity type.

[0002]

2. Description of the Related Art A complementary MOS transistor (CMOS transistor) in which an n-type MOS transistor (NMOS) and a p-type MOS transistor (PMOS) are formed on the same substrate has both n-type and p-type transistors turned on. Since the current flows only when the power consumption becomes low, the power consumption is low, and miniaturization and high integration are easy, and it is generally used widely.

In such a CMOS transistor, an n-type polysilicon film to which an n-type impurity such as phosphorus or arsenic is added has been used for both an NMOS gate electrode and a PMOS gate electrode. However, in recent years, N
In order to make the threshold voltage symmetrical between the MOS and the PMOS and lower the voltage, a PMOS gate electrode is being used instead of an n-type polysilicon film instead of a p-type polysilicon film. A CMOS transistor including such an NMOS having a gate electrode containing an n-type impurity and a PMOS having a gate electrode containing a p-type impurity is called a dual-gate CMOS transistor.

As a method for introducing an impurity into a polysilicon layer serving as a gate electrode, a thermal diffusion method, an ion implantation method, or a method of adding an impurity gas to an atmosphere during silicon deposition (hereinafter, this method is referred to as an in-situ method) Doping) is known.

In a dual gate type CMOS transistor, an impurity is generally introduced into a polysilicon layer serving as a gate electrode by an ion implantation method. For example, NM
The polysilicon layer serving as the gate electrode of the OS has a PMOS
N regions such as phosphorus and arsenic are implanted in a state where the region is masked with a resist, and a polysilicon layer serving as a gate electrode of the PMOS is implanted with a p-type material such as boron or boron difluoride in a state where the NMOS region is masked with the resist. Type impurity ions are implanted.

[0006]

When boron ions are implanted into a polysilicon layer serving as a gate electrode of a PMOS, part of the boron ions is trapped in crystal grain boundaries of the polysilicon layer during thermal diffusion after the implantation. Therefore, the activation rate of the implanted boron ions decreases. Therefore, when boron ions are implanted into a polysilicon layer serving as a gate electrode of a PMOS, a large amount of boron ions must be implanted to reduce the resistance value. However, when a large amount of boron ions are implanted into the polysilicon layer serving as the gate electrode, boron in the gate electrode is diffused and taken into the gate oxide film during heat treatment performed during activation of the source / drain regions. Further, there arises a problem that the boron penetrates through the gate oxide film and diffuses into the silicon substrate, so that the threshold voltage of the PMOS varies and the reliability of the gate oxide film is reduced.

Therefore, a conventional dual gate type CMO
In the case of manufacturing an S transistor, it is necessary to implant boron ions into the polysilicon layer serving as the gate electrode of the PMOS while solving these conflicting problems. It was difficult.

As a method of avoiding such a problem as boron penetration caused by ion implantation, it is conceivable to introduce an impurity into a polysilicon layer serving as a gate electrode by in-situ doping. In the in-situ doping, boron gas or boron difluoride gas is added to the atmosphere during the deposition of polysilicon, so that impurities are efficiently incorporated into the polysilicon crystal, and an equivalent amount of boron is obtained with a smaller amount of boron than ion implantation. Activation rates can be achieved. Therefore, when impurities are introduced into the polysilicon layer by in-situ doping, there is no problem such as boron penetration during subsequent thermal diffusion.

However, when the gate electrode is formed by in-situ doping, the entire surface of the silicon substrate becomes a p-type electrode. Therefore, dual gate type CMO
When forming the gate electrode in the NMOS region of the S transistor, the p-type polysilicon layer formed by in-situ doping is peeled off and a polysilicon layer is deposited again, and then n-type impurities are introduced by ion implantation or the like. There must be. Therefore, a very large number of steps have been required for manufacturing.

The present invention has been made in view of such circumstances, and has a first conductivity type transistor and a second conductivity type transistor on the same substrate, and has a gate of the first conductivity type transistor. Provided is a method for manufacturing a semiconductor device in which a semiconductor device having an electrode of a first conductivity type and a gate electrode of a transistor of a second conductivity type of a second conductivity type can be manufactured with a small number of steps and with high reliability. With the goal.

[0011]

In order to solve the above-mentioned problems, a method of manufacturing a semiconductor device according to the present invention is to provide a method of manufacturing a semiconductor device having a first conductive type region and a second conductive type region. A method for manufacturing a semiconductor device having a film formed thereon, wherein a first silicon film doped with a first conductivity type impurity is formed on a semiconductor substrate on which the insulating film is formed. Forming a second silicon film on the first silicon film to which a first conductivity type impurity is added at a concentration lower than that of the first conductivity type impurity added to the first silicon film; A second silicon film formation step, a first ion implantation step of implanting a second conductivity type impurity ion into the second silicon film formed on the first conductivity type region, The second silicon layer formed on the region of the second conductivity type. Relative emission layer, characterized in that it comprises a second ion implantation step of implanting impurity ions of the first conductivity type.

In the method for manufacturing a semiconductor device according to the present invention, two types of first and second conductivity type transistors are provided on one semiconductor substrate, and the first conductivity type transistor is a first conductivity type transistor. A semiconductor device in which a gate electrode is formed and a second conductivity type transistor is formed in the second conductivity type transistor. For example, a CMOS in which an nMOS transistor and a pMOS transistor are provided on one semiconductor substrate, and an n-type impurity is introduced into a gate electrode of the nMOS transistor and a p-type impurity is introduced into a gate electrode of the pMOS transistor This is for manufacturing a type transistor.

In the present invention, the gate electrode of each conductivity type transistor is formed as follows.

First, silicon doped with a first conductivity type impurity is deposited on a semiconductor substrate to form a first silicon film. In the first silicon film, a high activation rate can be obtained with an extremely small amount of impurities as compared with a case where impurities are implanted by ion implantation. For example, a first silicon film is formed on a semiconductor substrate by adding a p-type impurity gas such as boron to deposit silicon.

Subsequently, non-doped silicon is deposited on the first silicon film to form a second silicon film. The second silicon film does not need to contain any impurities, but only needs to be lower than the impurity concentration of the first silicon film.

In the present invention, in order to form a gate electrode, first, a silicon film having a two-layer structure is formed as described above.

Subsequently, in the present invention, a second conductivity type impurity is ion-implanted into the second silicon film in the first conductivity type region to be a second conductivity type transistor. For example, nMOS
An n-type impurity ion such as phosphorus or arsenic is implanted into the second silicon film in the transistor region.

Subsequently, in the present invention, an impurity of the first conductivity type is ion-implanted into the second silicon film in the region of the second conductivity type which becomes a transistor of the first conductivity type. For example, pMOS
P-type impurity ions such as boron are implanted into the second silicon film in the transistor region.

By the ion implantation as described above, the first conductivity type transistor is provided with the first silicon film (lower layer) deposited by adding the first conductivity type impurity gas and the first conductivity type transistor. A gate electrode having a two-layer structure including the second silicon film (upper layer) into which impurities are ion-implanted is formed. For example, in a pMOS transistor, a first silicon film (lower layer) deposited by adding boron as a p-type impurity, and a second silicon film (upper layer) ion-implanted with boron as a p-type impurity The gate electrode having a two-layer structure is formed.

The second conductivity type transistor has a first silicon film (lower layer) deposited by adding a first conductivity type impurity gas, and a second silicon type impurity ion-implanted second silicon film. A gate electrode having a two-layer structure including two silicon films (upper layers) is formed. For example, an nMOS transistor has a first silicon film (lower layer) deposited by adding boron as a p-type impurity and a second silicon film (ion-implanted with phosphorus or arsenic as an n-type impurity). ) Is formed.

Here, the gate electrode having such a two-layer structure is thereafter subjected to a heat treatment to diffuse the implanted ions.

At this time, in the gate electrode of the transistor of the first conductivity type, impurities of the first conductivity type have already been efficiently introduced into the first silicon film. Therefore, even if the amount of the first conductivity type impurity implanted into the second silicon film is small, a first conductivity type gate electrode having a high activation rate as a whole can be formed. For example, since a p-type impurity, boron, is introduced into a silicon film below a gate electrode of a pMOS transistor at the time of deposition, a high activation rate can be obtained. Therefore, even if the amount of boron ions, which are p-type impurities, implanted into the upper silicon film is small, a p-type gate electrode having a high activation rate as a whole can be formed.

In the gate electrode of the second conductivity type transistor, the first conductivity type impurity is introduced into the first silicon film. By ion implantation, an n-type gate electrode can be formed.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A method of manufacturing a dual gate CMOS transistor according to a first embodiment of the present invention will be described.

In the method of manufacturing a dual gate CMOS transistor according to the first embodiment of the present invention, first, as shown in FIG. 1, the steps up to the formation of a silicon oxide film are performed in a conventional manner. That is, an element isolation oxide film 12 is formed on a silicon substrate (Si) 11. Next, a p-type well (p-well) 13 is formed in a region where an n-type MOS transistor (NMOS) is formed on the silicon substrate 11, and a p-type MOS transistor (PMO) on the silicon substrate 11 is formed.
An n-type well (n-well) 1 is formed in a region where S) is formed.
4 is formed. Next, the silicon substrate 11 is thermally oxidized.
A 5 nm-thick silicon oxide film 15 is formed thereon.

Subsequently, as shown in FIG. 2, silicon is deposited on the entire surface of the silicon substrate 11 on which the silicon oxide film 15 and the element isolation oxide film 12 are formed by CVD, and a first silicon film having a thickness of 30 nm is formed. A film 16 is formed.
At this time, boron which is a p-type impurity is introduced into the deposited silicon layer by in-situ doping. That is, silicon is deposited by adding an impurity gas (boron) into the atmosphere. The conditions of the in-situ doping at this time are as follows.

Atmosphere: SiH ₄ (500 sccm) + B ₂ H ₆
(50 sccm) Temperature: 680 ° C. Pressure: 50 Torr (6.7 × 10 ³ Pa) Boron concentration: 5 × 10 ¹⁹ cm ⁻³ Film thickness: 30 nm

Since the temperature is as high as 680 ° C., the first silicon film 16 becomes polysilicon at the time of deposition.

Subsequently, as shown in FIG. 3, non-doped silicon is deposited on the first silicon film 16 by CVD to form a second silicon film 17 having a thickness of 70 nm. The silicon deposition conditions at this time are as follows.

Atmosphere: SiH ₄ (500 sccm) Temperature: 680 ° C. Pressure: 50 Torr (6.7 × 10 ³ Pa) Film thickness: 70 nm

Since the temperature is as high as 680 ° C., the second silicon film 17 becomes polysilicon at the time of deposition. Further, the deposition of the second silicon film 17 may be performed immediately after the deposition of the first silicon film 16 or may be performed at a predetermined time interval.

Subsequently, as shown in FIG. 4, a resist pattern is formed by photolithography and development processing, the first silicon film 16 and the second silicon film 17 are anisotropically etched, and the gate electrode is patterned. I do. In addition,
The gate electrode formed on the NMOS region is referred to as an nMOS gate electrode 18, and the gate electrode formed on the pMOS region is referred to as a pMOS gate electrode 19.

Subsequently, as shown in FIG. 5, the PMOS region is covered with a resist 21 and the arsenic ions (A
s ⁺ ) is implanted under the conditions of 15 keV and 1 × 10 ¹³ cm ⁻² , and n serving as a low-concentration impurity diffusion region in the LDD structure is formed.
^- -type source / drain regions. The arsenic ions are also implanted into the second silicon film 17 of the nMOS gate electrode 18.

Subsequently, after removing the resist 21, FIG.
As shown in FIG. 2, the NMOS region is covered with a resist 22 and P
10k a ^- (BF ₂₎ boron difluoride ions in the MOS region
Implantation is performed under the conditions of eV and 1 × 10 ¹⁴ cm ⁻² to form p ⁻ -type source / drain regions which become low-concentration impurity diffusion regions in the LDD structure. This boron difluoride ion is also implanted into the second silicon film 17 of the pMOS gate electrode 19.

Subsequently, after the resist 22 is removed, the CV
D, a silicon oxide film of about 100 nm is deposited on the silicon substrate 11 and then etched back to form an nMOS gate electrode 18 and a pMOS gate electrode 19 formed from the first silicon film 16 and the second silicon film 17. A sidewall oxide film 23 is formed on the side wall of.

Subsequently, as shown in FIG. 7, the PMOS region is covered with a resist 24, and the arsenic ions (A
s ⁺⁾ was implanted under the conditions of ^{30keV, 1 × 10 16 cm -2} , to form an n ⁺ -type source / drain region comprising a high concentration impurity diffused region of the NMOS. The arsenic ions are also implanted into the second silicon film 17 of the nMOS gate electrode 18.

Subsequently, after removing the resist 24, FIG.
As shown in the figure, the NMOS region is covered with a resist 25,
5 keV, 2 × 1 boron ions (B ⁻ ) in the MOS region
Implantation is performed under the condition of 0 ¹⁵ cm ^-2 to form p ⁺ -type source / drain regions which become high-concentration impurity diffusion regions of the PMOS.
The boron ions are also implanted into the second silicon film 17 of the pMOS gate electrode 19.

Subsequently, after removing the resist 25, 10
A rapid heat treatment at about 100 ° C. for about 10 seconds is performed to activate the impurities implanted in the source / drain regions.

Here, the second of the nMOS gate electrode 18 into which impurities were not introduced at the time of silicon deposition.
Implanted into the silicon layer 17 of FIG.
In FIG. 7), a large amount of arsenic ions is introduced. Arsenic ions introduced into the second silicon layer 17 are much higher than boron ions introduced into the first silicon layer 16 by in-situ doping. Therefore, when the rapid heat treatment is performed here, arsenic ions (n-type impurities) introduced into the second silicon layer 17 diffuse from the second silicon film 17 to the first silicon film 16 and the first silicon Membrane 1
Boron ions (p-type impurities) introduced by the in-situ doping of No. 6 are canceled out, and an n ⁺ -type polysilicon layer is formed as a whole.

Further, a boron ion implantation step (FIG. 6) is performed on the second silicon layer 17 of the pMOS gate electrode 19 into which no impurity has been introduced at the time of silicon deposition.
In FIG. 8), boron ions are introduced. This second silicon layer 17 is deposited on the first silicon layer 17 into which boron ions have been introduced by in-situ doping. Since the second silicon layer 17 has boron ions introduced by in-situ doping, a high activation rate is obtained with a small amount of boron. Therefore, even if the amount of boron ions implanted into the second silicon layer 17 is small, the pMOS gate electrode 19 as a whole has a low resistance p +
A polysilicon layer is formed, and boron does not penetrate into the gate oxide film 15 during the heat treatment.

By the manufacturing steps described above, as shown in FIG. 9, the nMOS gate electrode 18 made of an n ⁺ type polysilicon layer, the n ⁻ type source / drain region 26 and the n ⁺ type source / drain region 27 are formed. An NMOS composed of:
pMOS gate electrode 1 made of p ⁺ type polysilicon layer
9 and p ^- -type source / dual gate CMOS transistor PMOS and has formed composed of the drain region 28 and the p ⁺ -type source / drain regions 29. can be manufactured.

As described above, in the first embodiment of the present invention, after the first silicon film 16 is deposited by adding boron which is a p-type impurity, the non-doped second silicon film 1 is deposited.
7 are formed to form a two-layer gate electrode to manufacture a dual-gate CMOS transistor. As a result, in the first embodiment of the present invention, the step of removing the p-type polysilicon layer formed by in-situ doping is not performed, and the resistance of the PMOS gate electrode 19 of the PMOS can be reduced. Furthermore, PMOS PMOS
The penetration of boron into the gate oxide film during thermal diffusion of the gate electrode 19 does not occur, and the penetration of boron into the gate electrode, which is a problem of the prior art, can be avoided.

In the first embodiment of the present invention, a silicide film may be formed on the second silicon film 17 to reduce the resistance of the gate electrode.

(Second Embodiment) Next, a method of manufacturing a dual gate CMOS transistor according to a second embodiment of the present invention will be described.

In the method of manufacturing a dual gate CMOS transistor according to the second embodiment of the present invention, as shown in FIG. 10, the steps up to the formation of a silicon oxide film are performed in a conventional manner.
That is, an element isolation oxide film 32 is formed on a silicon substrate (Si) 31. Next, the n-type M on the silicon substrate 31
A p-type well (p-well) 33 is formed in a region where an OS transistor (NMOS) is formed, and a silicon substrate 3 is formed.
An n-type well (n-well) 34 is formed in a region where a p-type MOS transistor (PMOS) is formed.
Next, a film thickness of 5 nm is formed on the silicon substrate 31 by thermal oxidation.
Of silicon oxide film 35 is formed.

Subsequently, as shown in FIG. 11, silicon is deposited on the silicon substrate 31 on which the silicon oxide film 35 and the element isolation oxide film 32 are formed by CVD, and a first silicon film 36 having a thickness of 20 nm is formed. To form At this time, boron which is a p-type impurity is introduced into the deposited silicon layer by in-situ doping. That is, silicon is deposited by adding an impurity gas (boron) into the atmosphere. The conditions of the in-situ doping at this time are as follows.

Atmosphere: SiH ₄ (500 sccm) + B ₂ H ₆
(50 sccm) Temperature: 530 ° C. Pressure: 100 Torr (1.3 × 10 ⁴ Pa) Boron concentration: 5 × 10 ¹⁹ cm ⁻³ Film thickness: 20 nm

Since the temperature is as low as 530 ° C., the first silicon film 36 becomes amorphous silicon during deposition.

Subsequently, as shown in FIG. 12, non-doped silicon is deposited on the first silicon film 36 by CVD to form a second silicon film 37 having a thickness of 50 nm. The silicon deposition conditions at this time are as follows.

Atmosphere: SiH ₄ (500 sccm) Temperature: 530 ° C. Pressure: 100 Torr (1.3 × 10 ⁴ Pa) Film thickness: 50 nm

Since the temperature is as low as 530 ° C., the second silicon film 37 becomes amorphous silicon during deposition. Further, the deposition of the second silicon film 37 is as follows.
It may be performed immediately after the first silicon film 36 is deposited, or may be performed at a predetermined time interval.

Subsequently, as shown in FIG. 13, the PMOS region is covered with a resist 41, and phosphorus ions (P ⁺ ) are applied to the second silicon film 37 in the NMOS region at 10 keV and 8 × 1.
Inject under the condition of 0 ¹⁵ cm ^-2 .

Subsequently, after removing the resist 41, FIG.
As shown in FIG. 4, the NMOS region is covered with a resist 42,
Boron ions (B ⁻ ) are implanted into the second silicon film 37 in the PMOS region under the conditions of 5 keV and 1.5 × 10 ¹⁵ cm ⁻² .

Subsequently, after the resist 42 is removed, heat treatment is performed to crystallize the first silicon layer 36 and the second silicon layer 37 made of amorphous silicon. The conditions of the heat treatment are as follows.

Atmosphere: N ₂ temperature: 700 ° C. Time: 1 hour Here, the second silicon layer 37 in the NMOS region into which impurities were not introduced at the time of silicon deposition,
A large amount of phosphorus ions are introduced in the phosphorus ion implantation step (FIG. 13). The amount of phosphorus ions introduced into the second silicon layer 37 is much larger than the amount of boron ions introduced into the first silicon layer 36 by in-situ doping. Therefore, when heat treatment is performed here, phosphorus ions (n-type impurities) introduced into the second silicon layer 37 diffuse from the second silicon film 37 to the first silicon film 36, and the first silicon film 36 The boron ions (p-type impurities) introduced by the in-situ doping are canceled to form an n ⁺ -type polysilicon layer as a whole.

Further, boron ions have been introduced into the second silicon layer 37 in the PMOS region into which impurities have not been introduced at the time of silicon deposition in the boron ion implantation step (FIG. 14). The second silicon layer 37 is deposited on the first silicon layer 36 into which boron ions have been introduced by in-situ doping. This second
Since boron ions are introduced into the silicon layer 37 by in-situ doping, a high activation rate is obtained with a small amount of boron. Therefore, the second silicon layer 37
Even if the amount of boron ions implanted into the gate electrode of the PMOS is small, a p + -type polysilicon layer having a low resistance is formed as a whole on the gate electrode of the PMOS, and the penetration of boron into the gate oxide film 35 during the heat treatment is prevented. Does not occur.

Subsequently, as shown in FIG. 15, tungsten silicide is deposited on the polysilicon-converted second silicon layer 37 by CVD to form a tungsten silicide film 43 having a thickness of 70 nm. By forming the tungsten silicide film 43, the wiring resistance of the gate electrode can be reduced. The silicon deposition conditions at this time are as follows.

Atmosphere: SiH ₄ (400 sccm) + WF ₆
(4 sccm) + Ar (300 sccm) Temperature: 400 ° C. Pressure: 1 Torr (1.3 × 10 ² Pa) Film thickness: 70 nm Here, the silicide to be deposited is not limited to tungsten silicide, but may be other silicide. Is also good. Also, a refractory metal such as tungsten is deposited on the second silicon layer 3.
7 may be deposited.

Subsequently, as shown in FIG. 16, a resist pattern is formed by photolithography and development processing.
The first silicon film 36, the second silicon film 37, and the tungsten silicide film 43 are anisotropically etched to pattern the gate electrode. The gate electrode formed on the NMOS region is referred to as an nMOS gate electrode 44, and has a pM
The gate electrode formed on the OS region is referred to as a pMOS gate electrode 45.

Subsequently, as shown in FIG. 17, the PMOS region is covered with a resist 46, and arsenic ions (As ⁺ ) are implanted into the NMOS region under the conditions of 15 keV and 1 × 10 ¹³ cm ⁻² , and the low density in the LDD structure is obtained. An n ⁻ -type source / drain region serving as a high-concentration impurity diffusion region is formed.

Subsequently, after removing the resist 46, FIG.
As shown in FIG. 8, the NMOS region is covered with a resist 47,
Boron difluoride ions in the PMOS region (BF ₂ ^-) 10
Implantation is performed under the conditions of keV and 1 × 10 ¹⁴ cm ⁻² to form p ⁻ -type source / drain regions which become low-concentration impurity diffusion regions in the LDD structure.

Subsequently, after removing the resist 47, the CV
D, a silicon oxide film of about 100 nm is deposited on the silicon substrate 31 and then etched back to form an nMOS gate electrode 44 and a pMOS gate electrode 45 formed from the first silicon film 36 and the second silicon film 37. A sidewall oxide film 51 is formed on the side wall.

Subsequently, as shown in FIG. 19, the PMOS region is covered with a resist 52, and arsenic ions (As ⁺ ) are implanted into the NMOS region under the conditions of 30 keV and 1 × 10 ¹⁵ cm ⁻² , and the high concentration of NMOS is An n ⁺ type source / drain region serving as an impurity diffusion region is formed.

Subsequently, after removing the resist 52, FIG.
0, the NMOS region is covered with a resist 53,
Boron ions in the PMOS region (B ^-) and 5 keV, 2 ×
10 ^{1 5} implanted under conditions of cm ^-2, to form the p ⁺ -type source / drain region comprising a high concentration impurity diffusion regions of the PMOS.

Subsequently, after removing the resist 53, 10
A rapid heat treatment at about 100 ° C. for about 10 seconds is performed to activate the impurities implanted in the source / drain regions.

According to the above-described manufacturing process, the nMOS gate electrode 44 composed of the tungsten silicide film 43 and the n ⁺ type polysilicon layer 54 as shown in FIG.
, N ⁻ type source / drain region 56 and n ⁺ type source /
An NMOS composed of a drain region 57, a tungsten silicide film 43, and ap ⁺ type polysilicon layer 5
5 and a p ^- type source /
Drain region 58 and p ⁺ type source / drain region 59
Dual gate C having a PMOS composed of
MOS transistors can be manufactured.

As described above, in the second embodiment of the present invention, after the first silicon film 36 is deposited by adding boron as a p-type impurity, the non-doped second silicon film 3 is formed.
7 are formed to form a two-layer gate electrode to manufacture a dual-gate CMOS transistor. Thus, in the second embodiment of the present invention, there is no step of removing the p-type polysilicon layer formed by in-situ doping, and the resistance of the PMOS gate electrode 45 of the PMOS can be reduced. Furthermore, PMOS PMOS
The penetration of boron into the gate oxide film during the thermal diffusion of the gate electrode 45 does not occur, and the penetration of boron into the gate electrode, which is a problem of the prior art, can be avoided.

[0068]

According to the method of manufacturing a semiconductor device according to the present invention, a first silicon film deposited by adding a first conductivity type impurity and a non-doped silicon film deposited on the first silicon film are formed. A gate electrode is formed using a two-layer structure of the second silicon film and a first conductivity type transistor and a first conductivity type transistor are formed over the same substrate. That is, in the region of the transistor of the first conductivity type, a first silicon film deposited by adding an impurity of the first conductivity type and a second silicon film ion-implanted with the impurity of the first conductivity type are formed. Is formed.
A first silicon film deposited by adding an impurity of the first conductivity type to a region of the transistor of the second conductivity type;
A gate electrode having a two-layer structure composed of a second silicon film into which impurities of the second conductivity type are ion-implanted is formed.

Thus, according to the present invention, a transistor of the first conductivity type and a transistor of the second conductivity type are provided on the same substrate, and the gate electrode of the transistor of the first conductivity type is set to the first conductivity type. A semiconductor device in which the gate electrode of the transistor of the second conductivity type is the second conductivity type can be manufactured with a small number of steps and with high reliability. For example, in the present invention, a semiconductor device can be manufactured without an impurity such as boron penetrating into a gate oxide film during heat treatment and without removing a silicon film formed for forming a gate electrode. it can.

[Brief description of the drawings]

FIG. 1 shows a dual gate M according to a first embodiment of the present invention.
FIG. 9 is a schematic cross-sectional view showing a state after forming an element isolation layer, a P-type well, an N-type well, and a silicon oxide film on a silicon substrate in a method for manufacturing an OS transistor.

FIG. 2 is a schematic sectional view showing a state in which a first silicon film is formed on the silicon oxide film of FIG.

FIG. 3 is a schematic sectional view showing a state where a second silicon film is formed on the first silicon film in FIG. 2;

FIG. 4 is a schematic cross-sectional view showing a state in which a gate electrode is patterned by etching a first silicon film and a second silicon film of FIG. 3;

5 is a schematic cross-sectional view showing a state where ions are implanted by masking an NMOS region of the silicon substrate of FIG. 4 with a resist.

6 is a schematic cross-sectional view showing a state where ions are implanted by masking a PMOS region of the silicon substrate of FIG. 5 with a resist.

FIG. 7 is a diagram showing a side wall formed on the gate electrode of FIG. 6;
FIG. 4 is a schematic cross-sectional view showing a state where ions are implanted by masking a PMOS region with a resist.

8 is a schematic cross-sectional view showing a state where ions are implanted while masking a PMOS region of the silicon substrate of FIG. 7 with a resist.

FIG. 9 is a schematic cross-sectional view of a dual-gate MOS transistor completed in the first embodiment of the present invention.

FIG. 10 shows a method of manufacturing a dual-gate MOS transistor according to a second embodiment of the present invention, after forming an element isolation layer, a P-type well, an N-type well, and a silicon oxide film on a silicon substrate. It is a typical sectional view showing a state.

11 is a schematic cross-sectional view showing a state in which a first silicon film is formed on the silicon oxide film of FIG.

FIG. 12 is a schematic cross-sectional view showing a state where a second silicon film is formed on the first silicon film in FIG.

13 is a schematic cross-sectional view showing a state where ions are implanted into a second silicon film by masking a PMOS region of the silicon substrate of FIG. 12 with a resist.

FIG. 14 is a schematic cross-sectional view showing a state where ions are implanted into a second silicon film by masking an NMOS region of the silicon substrate of FIG. 13 with a resist.

FIG. 15 is a schematic sectional view showing a state in which a tungsten silicide film is formed on the second silicon film in FIG.

FIG. 16 is a schematic cross-sectional view showing a state where the first silicon film, the second silicon film, and the tungsten silicide film of FIG. 15 are etched to pattern the gate electrode.

17 is a schematic cross-sectional view showing a state where ions are implanted while masking an NMOS region of the silicon substrate of FIG. 16 with a resist.

18 is a schematic cross-sectional view showing a state where ions are implanted by masking a PMOS region of the silicon substrate of FIG. 17 with a resist.

FIG. 19 is a schematic cross-sectional view showing a state where a sidewall is formed on the gate electrode of FIG. 18 and ions are implanted by masking a PMOS region with a resist.

20 is a schematic cross-sectional view showing a state where ions are implanted while masking a PMOS region of the silicon substrate of FIG. 19 with a resist.

FIG. 21 is a schematic cross-sectional view of a dual-gate MOS transistor completed in the second embodiment of the present invention.

[Explanation of symbols]

11,31 silicon substrate, 13,33 P-type well,
14, 34 N-type well, 15, 35 silicon oxide film, 16, 36 first silicon film, 17, 37 second silicon film, 18, 44 NMOS gate electrode, 19,
45 PMOS gate electrode, 43 tungsten silicide film

Claims (8)

[Claims] 1. A method of manufacturing a semiconductor device having an insulating film formed on a semiconductor substrate having a region of a first conductivity type and a region of a second conductivity type, comprising: A first silicon film forming step of forming a first silicon film to which an impurity of a first conductivity type is added; and a first conductivity type added to the first silicon film on the first silicon film. A second silicon film forming step of forming a second silicon film to which an impurity of a first conductivity type is added at a concentration lower than that of the second silicon film; A first ion implantation step of implanting impurity ions of the second conductivity type into the film; and a first ion implantation step of the first conductivity type into the second silicon film formed on the region of the second conductivity type. A second ion implantation step of implanting impurity ions. Method of manufacturing a semiconductor device that. 2. The method according to claim 1, wherein the first substrate is formed on the semiconductor substrate.
A gate electrode patterning step of patterning the silicon film and the second silicon film to form a gate electrode, wherein the first ion implantation step and the second ion implantation step are performed after forming the gate electrode. 2. The method for manufacturing a semiconductor device according to claim 1, wherein ions are implanted. 3. The method according to claim 1, further comprising the step of: patterning the first silicon film and the second silicon film to form a gate electrode after ion-implanting the second silicon film. The method for manufacturing a semiconductor device according to claim 1, wherein: 4. The method according to claim 1, wherein the first conductivity type and the second conductivity type are p-type and n-type. 5. The method according to claim 1, wherein said second silicon film forming step forms a non-doped silicon film. 6. The method according to claim 1, wherein said first and second silicon film forming steps form a non-single-crystal silicon film. 7. An impurity ion of a second conductivity type is implanted into the second silicon film formed on the first conductivity type region, and the second silicon film is formed on the second conductivity type region. 7. A crystallization step of implanting impurity ions of a first conductivity type into the second silicon film and performing a heat treatment to crystallize the non-single-crystal silicon film. The manufacturing method of the semiconductor device described in the above. 8. The method of manufacturing a semiconductor device according to claim 1, further comprising a silicide film forming step of forming a silicide film on a region of the gate electrode on the second silicon film.