JPH05335503A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the shift of threshold voltage of a P-channel FET induced by gate doping by annealing a p-type gate electrode at first and then an n-type gate electrode for their activation when forming a CMOS device. CONSTITUTION:A field oxide film 2 and a gate oxide film 3 are formed on a silicon board 1 while a gate polysilicon film 4 is grown on the whole surface of the board. A resist film 5, which opens a p-type channel FET formation area, is formed. The resist film 5 is masked and p-type impurity ions B<+> or BF<+2> are implanted and doped. After the doping, the resist film 5 is removed and annealed for its activation. As for an n-type channel FET formation area, a second resist film 6 is masked and n-type impurity ions P<+> or As<+> are implanted and doped in a similar manner. After the doping, the second resist film 6 is removed and activation annealing is carried out. The gate electrode film 4 is patterned, thereby forming a gate electrode and source drains 7 and 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for doping a gate of a CMOS device.

In recent years, CMOS devices have been miniaturized, and the influence of the short channel effect has been increasing. There is a demand for measures for that.

[0003]

2. Description of the Related Art In conventional CMOS devices, an n-channel FE is used.
Both T and p-channel FETs used n-type gate electrodes. When the n-type gate electrode is used for the p-channel FET in this way, the p-channel FET has a buried channel structure in which the channel is formed at a position deeper than the surface. Therefore, it becomes difficult to satisfy both the threshold voltage V _th and the source-drain breakdown voltage BV _SD .

For this reason, in recent years, there has been considered an FET in which a surface channel type FET is formed by using a p type gate electrode for a p channel FET so that _Vth and BV _SD are compatible with each other.

[0005]

However, p-channel FE
When p-type and n-type doping is performed on the same gate electrode film deposited on the substrate to form a p-type gate electrode for T and an n-type gate electrode for an n-channel FET Due to the lateral diffusion of impurities, V _th of the p-channel FET
There was a problem of shifting.

The present invention is a p-channel FET having a p-type gate electrode.
When forming a CMOS device with n-channel FET with n-type gate electrode and p-channel
The purpose is to prevent the V _{th of the} FET from shifting.

[0007]

[Means for Solving the Problems] 1)
When a gate electrode film is deposited on a semiconductor substrate and impurities are introduced into the gate electrode film to form a p-type gate electrode and an n-type gate electrode, activation annealing of the p-type gate electrode is performed first, and then, A method of manufacturing a semiconductor device having a step of performing activation annealing of an n-type gate electrode, or 2) depositing a polycide gate electrode film composed of a composite film of a lower polysilicon film and an upper metal silicide film on a semiconductor substrate Then, before introducing impurities into the gate electrode film to form the p-type gate electrode and the n-type gate electrode, a step of cutting the metal silicide film at the boundary between the p-type gate electrode and the n-type gate electrode is performed. This is achieved by the manufacturing method of the semiconductor device.

[0008]

(Operation) FIGS. 5A and 5B are explanatory views of the operation of the present invention.
Figure 5 (A) shows the distance between the p-channel FET and the n-type impurity doped region, with the n-type FET gate doped with n-type impurities and the subsequent activation annealing temperature (900 ° C, 800 ° C) as a parameter. FIG. 6 is a diagram showing a relationship of a shift amount ΔV _th of V _th of a p-channel FET with respect to d. From the figure, the activation temperature is
It can be seen that at 900 ° C., V _th shift occurs as the distance d becomes smaller.

FIG. 5B shows the n-channel FET and the p-type impurity doped region when the p-type FET gate is doped with the p-type impurity and the subsequent activation annealing temperature is a parameter (900 ° C., 800 ° C.). FIG. 6 is a diagram showing a relationship between a shift amount ΔV _th of V _th of a p-channel FET and a distance d between and. From the figure,
Even when the activation temperature is 900 ° C., _Vth does not shift even if the distance d becomes small.

From the above results, in the first aspect of the present invention, after the p-type impurity is doped and the activation annealing is performed, the n-type impurity is doped and the activation annealing is performed to suppress the lateral diffusion of the n-type impurity. The _Vth of the channel FET is stabilized.

In the second invention, the metal silicide film is divided to suppress lateral diffusion of p-type and n-type impurities and stabilize _{Vth of the} p-channel FET.

As a result, it has become possible to simultaneously form a p-channel FET and an n-channel FET on the same substrate.

[0013]

1 (A) to 1 (D) are sectional views for explaining an embodiment (1) of the first invention. In Fig. 1 (A), silicon (S
i) The field oxide film 2 is formed on the substrate 1, and then the gate oxide film 3 is formed.

Then, a polysilicon film 4 is grown as a gate electrode film on the entire surface of the substrate. Then p-channel FET
A resist film 5 having an opening in a formation region is formed, and the p-type impurity ions (B ⁺ , or B
Doping by implanting F ₂ ⁺ ). After that, the resist film 5 is removed.

In FIG. 1B, the substrate is subjected to activation annealing at about 850 ° C. In Figure 1 (C), n-channel FET
The second resist film 6 having an opening in the formation region is formed, and the second resist film 6 is formed.
N-type impurity ions (P ⁺ ,
Alternatively, As ⁺ ) is implanted to dope. Then the second
The resist film 6 is removed.

Next, the substrate is subjected to activation annealing at about 800 ° C. In FIG. 1 (D), the gate electrode film 4 is patterned to form the gate electrode, and then the source / drain 7 and 8 are formed by a usual method, and the insulating film is deposited on the substrate to form the source / drain 7. A heat treatment which also serves to activate the impurities implanted in 8 is performed, contact holes are opened in the insulating film, and a wiring process is performed.

Although polysilicon is used as the gate electrode material in this embodiment, it may be a metal silicide or a composite film of polysilicon and metal silicide (polycide film) as shown in FIG.

2 (A) and 2 (B) are sectional views for explaining the embodiment (2) of the first invention. In FIG. 2A, a field oxide film 2 is formed on a Si substrate 1, and then a gate oxide film 2 is formed.

Then, a polysilicon film 4, a tungsten silicide (WSi) film 4A as a gate electrode film is formed on the entire surface of the substrate.
Grow in order. In FIG. 2B, a resist film 5 having an opening in the p-channel FET formation region is formed, and the resist film 5 is formed.
With p-type impurity ion (B ⁺ , or BF ₂ ⁺ )
Implanting and doping. Then, the resist film 5 is removed, and the substrate is subjected to activation annealing at about 850 ° C.

Below, referring to FIG. 1 (C), an n-channel FET
A second resist film having an opening in the formation region is formed, and n-type impurity ions (P ⁺ or As ⁺ ) are implanted and doped using the second resist film as a mask. After that, the second resist film is removed, and the substrate is subjected to activation annealing at about 800 ° C.

In Examples (1) and (2), activation annealing is performed before patterning the gate electrode, but activation annealing may be performed after patterning the gate electrode as shown in FIG.

FIGS. 3A to 3D show an embodiment (3) of the first invention.
It is sectional drawing explaining. In FIG. 3 (A), Si substrate 1
A field oxide film 2 is formed on the
To form.

Then, a polysilicon film 4 is grown as a gate electrode film on the entire surface of the substrate. In FIG. 3B, the gate electrode film 4 is patterned to form a gate electrode.

In FIG. 3C, a resist film 5 having an opening in the p-channel FET formation region is formed, and p-type impurity ions (B ⁺ or BF ₂ ⁺ ) are implanted by using the resist film 5 as a mask to dope. To do. After that, the resist film 5 is removed, and the substrate is subjected to activation annealing at about 850 ° C.

In FIG. 3D, a second resist film 6 having an opening in the n-channel FET formation region is formed, and the second resist film 6 is used as a mask to form n-type impurity ions (P ⁺ or
Doping by injecting As ⁺ ). After that, the second resist film 6 is removed, and the substrate is subjected to activation annealing at about 800 ° C.

In the embodiments (1) to (3), the doping to the gate electrode and the implantation for forming the source / drain are performed in different steps. However, in the embodiment (4), these may be performed simultaneously. Good.

That is, in the embodiment (4), after gate oxidation,
After depositing a gate electrode film on the entire surface of the substrate and patterning the gate, implant a p-channel gate electrode and source / drain formation with a resist mask, and then at 850 ° C.
The activation anneal is performed at. After implanting the n-channel gate electrode and source / drain with a resist mask, the activation anneal is performed at 800 ° C. The process of Example (1) is followed.

Although p-type impurities are introduced into the gate electrode film by ion implantation in Examples (1) to (4), Example (6)
As an alternative, the gate electrode film may be doped at the same time as it is deposited. Moreover, activation annealing may be performed by using furnace annealing or RTA (Rapid Thermal Annealing) using a lamp.
ing) may be used.

FIGS. 4A to 4C are sectional views for explaining the second embodiment of the invention. In FIG. 4A, the field oxide film 2 is formed on the Si substrate 1, and then the gate oxide film 2 is formed.

Then, a polysilicon film 4, a metal film (for example, tungsten (W)) is formed as a gate electrode film on the entire surface of the substrate.
Film) 4A is grown in order. Then, the gate electrode film is patterned to form a gate, and the boundary between the n-type gate and the plasma gate is removed by etching only the W film with a width of about 0.5 μm.

In FIG. 4B, a resist film 5 having an opening in the p-channel FET formation region is formed, p-type impurity ions (B ⁺ or BF ₂ ⁺ ) are implanted using the resist film 5 as a mask, A p-type gate electrode and a p-type source / drain 8 are formed. After that, the resist film 5 is removed, and the implanted impurities are activated and the gate electrode is silicidized by annealing.

In FIG. 4C, a second resist film 6 having an opening in the n-channel FET formation region is formed, and the second resist film 6 is used as a mask to form n-type impurity ions (P ⁺ , or
As ⁺ ) is injected to form an n-type gate electrode and an n-type source / drain 8. Doping. Then, the second resist film 6 is removed, and the implanted impurities are activated and the gate electrode is silicidized by annealing.

In this embodiment, the sympathetic metal film of the p-type gate and the n-type gate is etched after the gate patterning, but this step may be performed before the gate patterning according to FIG.

[0034]

According to the present invention, a p-channel FET having a p-type gate electrode and an n-channel FET having an n-type gate electrode are provided.
When forming a CMOS device, n during gate doping
Lateral diffusion of type impurities is suppressed, and V of p-channel FET is suppressed.
_{The th} shift could be suppressed. As a result, CMOS with both p-channel FET and n-channel FET on the same substrate
Devices can now be formed.

[Brief description of drawings]

FIG. 1 is a sectional view for explaining an embodiment (1) of the first invention.

FIG. 2 is a sectional view illustrating an embodiment (2) of the first invention.

FIG. 3 is a sectional view illustrating an embodiment (3) of the first invention.

FIG. 4 is a sectional view for explaining an embodiment of the second invention.

FIG. 5 is an explanatory diagram of the operation of the present invention.

[Explanation of symbols]

 1 Si substrate as semiconductor substrate 2 Field oxide film 3 Gate oxide film 4 Gate electrode film such as polysilicon film 4A metal silicide film or metal film 5 resist film 6 second resist film

Claims (2)

[Claims] 1. A gate electrode film is deposited on a semiconductor substrate,
Impurities are introduced into the gate electrode film to form a p-type gate electrode and an n-type gate electrode.
A method of manufacturing a semiconductor device, comprising a step of performing activation annealing of a p-type gate electrode first and then performing activation annealing of an n-type gate electrode when forming a type gate electrode. 2. A polycide gate electrode film composed of a composite film of a lower polysilicon film and an upper metal silicide film is deposited on a semiconductor substrate, and impurities are introduced into the gate electrode film to form a p-type gate electrode and an n-type gate electrode. A method of manufacturing a semiconductor device, comprising a step of cutting the metal silicide film at a boundary between the p-type gate electrode and the n-type gate electrode before forming the type gate electrode.