KR100839526B1 - A method for fabricating semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a source / drain ion implantation process and an additional ion implantation process in a semiconductor device fabrication process, and to manufacturing a semiconductor device capable of minimizing an increase in the number of processes due to p ⁺ additional ion implantation. The purpose is to provide a method. The present invention synthesis was carried out to in order to secure the contact resistance while maintaining the shallow p ⁺ source / drain junction p ⁺ additional ion implant process to that on the assumption that this is inevitable, then the contact open p ⁺ additional ion-implantation process, a separate ion It is carried out in blankets without an injection mask. At this time, the dose of the n-type dopant is increased during n ⁺ source / drain ion implantation to compensate for counter doping caused in the n ⁺ source / drain region. In fact, the n-type dopant, arsenic (As) or phosphorus (P), has a higher solid-solution limit than the order of boron (B), so that the dose of the n-type dopant is increased when n ⁺ source / drain ions are implanted. Even if not increased, it can be sufficiently activated in subsequent thermal processes to suppress the increase in contact resistance of the n ⁺ source / drain junction.

p-type source / drain, boron, fluorine, activation rate, additional ion implantation

Description

A method for fabricating semiconductor device             

1A to 1D are MOS transistor formation process diagrams of a semiconductor device according to the prior art.

2A to 2D are process diagrams of transistor formation of a semiconductor device in accordance with an embodiment of the present invention.

3 shows solid solution limit characteristics in silicon (Si) of each dopant.

Figure 4 shows the change in sheet resistance (Rs) of p ⁺ source / drain by subsequent thermal process.

FIG. 5 shows the sheet resistance (Rs) change of n ⁺ source / drain by subsequent thermal process;

6 is an isochronous heat treatment characteristic of boron (B).

* Explanation of symbols for the main parts of the drawings

21 silicon substrate 22 device isolation film

23a: n-well 23b: p-well                 

24 gate oxide film 25 gate electrode

26 mask oxide film 27 oxide / nitride spacer

28, 30: photoresist pattern 29: p ⁺ source / drain

31: n ⁺ source / drain 32: interlayer insulating film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing techniques, and more particularly to source / drain ion implantation processes and additional ion implantation processes in semiconductor device fabrication processes.

A semiconductor device including a semiconductor memory includes a large number of MOS transistors, and the operation characteristics of the device largely depend on the characteristics of the MOS transistors. On the other hand, almost all of the process steps affect the characteristics of the MOS transistor, but the source / drain ion implantation process for forming the source / drain is the core process for determining the characteristics of the MOS transistor. .

Traditionally, boron (B) has been used as the p-type dopant, and phosphorus (P) or arsenic (As) has been used as the n-type dopant. Meanwhile, since boron (B), which is a p-type dopant, has a small mass of itself, a serious channeling phenomenon occurs during ion implantation. Thus, ⁷³ Ge ion implantation is performed to prevent the source / drain region from being pre-amorphous. After layering, boron ion implantation is performed.

Recently, ⁴⁹ BF ₂ ions are used instead of ⁷³ Ge ion implantation ( ⁴⁹ BF ₂ + ¹¹ B mixed ion implantation), or ⁴⁹ BF ₂ ions with a higher molecular weight than ¹¹ B ions used as dopant ( ⁴⁹ BF ₂ single ion implantation) has been proposed.

1A to 1D illustrate a process of forming a MOS transistor of a semiconductor device according to the prior art, which will be described below with reference to the drawing.

According to the prior art, the device isolation film 2 is formed on the silicon substrate 1 by performing a shallow trench isolation (STI) process, as shown in FIG. 1A, and then implanted into the silicon substrate 1 through high energy ion implantation. After the n-well 3a and the p-well 3b are formed, the gate oxide film 4 and the gate electrode 5 are formed by performing a normal gate forming process. In this case, a mask oxide film 6 is formed on the gate electrode 5, and an oxide film / nitride spacer 7 is formed on the sidewall of the gate electrode 5.

Next, as shown in FIG. 1B, a photoresist pattern 8 covering the NMOS region is formed, and using this as an ion implantation mask, ⁴⁹ BF ₂ + ¹¹ B mixed ion implantation (or ⁴⁹⁾ into the p ⁺ source / drain region. BF ₂ alone ion implantation). Unexplained reference numeral '9' represents p ⁺ source / drain formed through a predetermined heat treatment.

Subsequently, as shown in FIG. 1C, the photoresist pattern 8 is removed, a photoresist pattern 10 covering the PMOS region is formed, and then, as an ion implantation mask, ⁷⁵ As source / drain ion implantation is performed. Perform. Unexplained reference numeral 11 denotes n ⁺ source / drain formed through a predetermined heat treatment.

Subsequently, as shown in FIG. 1D, the photoresist pattern 10 is removed, the interlayer insulating layer 12 is formed, and then the source / drain 9 and 11 are opened by selectively etching the interlayer insulating layer 12. Bit line contact holes are formed. Subsequently, a photoresist pattern 13 that covers the NMOS region, and performs an additional ⁴⁹ BF ₂ + ¹¹ B mixed ion-implantation (alone or ⁴⁹ BF ₂ ion implantation) in the PMOS region. Typically, since the plug is previously formed in the charge storage electrode contact region during the bit line contact process, contact holes are formed in both the source and drain regions.

Contact resistance is increasing due to a decrease in contact size due to ultra-high integration of semiconductor devices, and as a result of efforts to reduce such contact resistance during bit line contact or metal contact processes, the exposed source after contact hole formation as described above. Additional dopant ion implantation is performed for the / drain. In particular, p ⁺ source / drain contact resistance is about the lower solid solubility limit of boron (B)-about 1 order at the same temperature compared to ³¹ P or ⁷⁵ As, where the solid solution limit for silicon is n-type dopant. Due to low-resistance (surface resistance and contact resistance) issues, there are always additional ⁴⁹ BF ₂ ion implantation or ⁴⁹ BF ₂ + ¹¹ B mixed ion implantation locally in the p ⁺ contact area.

When such additional ⁴⁹ BF ₂ ion implantation (or ⁴⁹ BF ₂ + ¹¹ B mixed ion implantation) is performed, the resistance characteristics can be improved to some extent, but the manufacturing cost is greatly increased due to the increase in the number of processes, and in particular, the addition of a mask process. There was an issue to increase.

As is well known, due to the reduction of the effective gate channel length due to the reduction of device design rules, source / drain junctions of peripheral circuits are also required to form shallow junctions of about 0.1 μm in depth. Although the implementation of such a shallow junction is relatively superior to a deep junction in terms of transistor characteristics such as punch-through voltage characteristics and short channel effects, it is important in terms of implementation of a junction having low resistance, which is a main consideration in designing a peripheral circuit. It is disadvantageous. Therefore, the depth of the junction is determined in consideration of the correlation between these two characteristics.

In order to omit p ⁺ additional ion implantation and secure resistance characteristics in consideration of the above-described process addition problem, it is inevitable to bring deep depth of p ⁺ source / drain junction. In this case, an increase in the junction depth alone makes it difficult to hit the contact resistance, and causes a PMOS punch problem.

The present invention has been proposed to solve the above problems of the prior art, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can minimize the increase in the number of processes due to p ⁺ additional ion implantation.

According to an aspect of the present invention to achieve the above technical problem, the step of ion implanting a first p-type dopant containing fluorine and boron in the p-type source / drain region of the silicon substrate; Implanting an n-type dopant into an n-type source / drain region of the silicon substrate; Forming a contact hole through the interlayer insulating layer to expose the p-type source / drain region and the n-type source / drain region; And additionally implanting a second p-type dopant into the p-type source / drain region and the n-type source / drain region exposed using the interlayer insulating layer as an ion implantation mask. .

The present invention synthesis was carried out to in order to secure the contact resistance while maintaining the shallow p ⁺ source / drain junction p ⁺ additional ion implant process to that on the assumption that this is inevitable, then the contact open p ⁺ additional ion-implantation process, a separate ion It is carried out in blankets without an injection mask. At this time, the dose of the n-type dopant is increased during n ⁺ source / drain ion implantation to compensate for counter doping caused in the n ⁺ source / drain region. In fact, the n-type dopant, arsenic (As) or phosphorus (P), has a higher solid-solution limit than the order of boron (B), so that the dose of the n-type dopant is increased when n ⁺ source / drain ions are implanted. Even if not increased, it can be sufficiently activated in subsequent thermal processes to suppress the increase in contact resistance of the n ⁺ source / drain junction.

Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

2A to 2D illustrate a process of forming a transistor of a semiconductor device according to an embodiment of the present invention, which will be described below with reference to the drawings.

According to the present embodiment, first, as shown in FIG. 2A, an isolation layer 22 is formed on the silicon substrate 21 by performing a shallow trench isolation (STI) process, and the silicon substrate 21 is formed through high energy ion implantation. After the n-well 23a and the p-well 23b are formed in the gate, the gate oxide film 24 and the gate electrode 25 are formed by performing a normal gate forming process. In this case, a mask oxide layer 26 is formed on the gate electrode 25, and an oxide / nitride spacer 27 is formed on the sidewall of the gate electrode 25.

Next, as shown in FIG. 2B, a photoresist pattern 28 covering the NMOS region is formed, and using this as an ion implantation mask, ⁴⁹ BF ₂ + ¹¹ B mixed ion implantation (or ⁴⁹⁾ into the p ⁺ source / drain region. BF ₂ alone ion implantation). Here, ⁴⁹ BF ₂ + ¹¹ B when performing a mixed ion implantation, ⁴⁹ BF ₂ ion implantation energy is 10~30keV ion, the ion implantation energy of the ions ¹¹ B is a non-integer projection (Rp) in the desired range of 1~10keV Dose amount at BF ₂ ion implantation is 2.5 × 10 ¹⁴ # / ㎠ ~ ^1.5 × 10 ¹⁵ # / ㎠, and dose amount at B ion implantation is 2.5 × 10 ¹⁴ # / ㎠ ~ ^1.5 × 10 ¹⁵ # / ㎠ It is preferable to set it as. Unexplained reference numeral 19 denotes p ⁺ source / drain formed through a predetermined heat treatment.

Subsequently, as shown in FIG. 2C, the photoresist pattern 28 is removed, a photoresist pattern 30 covering the PMOS region is formed, and then, as a ion implantation mask, a ⁷⁵ As source / drain ion implantation ( Or ³¹ P source / drain ion implantation). Here, in case of using the ⁷⁵ As ions with an n-type dopant, the subsequent p ⁺ ion implantation more in consideration of the influence of the counter-doped in accordance with the ion implantation dose ^{1 × 10 15 # / ㎠~8 ×} 10 to ¹⁵ # / ㎠ range It is preferable to adjust, and it is preferable to adjust ion implantation energy in the range of 10-50 keV. On the other hand, with an n-type dopant when using the ³¹ P ions, the ion implantation dose is ^{1 × 10 15 # / ㎠~8 ×} 10 15 # / ㎠, ion implantation energy is preferable to control the wind to 4~20keV range. Unexplained reference numeral 31 denotes n ⁺ source / drain formed through a predetermined heat treatment.

Subsequently, as shown in FIG. 2D, the photoresist pattern 30 is removed, the interlayer dielectric layer 32 is formed, and the interlayer dielectric layer 32 is selectively etched to open the source / drain 29 and 31. A bit line contact hole is formed and ⁴⁹ BF ₂ + ¹¹ B additional ion implantation (or ⁴⁹ BF ₂ additional ion implantation) is performed over the entire surface. Here, the dose and ion implantation energy at the time of p ⁺ additional ion implantation may be applied in the same manner as at the time of p ⁺ source / drain ion implantation.

Thereafter, a subsequent process is performed to complete device fabrication.

As described above, in the present invention, p ⁺ additional ion implantation is performed to secure the transistor characteristics of the PMOS and to match the contact resistance target. Meanwhile, in the present invention, p ⁺ additional ion implantation is performed by front ion implantation without a separate ion implantation mask in order to minimize an increase in the number of processes due to p ⁺ additional ion implantation. In addition, the dose of the n-type dopant is adjusted during n ⁺ source / drain ion implantation in consideration of counter doping in the n ⁺ source / drain region according to the front ion implantation.

However, as shown in FIG. 3, the n-type dopants ⁷⁵ As and ³¹ P have higher orders of magnitude higher in silicon (Si) than the p-type dopants ¹¹ B, and thus the n-type dopants in subsequent thermal processes. Can be sufficiently activated, and the dose of the n-type dopant is not substantially increased.

Meanwhile, in the case of p ⁺ dopant, the surface resistance (Rs) of p ⁺ source / drain increases as shown in FIG. 4 due to deactivation by a subsequent thermal process, but in the case of n + dopant, Even if the deactivation occurs, as shown in FIG. 5, since the resistance characteristics are restored through the subsequent thermal process, the influence of the counter doping may be insignificant. This is attributed to the high in-silicone employment limit of n-type dopants.

For reference, the dopant deactivation phenomenon is a potential defect as the dopant (supersaturated state) of p ⁺ source / drain activated through a high temperature RTP process passes through a low temperature region of 600 to 850 ° C. where dislocation defects are easily formed. It is known to be due to the decrease in activation rate due to the precipitation (precipitation) in or near [Wolf, Silicon Processing for the VLSI Era, Vol. 1, p. 304]. FIG. 6 shows isochronous heat treatment characteristics of boron (B), and shows the ratio of free-carrier (P _Hall / φ) to the heat treatment temperature according to the dose of boron. Referring to FIG. 3, the dopant deactivation phenomenon was shown to be the most active at a temperature of 600 to 700 ° C., but the experiment showed that the largest increase in resistance was found at a temperature around 800 ° C. FIG. The boron ion implantation energy is 150 keV for each dose condition.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

For example, the technical principle of the present invention applies even when the BF ₂ ions used in the above-described embodiment are replaced with ³⁰ BF ions.

The above-described present invention can minimize the process water to be added in accordance with the practice of the p ⁺ p ⁺ additional ion-implantation, by performing the additional ion-implantation without ion implantation mask. On the other hand, in the present invention, it is possible to secure a contact resistance target while maintaining a shallow junction of p ⁺ source / drain, thereby improving the characteristics of the semiconductor device.

Claims (8)

Implanting a first p-type dopant containing fluorine and boron into the p-type source / drain region of the silicon substrate; Implanting an n-type dopant into an n-type source / drain region of the silicon substrate; Forming a contact hole through the interlayer insulating layer to expose the p-type source / drain region and the n-type source / drain region; And Further implanting a second p-type dopant into the p-type source / drain region and the n-type source / drain region exposed using the interlayer insulating layer as an ion implantation mask Semiconductor device manufacturing method comprising a. The method of claim 1, The first p-type dopant containing fluorine and boron is any one selected from BF ₂ + B, BF + B, BF ₂ , BF. The method of claim 2, The second p-type dopant is any one selected from BF ₂ + B, BF + B, BF ₂ , BF. The method of claim 2, When the BF ₂ + B is used as the first p-type dopant, the dose of BF ₂ is 2.5 × 10 ¹⁴ # / cm 2 to 1.5 × 10 ¹⁵ # / cm 2, and the dose of B is 2.5 × 10 ¹⁴ # / The semiconductor device manufacturing method characterized by setting to 2 cm <2> -1.5 * 10 <^15># / cm <2>. The method according to claim 2 or 4, The n-type dopant is arsenic (As) or phosphorus (P) characterized in that the semiconductor device manufacturing method. The method of claim 5, Method of manufacturing a semiconductor device, characterized in that for setting the dose of the n-type dopant to ^{1 × 10 15 # / ㎠~8 ×} 10 15 # / ㎠. The method of claim 6, When the BF ₂ + B is used as the first p-type dopant, the dose of BF ₂ is 2.5 × 10 ¹⁴ # / cm 2 to 1.5 × 10 ¹⁵ # / cm 2, and the dose of B is 2.5 × 10 ¹⁴ # / The semiconductor device manufacturing method characterized by setting to 2 cm <2> -1.5 * 10 <^15># / cm <2>. The method of claim 6, The method of manufacturing a semiconductor device, characterized in that the dose of the first p-type dopant and the second p-type dopant is the same in the ion implantation of the first p-type dopant and the additional ion implantation of the second p-type dopant.

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