JPS61294868A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the resistance value of an N<-> layer, by forming a low-concentration impurity diffused layer having a reverse conducting type with respect to a semiconductor substrate at a lower part of a side wall on one side, and forming a high- concentration impurity diffused layer having the same impurity as that in the low- concentration diffused layer at a lower part of a side wall on the source side. CONSTITUTION:On a P-type 100 substrate 1, a gate oxide film 2 is formed. A polysilicon film is formed. Phosphorus is doped by thermal diffusion. Then, with a photoresist film 7 as a mask, anisotropic etching is performed. Thus a gate electrode 3, whose side surface is approximately vertical is formed. With the gate electrode 3 as a mask, phosphorus is implanted in the silicon substrate at a slant angle of about 10 deg. to the drain side. The phosphorus-ion implanted layer is formed so that the layer is separated from the end part of the gate electrode. An oxide film 4' is formed by a plasma CVD method. Thereafter, anisotropic etching is performed until the surface of the silicon substrate 1 is exposed, and a side wall 4 is formed. Arsenic is implanted at a slant angle of about 10 deg. to the source side, which is opposite with respect to the phosphorus-ion implanting direction. Thus, the arsenic-ion implanted layer is formed. Therefore, suppression of a hot carrier effect and the suppression of increase in channel resistance can be simultaneously realized.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a MOS field effect transistor (hereinafter referred to as MOSF).
ET), especially double diffused drains (Lightly
The present invention relates to a semiconductor device having a doped drain structure.

BACKGROUND OF THE INVENTION As MOSFETs become smaller, the electric field strength inside the device increases, causing problems such as deterioration of device characteristics and reduction of drain breakdown voltage due to generated hot carriers.

As a structure to solve this problem, for example, IEE Transactions of Electron
Device, Eday Volume 29, No. 4.

1982, p. 69o (I E E E Transa
ctions of Electron Devices
There is an LDD structure MOSFET described in ED-29, No. 4, 1982, P590).

An example in which a conventional LDD structure is applied to an n-channel MOSFET is shown in the cross-sectional view of FIG. 3a. LDD-MOSFET
is a gate oxide film 1 formed on a p-type silicon substrate 11
2, a gate electrode 13, a side wall 14 made of an insulator formed on both side walls of the gate electrode 13, and an n-type low concentration diffusion layer formed by ion implantation using the gate electrode 13 as a mask. (n layer) 15, and an n-type high concentration diffusion layer (n+ layer) 16 formed in the same manner using the sidewall as a mask, and the n layer is made of M
By acting to weaken the electric field strength inside the OSFET, the generation of hot carriers was suppressed and the drain breakdown voltage was increased.

Problems to be Solved by the Invention However, in the conventional LDD-MOSFET, as shown in the equivalent circuit diagram in Figure 3, n layers of resistance Rn- are connected in series between the source and drain, so the on-resistance of the MOSFET is 2Rn- becomes high, which has the disadvantage of lowering the current driving ability.

Further, since the ability to prevent hot carrier generation and the ability to increase the drain breakdown voltage of the n-layer are inversely proportional to the resistance Rn-, it has been difficult to determine the optimal values for the length Ln- and the impurity concentration of the n-layer.

Means for Solving the Problems The present invention has been made in order to solve the above-mentioned drawbacks.The present invention has been made in order to solve the above-mentioned drawbacks. A wall is formed, and a low concentration impurity diffusion layer of the opposite conductivity type to the semiconductor substrate is formed at the bottom of the sidewall on one side, and a low concentration impurity diffusion layer of the opposite conductivity type to the semiconductor substrate is formed at the bottom of the sidewall on the source side. This is a semiconductor device in which a high concentration diffusion layer of the same type of impurity as the low concentration diffusion layer is formed.

Function: Since the MOSFET according to the present invention has an n-layer formed only on the drain side, the resistance value of the n-layer added between the source and drain can be reduced to half that of a conventional LDD-MOSFET. .

Embodiment FIG. 1 shows an embodiment in which the present invention is applied to an n-channel MOSFET.

The MOSFET of the present invention, as shown in a cross-sectional view of its main parts in FIG. A gate electrode 3 made of polysilicon, a sidewall 4 made of a CVD oxide film formed on both side walls of the gate electrode, and a low concentration n-type (n) diffusion layer on the drain side formed at the bottom of the sidewall. 5-a, a high concentration n-type (n+) diffusion layer 6-a on the drain side formed in contact with the n- diffusion layer 5-a on the drain side, and an n+ diffusion layer on the source side formed at the bottom of the sidewall. The layer consists of six layers.

Furthermore, the sidewalls are formed equally on the source side and the drain side, and the n-diffusion layer 6-a is formed only on the drain side (Ln-D), so hot carriers are generated on the n-drain side. This can be largely suppressed by the diffusion layer 5-a, and the increase in channel resistance of the MOSFET was dealt with by not providing a low concentration impurity diffusion layer on the source side.

Next, an embodiment of the method for manufacturing an LDD-MOSFET of the present invention will be described with reference to FIG.

As shown in FIG. 2a, a gate oxide film 2 having a thickness of approximately 300 wafers is formed on a p-type 1000 substrate 1 by thermal oxidation at 900°C.

Next, a polysilicon film with a thickness of about 600°A is formed by the well-known low pressure CVD method, and phosphorus is absorbed by about 1o2 by thermal diffusion.
After doping to about 0 crn-3, anisotropic etching is performed using the photoresist 7 as a mask to form a gate electrode 3 with substantially vertical sides as shown in FIG. 2a.

Next, using the gate electrode 3 as a mask, phosphorus is implanted into the silicon substrate 1 by ion implantation at an acceleration energy of 60 Kev and a dose of 6×10 crn. During this phosphorus injection, the injection direction is tilted approximately 100 degrees toward the drain side as shown in FIG. Then,
Due to the shadow effect of the gate electrode 3, the phosphorus ion-implanted layer on the source side is formed at a distance of about 0.1 μm from the end of the gate electrode. This separation length is the thickness of the gate electrode
(injection inclination angle). After implanting phosphorus ions, the silicon substrate is heat-treated at 900°C for 30 minutes to activate and diffuse the implanted phosphorus, resulting in asymmetric n-diffusion between the drain and source sides, as shown in Figure 2. Form layers 5-a and s-b. Although Figure 2 shows the state in which the n-diffusion layer s-b on the source side reaches the bottom of the gate electrode, the n-diffusion layer s-b on the source side does not have to overlap with the gate electrode 3. .

Next, as shown in FIG. 2C, an oxide film 4' with a thickness of approximately 300 μm is formed by plasma CVD, and then anisotropic etching is performed by reactive ion etching until the surface of silicon substrate 1 is exposed. Etching is performed to form the sidewall 4 as shown in FIG. 2d. The width of the sidewall formed at this time is influenced by the shape of the gate electrode, the step coverage of the plasma oxide film, and the degree of anisotropy of etching, but in the case of this example, the width of the sidewall was 1soO. Ta.

Next, as shown in FIG. 2d, using the sidewall 4 as a mask, arsenic is ion-implanted using an acceleration energy of 40.
Kev and a dose of 5×1orIn into the silicon substrate 1. At this time, the arsenic ion implantation direction is about 100 mm toward the source side, which is opposite to the arsenic ion implantation direction.
Tilt and inject. This time, due to the shadow effect of the sidewall 4, the arsenic ion-implanted layer on the drain side is formed at a distance of about 0.1 μm from the end of the gate electrode. This separation length is the height of the sidewall xtan (injection inclination angle)
is approximately equal to . Silicon substrate 1 after arsenic ion implantation
1000 tl: , 20 minutes of heat treatment is performed to activate and diffuse the implanted arsenic atoms, forming the n+ diffusion layer 6.
- form a and eb. At this time, the n+ diffusion layer eb on the source side includes the n- diffusion layer sb and overlaps with the gate electrode 3, so that the sidewalls are formed equally on the source side and the drain side, and the n-
LDD-MOSF where the diffusion layer is formed only on the drain side
ET is completed.

In the manufacturing method of this example, both phosphorus and arsenic elements were implanted at an angle, but if the implantation angle, gate electrode thickness, sidewall height, heat treatment conditions, etc. are set to appropriate values, lean or arsenic elements can be implanted. The LDD-MOSFET of the present invention can be manufactured even if only one of them is implanted at an angle.

In addition to the method of tilting the implantation angle of ion implantation as in this embodiment, for example, a method of forming sidewalls on one side at a time and providing an n-diffusion layer only in the drain region, etc.
Of course, any method that can realize the structure of the present invention does not impede the spirit of the present invention.

Effects of the Invention According to the present invention, since the n-diffusion layer is formed only on the drain side where the electric field is strong, it is possible to simultaneously suppress the hot carrier effect and the increase in channel resistance.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of the main parts of a semiconductor device according to an embodiment of the present invention, FIGS. 2 a - d are diagrams for explaining the manufacturing method thereof, and FIGS. These are a cross-sectional view and an equivalent circuit. 1...p-type silicon substrate, 2...gate oxide film, 3...gate electrode, 4...
Side wall, 5-a, 5-b... N-diffusion layer on drain side and source side, e-a, 6-b...
・N+ diffusion layer on drain side and source side. Name of agent: Patent attorney Toshio Nakao and 1 other person/-
--P silicon flea sheet 2--ke "-to-sun-i-otatsu 3-m-gate 1-ν 1-"---n'4L blue () hair (drain 11□rin 6-b- --rI integrated tJ (source length
F Ray/Deposit Diagram 2 Nsu l! Figure 2 Figure 3 Island-Island-

Claims (2)

[Claims] (1) Sidewalls of equal thickness made of an insulating material are formed on both sidewalls of a gate electrode of a MOS field effect transistor formed on a semiconductor substrate, and only the lower part of one sidewall is connected to the semiconductor substrate. A semiconductor device characterized in that a low concentration impurity diffusion layer having an opposite conductivity type is formed, and a high concentration diffusion layer of an impurity of the same group as the impurity is formed under the other sidewall. . (2) A low concentration diffusion layer is formed under the sidewall on the drain side of the MOS field effect transistor, and a high concentration diffusion layer is formed under the sidewall on the source side. 1. Semiconductor device described in Section 1.