JPH01108774A - Semiconductor device - Google Patents

Abstract

PURPOSE:To restrain the generation of short channel effect, and improve characteristics of an element, by burying a gate electrode in the surface of a silicon substrate, positioning a channel region at a part deeper than the surface of the source and drain regions, and arranging a low impurity concentration region having the same conductivity type as the drain region, around the channel region. CONSTITUTION:A trench 7 is formed in a channel region part of the surface region of a silicon substrate 6, and a gate electrode 3 like, e.g., polycrystalline silicon is formed in the trench 7, via a gate insulating film 4. By a processing such as ion implantation using the gate electrode 3 as a mask, a low impurity concentration (N<->) region 5 is formed. By ion implantation utilizing the side wall mask effect of an oxide insulating film formed by heat treatment, a source region 1 and a drain region 2 of high impurity concentration (N<+>) are formed. Thereby, a boundary against oxide insulator in the drain side low impurity region in which hot electron trap is apt to occur can be kept from a current path. As a result, the injection into an oxide film and the trap of hot electron can be restrained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device, particularly an MO3 type semiconductor device.

(Prior Art) With the rapid development of semiconductor technology toward higher integration and higher density, miniaturization of MOS type elements such as MOSFETs has become a problem.

In the past, especially in micro MOSFETs with a size of 1.5μ or less, IBBB Transactions on
Electron Devices, BD-27,
k8. L Rolo (Lightly Doped Drai) as proposed in AUGUST 1980.
n) structure MOSFET is generally widely adopted.

As shown in FIG. 2, this LDD structure MOSFET has a source region 1 with a high impurity concentration on the surface of a silicon substrate 60.
A gate electrode 3 is provided on the surface of the substrate 1 between the source region I and the drain region 2 with a gate oxide film layer 4 interposed therebetween. It is constructed by providing low impurity concentration regions 5 that protrude from the source region 1 and drain region 2, respectively, between the region 1 and the drain region 2.

(Problems to be Solved by the Invention) However, in this MOSFET with a six-hole structure, the high drain electric field is alleviated, but a low impurity concentration region is formed using a sidewall mask of the gate electrode. For IP
BB Electron Qevices Lette
rs, BDL-5, Nα3 As pointed out in 1984, when voltage is applied, as long as hot carriers (electrons) are not injected into the oxide film layer on the low impurity concentration region, the resistance value of the low impurity concentration region is is not as large as on the left, but when operated for a certain period of time, electrons are trapped in the oxide film layer on the low impurity concentration region on the drain side, depleting the low impurity concentration region and rapidly increasing its resistance value.
This has the drawback of lowering the conductance of the channel region and shortening the life of the device.

SUMMARY OF THE INVENTION It is an object of the present invention to eliminate the above-mentioned drawbacks and to provide a vIOS type semiconductor device of the above-mentioned type that does not generate short channel effects.

(Means for Solving the Problems) The present invention provides a pair of low impurity concentration regions of a second conductivity type, which are provided in a surface area of a semiconductor substrate of a first conductivity type, facing each other with a channel region interposed therebetween; A pair of high impurity concentration regions of a second conductivity type located outside the pair of low impurity concentration regions and connected to each of these low impurity concentration regions, and an insulating film layer on the substrate surface above the channel region. In a semiconductor device comprising a gate electrode provided through the semiconductor substrate, the gate electrode is buried to a certain depth from the surface of the semiconductor substrate, and between the channel region and the semiconductor-insulating film interface at the surface above the low impurity concentration region. It is characterized by being sufficiently spaced apart from each other.

(Function) According to the present invention, the gate electrode is buried in the surface of the silicon substrate, the channel region is located deeper than the surface of the source and drain regions, and the periphery of the channel region is provided with the same conductivity type as the drain region. By providing the low impurity concentration region, it is possible to provide an MO5 type semiconductor device having an LDD structure with good characteristics.

(Example) The present invention will be described in detail below with reference to FIG.

In the MO3 type semiconductor device of the present invention shown in FIG. 1, a silicon substrate 6 is provided similarly to the semiconductor device shown in FIG. A gate electrode 3 made of, for example, polycrystalline silicon is provided with a gate insulating film 4 interposed therebetween. Next, using this gate electrode 3 as a mask, a region 5 with a low impurity concentration (N-) is formed by processing such as ion implantation, and then ion implantation is performed using the sidewall mask effect of the oxide insulating film formed by heat treatment. A source region 1 and a drain region 2 having a high impurity concentration (N゛) are formed by this, and an LDD type MO3FET having the structure shown in the figure is thus constructed. The depth of the trench 7 is preferably approximately equal to or deeper than the depths of the source region 1 and drain region 2.

In the MO3 semiconductor device of the present invention configured as above,
By moving the channel region inward from the surface of the semiconductor substrate and separating it from the silicon-oxide film interface on the surfaces of the source region 1 and drain region 20, oxide insulation of the low impurity concentration region on the drain side where hot electron traps are likely to occur is improved. The boundary with objects and the current path can be kept far apart, so hot electrons are less likely to be injected into the oxide film and trapped. Therefore, it is possible to suppress the deterioration mode of the element peculiar to the LDD structure and improve the reliability of the element. In addition, since the source and drain regions are formed at a shallower position than the channel region, the source and drain regions are better separated and punch-through is less likely to occur, and the influence of the source and drain electric fields on the channel region is reduced. can be reduced and the short channel effect can be suppressed.

(Effects of the Invention) According to the semiconductor device of the present invention configured as described above, since the gate electrode is buried in the semiconductor substrate, electrons are trapped in the oxide film layer on the low impurity concentration region on the drain side. This prevents the low impurity concentration region from becoming a depletion layer, thereby also preventing a decrease in channel conductance, thereby extending the life of the device. At the same time, since the source and drain regions can be made shallower than the channel region than in the past, the occurrence of short channel effects can be suppressed, and the characteristics of the device can be improved.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing an example of a semiconductor device of the present invention, and FIG. 2 is a sectional view showing an example of a conventional semiconductor device. 1... Source region (high concentration impurity layer) 2... Drain region (high concentration impurity layer) 3... Gate electrode
4...Gate insulating film...Low impurity concentration region 6...
・Silicon substrate 7...groove Figure 1 Figure 2

Claims (1)

[Claims] 1. A pair of low impurity concentration regions of a second conductivity type provided opposite to each other via a channel region in the surface area of a semiconductor substrate of the first conductivity type, and a pair of low impurity concentration regions located outside of the pair of low impurity concentration regions. and a pair of high impurity concentration regions of a second conductivity type connected to each of these low impurity concentration regions, and a gate electrode provided on the surface of the substrate above the channel region via an insulating film layer. In the semiconductor device, the gate electrode is buried to a certain depth from the surface of the semiconductor substrate, and a sufficient distance is provided between the channel region and the semiconductor-insulating film interface at the surface above the low impurity concentration region. Characteristic semiconductor devices.