JPS58145156A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS58145156A JPS58145156A JP57028314A JP2831482A JPS58145156A JP S58145156 A JPS58145156 A JP S58145156A JP 57028314 A JP57028314 A JP 57028314A JP 2831482 A JP2831482 A JP 2831482A JP S58145156 A JPS58145156 A JP S58145156A
- Authority
- JP
- Japan
- Prior art keywords
- type
- insulating film
- semiconductor device
- depletion type
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 19
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 239000002184 metal Substances 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims 1
- 238000009413 insulation Methods 0.000 claims 1
- 239000012535 impurity Substances 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 239000011229 interlayer Substances 0.000 abstract description 3
- 238000005468 ion implantation Methods 0.000 abstract description 3
- 230000003647 oxidation Effects 0.000 abstract description 3
- 238000007254 oxidation reaction Methods 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 229910052785 arsenic Inorganic materials 0.000 abstract description 2
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 150000002500 ions Chemical class 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 238000005530 etching Methods 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000007788 liquid Substances 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 230000005669 field effect Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 229920006395 saturated elastomer Polymers 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000881 depressing effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置に関し、特にＭＯ８＠Ｏ８電界効果
トランジスタる。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor devices, and particularly to MO8@O8 field effect transistors.
近年、ＭＯ８電界効果トランジスタにおいて、素子の高
性能化のための勢力は、一方では高電圧高電猾を特徴と
する高電力化であり、もう一方では高速高電流利得を特
徴とする高周波化である。In recent years, in MO8 field-effect transistors, the forces for improving the performance of elements are on the one hand, high power, characterized by high voltage and high power, and on the other, high frequency, characterized by high speed and high current gain. be.
ＭＯ８型電界効果トランジスタの高周波化のための性能
係数（Ｆｉｇｕｒｅ ｏｆ ｍｅｒｉｔ）Ｆは、素子
特性及び素子構潰パラメータで表わすと
である。ここでｇｍ、Ｃｉｎは素子の相互コンダクタン
ス、入力容量でありμ、 Ｖ’Ｇ 、 Ｖｄ 、 Ｌは
それぞれキャリア移動度、正味のゲート電圧、キャリア
のドリフト速度、実効チヤネル長である。これらの指数
から高周波化のための条件は第１にチャネル長の低減で
あり次に、キャリア移動度の向上とバイアス電圧の上昇
、従ってキャリアのドリフト速度に依存する。これらの
要請から現状では、チャネル長は １μｍ以下のサブミ
クロンの寸法が要求されており、この寸法の微小化に伴
って種々の製造上の制御性の問題が生じている。すなわ
ち、チャネルｈはもちろんのことしきい値電圧がばらつ
いたり、ドレイン耐圧が減少するといった欠点がある。The figure of merit F for increasing the frequency of an MO8 type field effect transistor is expressed in terms of device characteristics and device collapse parameters. Here, gm and Cin are the mutual conductance and input capacitance of the element, and μ, V'G, Vd, and L are carrier mobility, net gate voltage, carrier drift speed, and effective channel length, respectively. Based on these indexes, the conditions for increasing the frequency are firstly a reduction in channel length, and secondly, an improvement in carrier mobility and an increase in bias voltage, which depends on carrier drift speed. Due to these requirements, the channel length is currently required to have a submicron dimension of 1 μm or less, and as this dimension becomes smaller, various manufacturing controllability problems arise. That is, there are drawbacks such as variations in not only the channel h but also the threshold voltage and a decrease in drain breakdown voltage.
本発明は上記欠点を除き、制御性が良く、且つ高周波特
性の優れたＭＯ８電界効果型の半導体装置を提供するも
のである。The present invention provides an MO8 field effect type semiconductor device which eliminates the above drawbacks and has good controllability and excellent high frequency characteristics.
本発明の半導体装置は、−主面が（１００）面である一
導電型半導体基板の該−主面に設けられた逆向き台形の
溝部と、前記溝部の傾斜面の一方に設けられ前記半導体
基板と逆導電型のソース領域と、前記溝部の他方の傾斜
面に設けられたデプレッション型のＭ２Ｓ部と、前記溝
部の底面に設けられたエンハンスメント型のＭ２Ｓ部と
、前記デプレッション型ＭＯ８部に接続して前記半導体
基板の一主面に設けられた逆導電型のドレイン領域とを
含んで構成される。The semiconductor device of the present invention includes: an inverted trapezoidal groove provided on the main surface of a one-conductivity type semiconductor substrate whose main surface is a (100) plane; A source region of a conductivity type opposite to that of the substrate, a depression type M2S part provided on the other inclined surface of the groove, an enhancement type M2S part provided on the bottom surface of the groove, and connected to the depression type MO8 part. and a drain region of opposite conductivity type provided on one main surface of the semiconductor substrate.
前記デプレッション型及びエンハンスメント型ＭＯ８部
は前記溝部の表面に絶縁膜を設け、該絶縁膜上に金属膜
を設けることにより形成される。The depression type and enhancement type MO8 parts are formed by providing an insulating film on the surface of the groove part and providing a metal film on the insulating film.
前記絶縁膜は前記半導体基板の一主面上の絶縁膜に接続
して形成され、かつ前記デプレッション型及びエンハン
スメント型ＭＯ８部の絶縁膜の厚さよりも前記ソース領
域及びドレイン領域の絶縁膜の厚さの方が大きいように
形成される。The insulating film is formed to be connected to an insulating film on one main surface of the semiconductor substrate, and the thickness of the insulating film in the source region and drain region is greater than the thickness of the insulating film in the depletion type and enhancement type MO8 parts. is formed so that it is larger.
本発明の半導体装置は、前記ドレイン領域から流れ出る
ドレイン電流の使用範囲の最大値をＩＤ。In the semiconductor device of the present invention, ID is the maximum value of the usable range of drain current flowing out from the drain region.
ｍａｘとするとき
ＶＴＩ ：エンハンスメント型ＭＯ８のターンオン電圧
５−
ＶＴ２：デプレッション型ＭＯ８のターンオン螺圧
μ７：デプレツシヨン型ＭＯ８のキャリア移動度
１２：デプレッション型ＭＯ８のチャネル長ＣＯＸ、２
：デプレッシ冒ン型ＭＯ８のゲート絶縁膜容量
Ｗ：Ｍ２Ｓ部のチャネル幅
なる式（１）が成立するように形成される。When set to max, VTI: Turn-on voltage of enhancement type MO8 5- VT2: Turn-on helical pressure of depression type MO8 μ7: Carrier mobility of depletion type MO8 12: Channel length of depression type MO8 COX, 2
: gate insulating film capacitance of depressurized type MO8 W: channel width of M2S section.
次に本発明の実施例について図面を用いて説明する。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）〜（Ｃ）は本発明の一実施例の製造方法を
説明するための工程断面図である。FIGS. 1A to 1C are process cross-sectional views for explaining a manufacturing method according to an embodiment of the present invention.
まず、第１図（ａ）に示すように、−主面が（１００）
面であるＰ型シリコン基板の一主面に通常の方法により
Ｎ型領域２を形成し、その上に５ｉｎ２等の絶縁膜３ｆ
設ける。更にその上にホトレジスト膜４を設け、露光、
現像し開口部を設ける。ホトレジスト膜４をマスクにし
て絶縁膜３をエツチングして幅りの窓５をあける。First, as shown in Fig. 1(a), the -principal surface is (100)
An N-type region 2 is formed on one main surface of a P-type silicon substrate by a normal method, and an insulating film 3f of 5in2 or the like is formed thereon.
establish. Further, a photoresist film 4 is provided thereon, exposed to light,
Develop and create openings. Using the photoresist film 4 as a mask, the insulating film 3 is etched to open a wide window 5.
６−
次に、第１図ｔｂ＋に示すように、（１１１１而の方が
他の而と比較してエツチング速度が遅いような異方性エ
ツチング液、例λ、ばＫＯＨ＠液等を用いて基板１を異
方性エツチングして逆向き台形の溝部６を設ける。溝部
６のＩＩＩｆ＋面が（１，１１）面、底面が（１００）
而となる。また、Ｎ型懺域２は二つに分けらする。これ
全ソース領域２′ 、ドレイン領域２“とする。次に溝
部６の一方の傾斜面に入射角管θだけ傾けたイオン注入
によりＡｓ、Ｐ等のドナー不純物をイオン注入し、熱処
理＃−を施し、Ｎ型ソース領域７を形成する。6- Next, as shown in FIG. The substrate 1 is anisotropically etched to form an inverted trapezoidal groove 6. The IIIf+ plane of the groove 6 is a (1,11) plane, and the bottom plane is a (100) plane.
It becomes. Further, the N-type coverage area 2 is divided into two. These are all made into a source region 2' and a drain region 2''.Next, donor impurities such as As and P are ion-implanted into one inclined surface of the trench 6 at an angle of incidence θ, and a heat treatment #- is performed. Then, an N-type source region 7 is formed.
次に、ｆｆ１１図ｔｃ）に示すように、熱酸化等により
ゲート絶縁１［８’、８“及び層間絶縁膜８を形成した
後、ゲート絶縁膜９を形成する。最後にソース及びドレ
イン・１域２′ 、２“にコンタクト窓の開孔部を設け
、それぞれにＡＩ等の金属を極等を形成する。ここで、
）＠ ＩＩＪ１絶縁膜８のｎさはゲート絶縁膜８′、８
“より厚く形ルνすることが重装である。基板１とゲー
ト絶縁膜８′とゲート成極９とでエンハンスメント型Ｍ
ｏ５ｉｆｌｌ（以下Ｅ ｇ Ｍ２Ｓ部と記す）１０を形
成し、基板１とゲート絶縁膜８“とゲート電極９とでデ
プレッション型ＭＯ８部（以下り型Ｍ２Ｓ部と記す）１
１を形成する。このようにＥ型及びＤ型のＭ２Ｓ部を有
する半導体装置をＥｌ）−ＭＯｆＳ型電界効果トランジ
スタと称することにする。Ｅ型、Ｄ型の差異はターンオ
ン電圧によって規定されるが、このターンオン電圧は基
板の不純物濃度、ゲート酸化膜厚、８ｌ−８Ｉ０２系の
Ｑｓｓの関数であるばかりでなく、Ｓ ＋ −８ｉ Ｏ
２界面近傍にＢ、Ｐ、Ａ、ｓ等の不純物をドープするこ
とによって容易に制御できる。Next, as shown in ff11 (tc), after forming gate insulating film 1 [8', 8'' and interlayer insulating film 8 by thermal oxidation etc., gate insulating film 9 is formed.Finally, source and drain 1 Openings for contact windows are provided in regions 2' and 2'', and poles, etc., of metal such as AI are formed in each. here,
) @ IIJ1 The n-thickness of the insulating film 8 is the same as that of the gate insulating films 8' and 8.
“It is heavy mounting to make the shape thicker.The enhancement type M
o5ifll (hereinafter referred to as E g M2S part) 10 is formed, and a depression type MO8 part (hereinafter referred to as depletion type M2S part) 1 is formed by the substrate 1, gate insulating film 8'' and gate electrode 9.
Form 1. A semiconductor device having such E-type and D-type M2S portions will be referred to as an El)-MOfS field effect transistor. The difference between E type and D type is determined by the turn-on voltage, which is a function not only of the impurity concentration of the substrate, the gate oxide film thickness, and the Qss of the 8l-8I02 system, but also of the S + -8i O
This can be easily controlled by doping impurities such as B, P, A, and s near the two interfaces.
以上の如く形成したＥＤ、−ＭＯ８型心界効果トランジ
スタにおいてドレイン電流の使用範囲においてその最大
値を■Ｄ、ｍａｘとした時に次なる関係式が成立するよ
うに形成した事が本発明の第１の特徴でち６゜
ここで ＶＴＩ ： Ｅ型ＭＯ８のターンオン電圧ＶＴ
２ ： Ｄ型ＭＯ８のターンオン電圧μ２：Ｄ型ＭＯ８
のキャリア移動度
ｅ２．：Ｄ型ＭＯ８（Ｄチャネル長
ＣＯＸ、２ ： Ｄ型ＭＯ８のゲート酸化膜容量Ｗ：Ｅ
Ｄ型ＭＯ８のチャネル幅
第２図は第１図（Ｃ）に示した一実施例の等価回路図で
ある。The first aspect of the present invention is that the ED, -MO8 type mind field effect transistor formed as described above is formed so that the following relational expression holds when the maximum value of the drain current in the usage range is D, max. Characteristics of 6゜Here, VTI: Turn-on voltage VT of E-type MO8
2: Turn-on voltage μ2 of D-type MO8: D-type MO8
Carrier mobility e2. : D type MO8 (D channel length COX, 2 : Gate oxide film capacitance of D type MO8 W: E
Channel width of D-type MO8 FIG. 2 is an equivalent circuit diagram of the embodiment shown in FIG. 1(C).
第２図において、Ｅはエンハンスメント型、Ｄはデブレ
ッシ田ン型を示し、点ＭはＥ部とＤ部の実効的な接点を
示す。この点Ｍでの電位ｙＶＭで表示する。In FIG. 2, E indicates the enhancement type, D indicates the depressing type, and point M indicates the effective contact point between the E section and the D section. The potential at this point M is expressed as yVM.
第３図は第２図に示す等価回路の動作特性の一例の特性
曲線図である。Ｅ型、Ｄ型ＭＯ８のそれぞれの動作条件
は次の通りである。領域Ｉ 、 ＩＩにおいては、Ｅ部
がカットオフであるために電流は流れない。領域ｖ、■
においてはＥ部とＤ部の電流駆動能力が同程度となり、
双方が電諸制限項となるが、領域１．ｍＶにおいては、
Ｄ部の電流駆動能力がＥ部の駆動能力より大きいため、
全体として ９−
は、Ｅ部のみによって電離が決定される。Ｅ部は飽和状
態であるので、この時の電Ｒを線形近似で示すと、
Ｄ部は領域■では非飽和、領域■では飽和状態となるが
Ｖｏの範囲は第３図から
ＶＴ １（Ｖｃ ＜ＶＴ ｔ＋Ｖ／ａ （ＶＴ ｔ −
ＶＴ ｘ ） ・（４）このＶａの値から（３）式の電
ｉＩｎの範囲は直ちにα＝β２／／１
従って、ＥＤ−ＭＯ８型トランジスタに於てなるように
素子パラメータを設定するとドレイン電流・ゲート電圧
特性はＥ型ＭＯ８部のみによって決まる。すなわち第１
図（Ｃ）において溝部６の底部のトランジスタによって
決められる。この底部は（１００）面であり斜面部の（
１１１）面と比較すると、ＭＯＳを形成した場合一般的
には、Ｑｓｓが小さく、表面移動度が大きい。これは前
述した高周波化には有利である。又、チャネル長の微小
化においては、第４図に示した９０くＥ型ＭＯ８部のチ
ャネル長ｌ−の決定は窓５０幅り、溝部６の閑さｔ及び
Ｄ型ＭＯ８部のチャネル長１２．ドレイン領域２“の接
合深さＸｊによってなされる。FIG. 3 is a characteristic curve diagram of an example of the operating characteristics of the equivalent circuit shown in FIG. 2. The operating conditions for the E type and D type MO8 are as follows. In regions I and II, since section E is cutoff, no current flows. Area v,■
In this case, the current drive capabilities of the E section and the D section are about the same,
Both are electric limit terms, but in area 1. In mV,
Since the current drive capability of section D is greater than the drive capability of section E,
Overall, the ionization of 9- is determined only by the E part. Since the E part is in a saturated state, if the electric current R at this time is expressed by linear approximation, the D part will be unsaturated in the region ■ and saturated in the region ■. However, the range of Vo is VT 1 (Vc <VT t+V/a (VT t −
VT The gate voltage characteristics are determined only by the E-type MO8 section. That is, the first
In figure (C), it is determined by the transistor at the bottom of the trench 6. This bottom part is a (100) plane, and the slope part is (
111) surface, when a MOS is formed, Qss is generally small and the surface mobility is large. This is advantageous for increasing the frequency mentioned above. In addition, in the miniaturization of the channel length, the channel length l- of the 90-type E-type MO8 section shown in FIG. ．． This is done by the junction depth Xj of the drain region 2''.
（ψ−５５°）
例として、Ａ！−＝１μ”＋１ｚ＝１．５ ｔｔｍ、Ｘ
ｊ ＝０．３１１ＭとするとＬ＝３．４５μｍとなり、
チャンネル長１μｍの制御ｆ３４５μｍによってなされ
た訳であるからばらつき等を深さｔの制御を適当にする
ことにより、約１／３に減少することができる。これは
実際の製作上大きなメリットである。(ψ−55°) For example, A! -=1μ”+1z=1.5 ttm,X
If j = 0.311M, L = 3.45μm,
Since the channel length was controlled by f345 μm with a channel length of 1 μm, variations, etc. can be reduced to about ⅓ by appropriately controlling the depth t. This is a great advantage in actual production.
以上のように前記条件によれば、電離はＥ型Ｍ（１８部
のみによって決めらねる。このことは逆にＤ型ＭＯ８部
ではドレイン・ソース間の電圧の一部を相っているので
Ｅ型ＭＯ８部だけの場合と比較すると、高耐圧化を計る
ことが可能である。この時電流には影Ｉｉ＃全与えない
。次に、第１図（Ｃ１及び第４図に示すように、溝６の
一部の傾斜面にはイオン注入等によりソース領域を形成
したがゲート酸化膜形成時にこれらの高濃度拡散領域に
は増速酸化を引き起こす事が可能である。これらの増速
酸化によりソース領域２′ 、７及びドレイン領域２“
とゲート電極間に付随する寄生容ｔ’を低減させること
ができる。この溝部６の傾斜面にイオン注入する時、第
４図に示したように、入射角θはＥ型チャネル長１１と
溝部６の深さｔによって次式で表わされる。As described above, according to the above conditions, ionization cannot be determined only by the E-type M (18 part).This means that in the D-type MO8 part, part of the voltage between the drain and source is mutual, so the E Compared to the case of only the type MO8 section, it is possible to achieve a higher withstand voltage.At this time, there is no effect on the current Ii#.Next, as shown in Fig. 1 (C1 and Fig. 4), Although source regions were formed by ion implantation or the like on the slopes of some of the grooves 6, it is possible to cause accelerated oxidation in these high concentration diffusion regions when forming the gate oxide film. Source regions 2', 7 and drain regions 2''
It is possible to reduce the parasitic capacitance t' between the gate electrode and the gate electrode. When ions are implanted into the inclined surface of the groove 6, the incident angle θ is expressed by the following equation using the E-type channel length 11 and the depth t of the groove 6, as shown in FIG.
例として、１ｌ＝ｔμｌ ｔ＝１．５ｔｔｍ（ｌｚ＝１
．５ｔｔｔｎ、ｘｊ＝０３μｍの時）の時θ＝５４’で
ある。以上のようにゲート・ソース間の寄生容量を減ら
すことを目的として、溝部６のソース側の傾斜面の酸化
膜厚をＥ及びＤ型ＭＯ８のゲート酸化膜厚より大きくな
るように形成した事が本発明の第２の特徴である。又、
Ｄ型ＭＯ８の制御をイオン注入によって行う場合、前記
ソース領域の場合と同様であり、入射角を（７）式に従
って調整すれば良い。As an example, 1l=tμl t=1.5ttm (lz=1
．． 5tttn, xj=03 μm), θ=54′. As described above, in order to reduce the parasitic capacitance between the gate and the source, the oxide film thickness on the sloped surface on the source side of the trench 6 is formed to be larger than the gate oxide film thickness of the E and D type MO8. This is the second feature of the present invention. or,
When the D-type MO8 is controlled by ion implantation, it is the same as the case of the source region, and the incident angle may be adjusted according to equation (7).
以上説明したように、本発明は逆向き台形の溝部を形成
したＥｌ）−ＭＯ８型成界効果トランジスタにおいて、
チャネル長或ｕ”を気的特性の制御性を向トさせ、素子
性能の高周波化を達成せしめることが可能であるという
効果ケ有す。As explained above, the present invention provides an El)-MO8 type field effect transistor in which an inverted trapezoidal groove is formed.
This has the effect that it is possible to improve the controllability of the channel length (u'') and achieve higher frequency device performance.
第１図（ａｌ〜（Ｃ）は本発明の一実施例の製造方法を
説明するための工程断面図、第２図は第１図（Ｃ）に示
す一実施例の等価回路図、第３図は第１図（Ｃ）に示す
一実施例の動作特性の一例の特性曲線図、第４図は第１
図（Ｃ）に示す一実施例の幾何学的条件を説明するため
の図である。
１・・・・・・Ｉ〕型シリコン基板、２・・・・・・Ｎ
型領域、２′・・・・・・ソース領域、２″・・・・・
・ドレイン領域、３・・・・・・絶縁膜、４・・・・・
ホトレジスト膜、５・°°・・・窓、６・°。
・・・溝部、７・・・・・・ソース領域、８・・・・・
・層間絶縁膜、Ｂ／ 、 Ｂ″−・・・・・ゲート絶縁
膜、９・・・・・・ゲート’＋を極、１０・・・・・・
エンハンスメントＭＯ８部、 １１・・・・・・テフレ
ノションＭＯ８部。
＝１３−1(al to C) are process sectional views for explaining the manufacturing method of an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of the embodiment shown in FIG. 1(C), and 3. The figure is a characteristic curve diagram of an example of the operating characteristics of the embodiment shown in Figure 1 (C), and Figure 4 is a characteristic curve diagram of an example of the operating characteristics of the embodiment shown in Figure 1 (C).
FIG. 6 is a diagram for explaining the geometrical conditions of the example shown in FIG. 1...I] type silicon substrate, 2...N
Type area, 2'...Source area, 2''...
・Drain region, 3... Insulating film, 4...
Photoresist film, 5·°°...window, 6·°. ...Groove portion, 7...Source region, 8...
・Interlayer insulating film, B/, B''-...Gate insulating film, 9...Gate'+ as pole, 10...
Enhancement MO 8 parts, 11...Tephrenotion MO 8 parts. =13-
Claims (4)
の該−主面に設けられた逆向き台形の溝部と、前記溝部
の傾゛斜面の一方に設けられ前記半導体基板と逆導電型
のソース領域と、前記溝部の他方の傾斜面に設けられた
デプレッション型のＭ２Ｓ部と、前記溝部の底面に設け
られたエンハンスメント型のＭ２Ｓ部と、前記デプレッ
ション型ＭＯ８部に接続して前記半導体基板の一主面に
設けられた逆導電型のドレイン領域とを含むことを特徴
とする半導体装置。(1) - An inverted trapezoidal groove provided on the principal surface of a one-conductor molded semiconductor substrate whose principal surface is a (100) plane, and a groove provided in one of the inclined surfaces of the groove and opposite to the semiconductor substrate. A conductive type source region, a depletion type M2S part provided on the other inclined surface of the trench, an enhancement type M2S part provided on the bottom surface of the trench, and a depletion type M2S part connected to the depletion type MO8 part. 1. A semiconductor device comprising: a drain region of opposite conductivity type provided on one main surface of a semiconductor substrate.
ＭＯ８部が前記溝部の表面に絶縁膜を設け、該絶４禄模
上に金属膜を設けて形成されることを特徴とする特許請
求の範囲第（１）項記載の半導体装置。(2) The depression type and enrichment type MO8 parts are formed by providing an insulating film on the surface of the groove part and providing a metal film on the insulation film. 1) The semiconductor device described in item 1).
に接続して形成され、かつ前記デプレッション型及びエ
ンハンスメント型ＭＯ８部の絶縁膜の厚さよりも前記ソ
ース領域及びドレイン領域の絶縁膜の厚さが大きいこと
を特徴とする特許請求の範囲第（１）項記載の半導体装
置。(3) The insulating film is formed to be connected to the insulating film on one main surface of the semiconductor substrate, and the insulating film in the source region and drain region is thicker than the insulating film in the depletion type and enhancement type MO8 parts. The semiconductor device according to claim 1, wherein the semiconductor device has a large thickness.
ｆの使用範囲の最大値をｉｎ、ｍａｘとするときここで ＶＴｌ：エンハンスメント型ＭＯ８のターンオン電圧 ＶＴ２：デプレッション型ＭＯ８のターンオン′邂圧 μ２：デプレソ７ヨン型ＭＯ８のキャリア移動度 １２：デプレッション型ＭＯ８のチャネル長 Ｃｏｘ、２：デプレッション型ＭＯ８のゲート絶縁膜容
量 Ｗ：Ｍ２Ｓ部のチャネル幅 なる式が成立するように形成したことを特徴とする特許
請求の範囲第（１）項記載の半導体装置。(4) Drain tttA protruding from the drain region
When the maximum value of the usable range of f is in and max, here VTl: turn-on voltage of enhancement type MO8 VT2: turn-on pressure of depletion type MO8 μ2: carrier mobility of depression type MO8 12: depletion type MO8 The semiconductor device according to claim 1, wherein the semiconductor device is formed so that the following formula holds true: channel length Cox, 2: gate insulating film capacitance of depletion type MO8, W: channel width of M2S portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57028314A JPS58145156A (en) | 1982-02-24 | 1982-02-24 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57028314A JPS58145156A (en) | 1982-02-24 | 1982-02-24 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58145156A true JPS58145156A (en) | 1983-08-29 |
Family
ID=12245149
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57028314A Pending JPS58145156A (en) | 1982-02-24 | 1982-02-24 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58145156A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63197375A (en) * | 1987-02-12 | 1988-08-16 | Matsushita Electric Ind Co Ltd | Manufacture of mos type semiconductor device |
| WO1998012753A1 (en) * | 1996-09-18 | 1998-03-26 | Advanced Micro Devices, Inc. | Short channel self aligned vmos field effect transistor |
| US6150693A (en) * | 1996-09-18 | 2000-11-21 | Advanced Micro Devices | Short channel non-self aligned VMOS field effect transistor |
-
1982
- 1982-02-24 JP JP57028314A patent/JPS58145156A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63197375A (en) * | 1987-02-12 | 1988-08-16 | Matsushita Electric Ind Co Ltd | Manufacture of mos type semiconductor device |
| WO1998012753A1 (en) * | 1996-09-18 | 1998-03-26 | Advanced Micro Devices, Inc. | Short channel self aligned vmos field effect transistor |
| US6150693A (en) * | 1996-09-18 | 2000-11-21 | Advanced Micro Devices | Short channel non-self aligned VMOS field effect transistor |
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