JPS61292372A - Semiconductor device - Google Patents

Abstract

PURPOSE:To simultaneously improve the hot carrier production preventive capability and drain pressure-resistance increase capability of a semiconductor device by making the length of the diffusion layer on a drain side larger and the length of the diffusion layer on a source side shorter. CONSTITUTION:The MOSFET consists of a P-type silicon substrate 1, a gate oxide film 2, a gate electrode 3, a side wall 4, a low-density N<-> diffusion layer on the drain side 5-a, an N<-> diffusion layer on the source side 5-b, a high density N<+> diffusion layer on the drain side 6-a, and an N<+> diffusion layer on the source side 6-b. The width of the side wall LSW is the same on the source and drain sides, and the length of the N<-> diffusion layer is longer on the drain side (Ln<->D) than on the source side (Ln<->S). The generation of the hot carrier is substantially suppressed by Ln<->D made larger on the drain side. The increase in the channel resistance of the MOSFET is coped with by making Ln<-->S on the source side shorter.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a MOS field effect transistor (hereinafter referred to as MOSF).
ET), especially double diffused drains (Lightly
The present invention relates to a semiconductor device having a doped drain structure.

BACKGROUND OF THE INVENTION As MOSFETs become smaller in size, the electric field strength inside the device becomes higher, deterioration of device characteristics due to generated hot carriers, and reduction in drain breakdown voltage become problems.

As a structure for solving this problem, for example, IEE Lands Action Op Electron Device Eday Vol. 29, No. 4.

1982, p. 69o (IEEE Transacti.
ons volume of Electron Devices ED-29
v, No. 4, 1982.

MOSFET with LDD structure described in psso)
There is. Conventional LDD structure is converted to n-channel Sakaki 0→MOS
An example applied to an FET is shown in the sectional view of FIG. 3a. LDD
- The MOSFET includes a gate oxide film 12 formed on a p-type silicon substrate 11, a gate electrode 13, side walls 14 made of an insulator formed on both side walls of the gate electrode 13, and a mask for the gate electrode 13. An n-type low concentration diffusion layer (n single layer) 15 formed using the ion implantation method, and an n type high concentration diffusion layer (n''/layer 16) formed in the same manner using the sidewall as a mask. has become,
This n layer functions to weaken the zero electric field inside the MOSFET, thereby suppressing the generation of hot carriers and increasing the drain breakdown voltage.

Despite the problems that the invention attempts to solve, the conventional (7) LDD-MOSFET-7'
is a resistor Rn of n layers as shown in the equivalent circuit diagram in Figure 3.
- enters in series between the source and drain, so the MOSFE
There was a drawback that the on-resistance of T increased by 2Rn- and the current driving ability decreased.

In addition, since the ability to prevent hot carrier generation and the ability to increase drain breakdown voltage of the n-layer are inversely proportional to the resistance Rn-, the length Ln- of the n-layer and impurity The present invention was made to solve the above-mentioned drawbacks. A MOSFET is formed on a semiconductor substrate, and side walls of equal thickness are formed on both sides of the gate electrode of the MOSFET.
Furthermore, a low concentration diffusion layer of an impurity having a conductivity type opposite to that of the semiconductor substrate is formed at the bottom of the sidewall, and the length of the low concentration diffusion layer is longer on the drain side than on the source side. It is characterized by

Function: In the MOSFET according to the present invention, since the length of the n layer on the source side is shorter, Rn″″(II>Rn−(S)),
Rn-Q))+Rn-(S) is the conventional series resistance value 2Rn
-, it becomes possible to significantly improve the ability to prevent hot carrier generation and the ability to increase drain breakdown voltage.

Embodiment FIG. 1 shows an embodiment in which the present invention is applied to an n-channel MOSFET.

The MOSFET of the present invention, as shown in a cross-sectional view of its main parts in FIG. A gate electrode 3 made of polysilicon, a sidewall 4 made of a CVD oxide film formed on both side walls of the gate electrode 3, and a low concentration n-type (n-) layer on the drain side formed at the bottom of the sidewall. The diffusion layer 5-a, the n-diffusion layer s-b on the source side, and the high concentration n-type (n-diffusion layer 6-a) on the drain side formed in contact with each n-diffusion layer.
a and an n+ diffusion layer eb on the source side.

Furthermore, the width Is+w of the sidewall is equal on the source side and the drain side, and the length of the n- diffusion layer is on the source side (
LnS) is larger on the drain side (Ln-D), and hot carriers are generated on the drain side (Ln-D).
By increasing n-D, it can be significantly suppressed, and the MOS
In response to an increase in FET channel resistance, the source side L
This problem was solved by shortening n-3.

Next, an embodiment of the method for manufacturing an LDD-MOSFET of the present invention will be described with reference to step-by-step sectional views of FIGS. 2a to 2d.

As shown in FIG. 2a, a 900 nm
A gate oxide film 2 having a thickness of about 300 wafers is formed by thermal oxidation at .degree.

Next, a polysilicon film with a thickness of about 6,000 wafers is formed by the well-known low pressure CVD method, and phosphorus is absorbed by about 1o2 by thermal diffusion.
After doping to about 0 cnt-3, anisotropic etching is performed using the photoresist as a mask to form a gate electrode 3 with substantially vertical sides as shown in FIG. 2a.

Next, using the gate electrode 3 as a mask, phosphorus is implanted using an ion implantation method at an acceleration energy of 60 keys and a dose of 5×10
It is implanted into the silicon substrate 1 under the conditions of crrl. During this phosphorus injection, the injection direction is tilted approximately 100 degrees toward the drain side as shown in FIG. Then, gate electrode 3
Due to the shadow effect, the phosphorus ion-implanted layer on the source side is formed at a distance of about 0.1 μm from the end of the gate electrode.

This separation length is the gate electrode thickness xtan (implantation tilt angle)
is approximately equal to . After implanting phosphorus ions, the silicon substrate is heat treated at 900°C for 30 minutes to activate and diffuse the implanted phosphorus, forming drain breakdown layers 5-a and s- as shown in Figure 2. form b. Although Figure 2 shows the state in which the n-'' diffusion layer s-b on the source side has reached the lower part of the gate electrode, in reality, after the subsequent heat treatment, the n- diffusion layer ts on the source side is -b and the gate electrode 3 should just overlap.

Next, as shown in FIG. 2C, an oxide film 4' having a thickness of approximately 5000 Å is formed by plasma CVD, and then anisotropic etching is performed by reactive ion etching until the surface of silicon substrate 1 is exposed. Then, the sidewall 4 as shown in FIG. 2d is formed. The width of the sidewall formed at this time is influenced by the shape of the gate electrode, the step coverage of the plasma oxide film, and the degree of anisotropy of etching, but in the case of this example, the width of the sidewall was 3500 mm. .

Next, as shown in FIG. 2d, using the sidewall 4 as a mask, arsenic is ion-implanted using an acceleration energy of 40%.
Kev and a dose of 5×10 m into the silicon substrate 1. At this time, the implantation direction of arsenic ions is tilted by about 10 degrees toward the source side, which is opposite to the direction of implantation of phosphorus ions. ,Next time.

Due to the shadow effect of the sidewall 4, the arsenic ion-implanted layer on the drain side is formed at a distance of about 0.1 μm from the end of the gate electrode. This separation length is approximately equal to sidewall height×(implantation inclination angle). After implanting arsenic ions, the silicon substrate 1 is heat-treated at 1000°C for 20 minutes to activate and diffuse the implanted arsenic atoms, forming n+ diffusion layers 6-a and 6-b. The width Lsw of the sidewall shown in the figure is equal on the source side and the drain side, and the length of the n- diffusion layer is Ln''D (drain side) than Ln-9 (source side).
A larger LDD-MOSFET is completed.

In the manufacturing method of this example, both phosphorus and arsenic were implanted at an angle, but if the implantation angle, gate electrode thickness, sidewall height, heat treatment conditions, etc. are set to appropriate values, phosphorus or arsenic can be implanted at an angle. The LDD-MOSFET of the present invention can be manufactured even if only one of them is implanted at an angle.

Effect of the invention According to the present invention, as is clear from the above description.

Since the length Ln-D of the n-diffusion layer on the drain side can be increased and the length Ln-3 of the n-diffusion layer on the source side can be decreased, the hot carrier effect and the increase in channel resistance can be suppressed at the same time. It has the effect of

[Brief explanation of drawings]

FIG. 1 is a sectional view of a main part of a semiconductor device according to an embodiment of the present invention, and FIGS. 2 a to 2 d are LDD-MOSFs according to an embodiment of the present invention.
FIG. 3a is a cross-sectional view showing a conventional LDD-MOSFET, and FIG. 3 is an equivalent circuit thereof. 1...p-type silicon substrate, 2...gate oxide film, 3...gate electrode, 4...
Side wall, 6-a, 5-b... N-diffusion layer on drain side and source side, e-a, e-b...
・N+ diffusion layer on drain side and source side. Name of agent: Patent attorney Toshio Nakao and 1 other person/-
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Claims (2)

[Claims] (1) Sidewalls of equal thickness made of an insulator are formed on both sides of the gate electrode of a MOS field effect transistor formed on a semiconductor substrate, and the lower part of the sidewall is of a conductivity type opposite to that of the semiconductor substrate. 1. A semiconductor device characterized in that a low concentration diffusion layer of an impurity exhibiting the following properties is formed to have different lengths on a source side and a drain side. (2) Claim 1 characterized in that the length of the low concentration diffusion layer is longer on the drain side than on the north side.
1. Semiconductor device described in Section 1.