JPH0629527A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To obtain a high-breakdown strength semiconductor device by a method wherein the breakdown strength of the semiconductor device in the vertical direction in addition to an electric-field relaxation effect in a channel direction is enhanced. CONSTITUTION:A conductive layer 14 is formed, via an insulating film 13, on the main face part of a first first-conductivity-type semiconductor region 11; second second-conductivity-type regions 15 are formed on the main face part of the first semiconductor region 11 on both sides of the conductive layer 14; third second-conductivity-type regions 16 whose impurity concentration is lower than that of the second semiconductor regions are formed so as to come into contact with the second semiconductor regions 15 and in parts on the main face part of the first semiconductor region. Fourth second-conductivity-type semiconductor regions 17 whose impurity concentration is lower than that of the second semiconductor regions are formed along the boundary between the second semiconductor regions 15 and the first semiconductor region 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and particularly to a high breakdown voltage MISFE.
The present invention relates to T (metal-insulating layer-semiconductor field effect transistor).

[0002]

2. Description of the Related Art In recent years, semiconductor integrated devices have been extremely miniaturized. With such miniaturization, the line width of gates and wirings used in the device has become smaller. Due to such high integration, the gate insulating film is thinned and the channel length is shortened, so that a high electric field is generated in the vicinity of the drain region. For this reason, hot electrons are remarkably generated, causing an increase in current flowing through the substrate, that is, so-called substrate current. As a result, the threshold voltage of the MISFET deteriorates with time in its electrical characteristics.

Further, with the miniaturization of semiconductor integrated devices, there have been problems such as reduction of breakdown voltage between source and drain, which are caused by an electric field near the drain. In order to reduce the short channel effect and the like caused by the reduction of the gate line width, Japanese Patent Publication No. 62-31506 discloses a TEOS.
CVD (Che) by thermal decomposition of (tetraethoxysilane)
mical vapor deposition) to form an insulating film, anisotropic dry etching to form sidewalls, and the source and drain channel parts to have a double structure.
A so-called LDD (Lightly Dopod Drain) structure for forming a region having a high impurity concentration and a region having a low impurity concentration is described.

Alternatively, a DDD (Double Difused Drain) structure is known in which a semiconductor region having a high impurity concentration and a semiconductor region having a low impurity concentration form a double drain structure, and a high electric field near the drain region of a MISFET is relaxed. A method has been proposed. To form a double drain structure, two types of impurities having different diffusion coefficients, for example, phosphorus are ion-implanted and thermally diffused to form a low-concentration impurity region, and then arsenic is ion-implanted to form a high-concentration impurity. A region is formed, or phosphorus and arsenic are ion-implanted almost simultaneously to form a semiconductor region having a high impurity concentration and a semiconductor region having a low impurity concentration due to the difference in diffusion coefficient.

By using either the LDD structure or the DDD structure, deterioration of the semiconductor device due to miniaturization has been reduced.

[0006]

Generally, in the LDD structure, the low-concentration impurity region in the channel direction is longer than that in the DDD structure and can be formed at a low concentration. Therefore, the LDD structure is used for a MISFET of about 1 μm or less. Has been. By the way, in the LDD structure, after the sidewall is formed, a high concentration of arsenic is implanted and diffused, but the electric field relaxation effect in the vertical direction is smaller than the electric field relaxation effect in the horizontal direction of the channel. Therefore, in a device using a high voltage, it is difficult to obtain a voltage of about 12 to 13 V or higher when using the punch-through characteristic of MISFET and using it as a regulator.

In view of the above points, it is an object of the present invention to provide a semiconductor device which improves the breakdown voltage in the vertical direction in addition to the effect of relaxing the electric field in the channel direction, and a method for manufacturing the same.

[0008]

According to claim 1 of the present invention,
A conductive layer is provided on the main surface portion of the conductive type first semiconductor region via an insulating film, and a second conductive type second semiconductor region is provided on the main surface portions of the first semiconductor region on both sides of the conductive layer. In the semiconductor device, a third semiconductor region of a second conductivity type, which is in contact with the second semiconductor region and has a lower impurity concentration than that of the second semiconductor region, is provided in a part of the main surface portion of the first semiconductor region, and The semiconductor device is characterized in that a fourth semiconductor region of a second conductivity type having a lower impurity concentration than that of the second semiconductor region is provided along a boundary between the second semiconductor region and the first semiconductor region.

According to a second aspect of the present invention, a step of forming an insulating film on the main surface portion of the first semiconductor region of the first conductivity type and providing a conductive layer on the insulating film; A step of introducing a first impurity for forming a semiconductor region, and CVD
Forming an insulating layer by etching, a step of etching the insulating layer by anisotropic etching, and a second conductivity type second
Introducing a second impurity for forming a semiconductor region and a third impurity for forming a fourth semiconductor region of the second conductivity type, and introducing the introduced first, second and third impurities. And a step of diffusing impurities to form a second semiconductor region, a third semiconductor region, and a fourth semiconductor region.

[0010]

According to the present invention, the electric field relaxing effect in the channel direction can be obtained by the third semiconductor region, and the vertical breakdown voltage can be improved by the fourth semiconductor region.
Therefore, it is possible to obtain a semiconductor device having a higher breakdown voltage than the conventional one.

[0011]

EXAMPLES The present invention will be described in detail below based on examples. FIG. 1 is a diagram schematically showing an embodiment of a semiconductor device of the present invention. In the following figures, the same numeral is given to the same configuration in each figure, and repeated description is omitted. In FIG. 1, 10 is a semiconductor substrate, 11 is a first semiconductor region,
12 is a field insulating film, 13 is an insulating film, 14 is a conductive layer, 15 is a second semiconductor region, 16 is a third semiconductor region, 1
7 is a fourth semiconductor region.

As the semiconductor substrate 10, for example, an N type silicon substrate having a thickness of 4 to 12 Ωcm can be used. The first semiconductor region 11 is formed on the semiconductor substrate 10. The first semiconductor region 11 is a P-type semiconductor region, which is a so-called P-well, and is formed by introducing and diffusing impurities such as boron by a known method. When a P-type semiconductor substrate is used, it is not necessary to have a well structure, and the semiconductor substrate 10 serves as the first semiconductor region.

MISF is formed on the upper surface of the first semiconductor region 11.
The field insulating film 12 for electrically separating ET is formed by a well-known technique such as the LOCOS method. Further, an insulating film 13 formed by thermally oxidizing the first semiconductor region 11 is provided in a region of the main surface portion of the first semiconductor region 11 where the MISFET is formed, and is used as a gate insulating film of the MISFET. Further, the conductive layer 1 is provided through the insulating film 13.
4 is provided, and the conductive layer 14 is formed by a well-known etching technique after forming a polycrystalline silicon layer and then doping phosphorus, and is used as a gate electrode of a MISFET.

The second semiconductor region 15 is an N type region having a high impurity concentration, which is formed by ion-implanting arsenic, for example, and is a so-called N ⁺ region. The second semiconductor region 15 is the drain / source region of the MISFET. The third semiconductor region 16 is in contact with the second semiconductor region, and the first semiconductor region 1
This is an N ⁻ type region which is provided in a part of the main surface portion 1 and has an impurity concentration lower than that of the second semiconductor region 15.

The fourth semiconductor region 17 is the second semiconductor region 1
5 provided along the boundary between the first semiconductor region 11 and the second semiconductor region 11.
This is an N ⁻ type region having an impurity concentration lower than that of the semiconductor region 11. The third semiconductor region 16 and the fourth semiconductor region 17 are formed by introducing and diffusing phosphorus, for example.

FIG. 2 shows an MIS having the above structure.
A method for manufacturing a semiconductor device having a FET will be described. First, as shown in FIG. 2A, a first method is performed on the semiconductor substrate 10 by a known method.
A semiconductor region 11 is formed and a field oxide film 12 is formed. Next, after forming the insulating film 13, for example, a polycrystalline silicon film is formed by CVD, phosphorus is doped, a conductive layer 14 is formed by a known lithography technique, and the surface is thinly oxidized.

Next, an impurity for forming the third semiconductor region 16, for example, phosphorus is applied at an energy of 50 keV at 1.5 × 1.
An amount of 0 ¹³ cm ^-2 is ion-implanted. Next, as shown in FIG. 2B, a silicon oxide layer 20 is formed by a CVD (Chemical Vapor Deposition) method by thermal decomposition of TEOS (tetraethoxysilane), for example.

This silicon oxide layer 20 is anisotropically dry-etched to lightly oxidize the surface, as shown in FIG. 2C. This etching is so-called sidewall etching, and forms a silicon oxide layer on both sides of the conductive layer 14. Next, an impurity for forming the second semiconductor region 15, for example, arsenic is ion-implanted at an energy of 75 keV in an amount of 5 × 10 ¹⁵ cm ⁻² , and an impurity for forming the fourth semiconductor region 17, for example, phosphorus. 50k
An amount of 2 × 10 ¹⁴ cm ⁻² is ion-implanted with an energy of eV. The energy and concentration of impurities for forming the fourth semiconductor region 17 can be independently controlled.

After the ion implantation, the ion-implanted impurities are thermally diffused for 20 minutes in a furnace at 1000 ° C., for example. The respective impurities form the second semiconductor region 15 and the fourth semiconductor region 17 due to the difference in diffusion coefficient, as shown in FIG. 2D. The junction depth of the fourth semiconductor region 17 can be controlled by adjusting the diffusion temperature and the diffusion time. As described above, in addition to the effect of relaxing the electric field in the channel direction as shown in FIG. 1, the MISFET which improves the breakdown voltage in the vertical direction.
I was able to get MISF with conventional LDD structure
Whereas the ET punch-through breakdown voltage was about 12V,
The punch-through breakdown voltage of the MISFET obtained by the above manufacturing method was 17V. As described above, the punch-through breakdown voltage can be controlled in a wide range by appropriately changing the impurity concentration, implantation energy, or diffusion condition, and a high breakdown voltage MISFET can be realized.

[0020]

According to the present invention, in addition to the effect of relaxing the electric field in the channel direction by the third semiconductor region,
The breakdown voltage in the vertical direction can be improved by the semiconductor region. Therefore, it is possible to obtain a semiconductor device having a higher breakdown voltage than the conventional one.

[Brief description of drawings]

FIG. 1 is a diagram showing a semiconductor device of the present invention.

FIG. 2 is a diagram showing steps of manufacturing a semiconductor device of the present invention.

[Explanation of symbols]

 10 substrate 11 first semiconductor region 12 field insulating film 13 insulating film 14 conductive layer 15 second semiconductor region 16 third semiconductor region 17 fourth semiconductor region

Claims (2)

[Claims] 1. A conductive layer is provided on a main surface portion of a first semiconductor region of the first conductivity type via an insulating film, and a main surface portion of the first semiconductor region on both sides of the conductive layer has a second conductivity type second surface. In a semiconductor device having two semiconductor regions, a second semiconductor of the second conductivity type, which is in contact with the second semiconductor region and has an impurity concentration lower than that of the second semiconductor region in a part of a main surface portion of the first semiconductor region. A region is provided, and the second semiconductor region is provided along a boundary between the second semiconductor region and the first semiconductor region.
A semiconductor device comprising a fourth semiconductor region of the second conductivity type having an impurity concentration lower than that of the semiconductor region. 2. A step of forming an insulating film on a main surface of a first semiconductor region of the first conductivity type and providing a conductive layer on the insulating film; and a step of forming a third semiconductor region of the second conductivity type. A step of introducing a first impurity; a step of forming an insulating layer by CVD; a step of etching the insulating layer by anisotropic etching; and a second step for forming a second semiconductor region of the second conductivity type. And the third impurity for forming the fourth semiconductor region of the second conductivity type, and the second semiconductor region by diffusing the introduced first, second and third impurities. And a step of forming a third semiconductor region and a fourth semiconductor region, the method for manufacturing a semiconductor device.