JPS6136973A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6136973A JPS6136973A JP15965484A JP15965484A JPS6136973A JP S6136973 A JPS6136973 A JP S6136973A JP 15965484 A JP15965484 A JP 15965484A JP 15965484 A JP15965484 A JP 15965484A JP S6136973 A JPS6136973 A JP S6136973A
- Authority
- JP
- Japan
- Prior art keywords
- diffusion layer
- drain
- gate electrode
- oxide film
- side wall
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 238000009792 diffusion process Methods 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000012535 impurity Substances 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052710 silicon Inorganic materials 0.000 abstract description 10
- 239000010703 silicon Substances 0.000 abstract description 10
- 239000002784 hot electron Substances 0.000 abstract description 9
- 230000005684 electric field Effects 0.000 abstract description 7
- 238000005468 ion implantation Methods 0.000 abstract description 3
- 230000003467 diminishing effect Effects 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 238000000034 method Methods 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- -1 phosphorus ions Chemical class 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7836—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a significant overlap between the lightly doped extension and the gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明はＭＩＳ型電界効果トランジスタ（ＭＩＳＦＥＴ
）に関する。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is applied to MIS field effect transistors (MISFETs).
) regarding.
従来例の構成とその問題点
従来のｎチャンネル−ＭＩＳＦＥＴは、第１図にその要
部の断面形状を示すように、Ｐ型シリコン基板１上Ｋ、
各素子間を分離するフィールド酸化膜２と、フィールド
酸化膜２で囲まれたシリコ２ ／・ ／
ン基板１の表面に形成されたゲート酸化膜３と、ゲート
酸化膜３上に形成されたゲート電極４と、ゲート電極４
に自己整合に形成されたｎ＋拡散層からなるソース５お
よびドレイン６とで構成されている。この構造のＭＩＳ
ＦＥＴでは、ドレイン６側の空乏層内の電界によって発
生したホットエレクトロンによるデバイス劣化の問題が
あった。Structure of the conventional example and its problems A conventional n-channel MISFET, as shown in FIG.
A field oxide film 2 separating each element, a silicon 2 surrounded by the field oxide film 2, a gate oxide film 3 formed on the surface of the substrate 1, and a gate formed on the gate oxide film 3. electrode 4 and gate electrode 4
The source 5 and drain 6 are composed of an n+ diffusion layer formed in a self-aligned manner. MIS of this structure
The FET has the problem of device deterioration due to hot electrons generated by the electric field in the depletion layer on the drain 6 side.
この対策として、ドレイン領域６をｎ−拡散層と♂拡散
層とで形成したライトリ−ドープトドレイン構造（Ｌｉ
ｇｈｔｌｙ−Ｄｏｐｅｄ−Ｄｒａｉｎ、以下、ＬＤＤと
略す）のＭＩＳＦＥＴが提案されている。ＬＤＤ−ＭＩ
ＳＦＥＴは第２図（、）に断面形状を示すようＫ、ゲー
ト電極に自己整合的に形成された長さ１０分の数μｍの
が拡散層５ａ 、６ａと、このｎ−拡散層５ａ、６ａに
隣接した♂拡散層６ｂ 、ｅｂとでソース、ドレイン各
領域を形成している。ＬＤＤ−ＭＩＳＦＥＴでは、ｉ拡
散層６ｂでドレイン近傍の電界集中を大幅に緩和できる
ので、デバイス中のホットエレクトロンの発生を抑制す
る利点を有している。しかしながら、ＬＤＩ）−ＭＩＳ
ＦＥＴ３べ−７
では、第２図ａで示したように、ホットエレクトロンの
ダメージによってｉ拡散層６ｂとその上に形成された絶
縁膜７との界面に界面電荷Ｎｉｔが生成される。第２図
（ｂ）はＬＤＤ−ＭＩ ５ＦＥＴの等節回路であり、こ
のうち、ｉ拡散層の抵抗値Ｒｎ−は（１）式で与えられ
る。As a countermeasure to this problem, the drain region 6 has a lightly doped structure (Li
A highly-doped-drain (hereinafter abbreviated as LDD) MISFET has been proposed. LDD-MI
The cross-sectional shape of the SFET is shown in FIG. The male diffusion layers 6b and eb adjacent to each other form source and drain regions. The LDD-MISFET has the advantage of suppressing the generation of hot electrons in the device because the i-diffusion layer 6b can significantly alleviate the electric field concentration near the drain. However, LDI)-MIS
In the FET 3B-7, as shown in FIG. 2A, an interfacial charge Nit is generated at the interface between the i-diffusion layer 6b and the insulating film 7 formed thereon due to damage caused by hot electrons. FIG. 2(b) shows an equinodal circuit of LDD-MI 5FET, in which the resistance value Rn- of the i diffusion layer is given by equation (1).
Δ■。Δ■.
ここで、ΔＬはｎ−拡散層の長さ、ｑは単位電荷、Ｗは
チャンネル幅、ｌｌｎは電子移動度、Ｑｎ−はぎ拡散層
の面電荷である。したがって、ＬＤＤ−ＭＩＳＦＥＴで
は、ホットエレクトロンによってＮｉｔが増大し、その
結果Ｒｎ−が増大するため、ＭＩＳＦＥＴのソース、ド
レイン間の直列抵抗が増大し、ＦＥＴの伝達コンダクタ
ンスの劣化を速める欠点があった。Here, ΔL is the length of the n-diffusion layer, q is the unit charge, W is the channel width, lln is the electron mobility, and Qn is the surface charge of the strip-diffusion layer. Therefore, in the LDD-MISFET, hot electrons increase Nit, and as a result, Rn- increases, resulting in an increase in series resistance between the source and drain of the MISFET, which has the disadvantage of accelerating deterioration of the FET's transfer conductance.
発明の目的
本発明は上記の欠点を除去するためになされたもので、
ホットエレクトロンの発生を抑制すると同時に、界面電
荷の影響を小さくできるＭＩＳＦＥＴを提供することに
ある。OBJECT OF THE INVENTION The present invention has been made to eliminate the above-mentioned drawbacks.
An object of the present invention is to provide a MISFET that can suppress the generation of hot electrons and at the same time reduce the influence of interfacial charges.
発明の構成
本発明は、−導電形の半導体基板−４−に、第１のＭＩ
Ｓ型ダイオードと、同第１のＭＩＳ型ダイオードに自己
整合的に隣接して第２のＭＩＳ型ダイオードが形成され
ており、さらに同第２のＭＩＳ型ダイオードの導電膜の
一端が前記半導体基板中に形成された不純物拡散層と電
気的に接触していることを特徴としており、上記不純物
拡散層をドレインとするダブルゲ−１−Ｍｌ５ＦＥＴの
構造となっており、上記第２Ｍｌ５ダイオード直下の空
乏層又は拡散層で電界強度の緩和を行なって、ホットキ
ャリアの発生を抑制すると共に、第２ＭＩＦ５ゲートの
存在によって、界面電荷の影響を小さくすることが可能
となる。Structure of the Invention The present invention provides a first MI on a conductive type semiconductor substrate-4.
A second MIS type diode is formed adjacent to the S type diode and the first MIS type diode in a self-aligned manner, and one end of the conductive film of the second MIS type diode is formed in the semiconductor substrate. It is characterized in that it is in electrical contact with the impurity diffusion layer formed in the second Ml5 diode, and has a double-gauge-1-Ml5FET structure with the impurity diffusion layer as the drain, and the depletion layer directly under the second Ml5 diode or The electric field intensity is relaxed in the diffusion layer to suppress the generation of hot carriers, and the presence of the second MIF5 gate makes it possible to reduce the influence of interfacial charges.
実施例の説明
以下に、本発明の半導体装置の一実施例を示す第３図お
よび、その製造方法を示した第４図を参照して本発明の
詳細な説明する。DESCRIPTION OF EMBODIMENTS The present invention will be described in detail below with reference to FIG. 3 showing an embodiment of a semiconductor device of the present invention and FIG. 4 showing a method of manufacturing the same.
本発明のＭＩＳＦＥＴは、第３図にその断面形５へ一／
状を示すように、ｐ型シリコン基板１１に形成されたフ
ィールド酸化膜１２と、第１ゲート絶縁膜１３と、その
上に形成された多結晶シリコン膜からなる第１ゲート電
極１４と、同第１ゲート電極１４に自己整合に形成され
たｉ拡散層１６と、同ｎ−拡散層１６上に形成された第
２ゲート絶縁膜１７と、絶縁膜１５を介して第１ゲート
電極１４の側壁に形成された第２ゲート電極となる多結
晶シリコン膜のサイドウオール１８と、同サイドウオー
ルに自己整合に形成されたソース２ｏおよびドレイン２
１と、同ソース２０． ドレイン２１と前記サイドウ
オール１８上にのみ選択的に形成されたタングステン膜
１９とで構成されている。The MISFET of the present invention, as shown in its cross-sectional shape 5 in FIG. A first gate electrode 14 made of a polycrystalline silicon film, an i diffusion layer 16 formed in self-alignment with the first gate electrode 14, and a second gate insulating film formed on the n- diffusion layer 16. 17, a sidewall 18 of a polycrystalline silicon film that becomes a second gate electrode formed on the sidewall of the first gate electrode 14 via an insulating film 15, and a source 2o and a drain formed in self-alignment with the sidewall. 2
1 and the same source 20. It consists of a drain 21 and a tungsten film 19 selectively formed only on the sidewall 18.
上述したように、本発明によるＭＩＳＦＥＴはサイドウ
オール１８がゲート電極としての機能を有し、さらにそ
の電位がソース電位とドレイン電位に固定されている所
に特徴がある。As described above, the MISFET according to the present invention is characterized in that the sidewall 18 has a function as a gate electrode, and furthermore, the potential thereof is fixed to the source potential and drain potential.
また、本実施例の場合、サイドウオール１８の下ジョン
モードになっている。第３図に示したＭＩＳＦＥＴでは
、ドレイン２１近傍の電界強度は、このサイドウォール
ゲー）ＭＩＳダイオードによって小さくなるので、ホッ
トエレクトロンの発生を抑制することができる。また、
第２図で示したＬＤＤ−ＭＩＳＦＥＴで問題となった界
面電荷の悪影響も、サイドウオールゲート１８によって
除去できる。Further, in this embodiment, the sidewall 18 is in the lower side mode. In the MISFET shown in FIG. 3, the electric field strength near the drain 21 is reduced by the sidewall MIS diode, so that generation of hot electrons can be suppressed. Also,
The sidewall gate 18 can also eliminate the adverse effects of interfacial charges, which were a problem in the LDD-MISFET shown in FIG.
次に本発明のＭＩＳＦＥＴの製造方法を第４図の（−）
〜（、）を参照して説明する。Next, the method for manufacturing the MISFET of the present invention is shown in (-) in Fig. 4.
This will be explained with reference to ~(,).
捷ず、第４図（−）で示すようにＰ型シリコン基板１１
に、通常の選択酸化法で膜厚約８０００人のフィールド
酸化膜１２を形成し、続いてフィールド酸化膜１２で分
離されたシリコン基板表面に膜厚約２００人の第１ゲー
ト酸化膜１３を形成し、さらに、この上に周知のＣＶＤ
法でリンを約１０２０．、−３ドープした膜厚約５００
０人の多結晶シリコン膜からなる第１ゲート電極１４を
パターニングし、ゲート電極以外のゲート酸化膜を除去
した後、ゲート電極１４をマスクにして、シリコン基板
１１中にリンイオンを加速エネルギ３０ ＫｅＶ、ドー
ズ量１ｘ１０ｍの条件でイオン注入する。As shown in FIG. 4 (-), the P-type silicon substrate 11 is
Then, a field oxide film 12 with a thickness of about 8,000 thick is formed using a normal selective oxidation method, and then a first gate oxide film 13 with a thickness of about 200 thick is formed on the silicon substrate surface separated by the field oxide film 12. Furthermore, on top of this, the well-known CVD
Approximately 1020. , -3 doped film thickness approximately 500
After patterning the first gate electrode 14 made of a polycrystalline silicon film and removing the gate oxide film other than the gate electrode, using the gate electrode 14 as a mask, phosphorus ions are accelerated into the silicon substrate 11 at an energy of 30 KeV. Ion implantation is performed at a dose of 1×10 m.
次に第４図（ｂ）に示すように、シリコン基板１１に熱
処理を施してリンイオンを活性化させてｎ−拡散層１６
を形成した後、９００°Ｃのウェット酸素酸化によって
、シリコン基板上に膜厚約４００への第２ゲート酸化膜
１７を形成すると同時に、多結晶シリコン１４上にも膜
厚約１０００人の酸化膜１６を形成する。この時、シリ
コン基板より多結晶シリコン膜の方が酸化速度が速いの
は、多結晶シリコン膜に高濃度のリンがドープされてい
ることが原因している。Next, as shown in FIG. 4(b), the silicon substrate 11 is heat-treated to activate the phosphorus ions and the n- diffusion layer 16 is heated.
After forming the second gate oxide film 17 to a thickness of about 400 nm on the silicon substrate by wet oxygen oxidation at 900°C, at the same time an oxide film of about 1000 nm thick is formed on the polycrystalline silicon 14. form 16. At this time, the oxidation rate of the polycrystalline silicon film is faster than that of the silicon substrate because the polycrystalline silicon film is doped with phosphorus at a high concentration.
続いて、第４図（Ｃ）に示すように、周知のＣＶＤ法で
リンを約１ｏ２０ｃｔｎ−３ドープした膜厚約５０００
人の多結晶シリコン膜を全面に形成し、さらに反応性イ
オンエツチングによって、多結晶シリコン膜を異方性エ
ッチし、酸化膜１６を介して第１ゲート電極１４の側壁
にサイドウオ−ル１８を形成する。Subsequently, as shown in FIG. 4(C), a film with a thickness of about 5,000 doped with about 1020 ctn-3 of phosphorus was formed using the well-known CVD method.
A polycrystalline silicon film is formed on the entire surface, and the polycrystalline silicon film is anisotropically etched by reactive ion etching to form a sidewall 18 on the side wall of the first gate electrode 14 via an oxide film 16. do.
次に第４図（ｄ）に示すように、第２ゲート酸化膜１７
を除去した後、サイドウオール１８をマスクにして、シ
リコン基板中にヒソイオンを加速エネルギ４０ ＫｅＶ
、 ドーズ量６×１０ｃｒｎ の条件でイオン注入
し、熱処理によって注入イオンを活性化させて、ｎ＋拡
散層からなるソース２０およびドレイン２１を形成する
。Next, as shown in FIG. 4(d), the second gate oxide film 17
After removing, using the sidewall 18 as a mask, hiso ions are accelerated into the silicon substrate at an energy of 40 KeV.
, Ion implantation is performed at a dose of 6×10 crn, and the implanted ions are activated by heat treatment to form a source 20 and a drain 21 made of n+ diffusion layers.
最後に、第４図（、）に示したように、減圧ＣＶＤ法で
、水素と６７ノ化タングステンの混合ガスを用いて、タ
ングステン膜１９を、サイドウオール１８上と、ソース
およびドレイン上にのみ選択的に成長させることによっ
て、本発明のＭＩＳＦＥＴが完成する。Finally, as shown in FIG. 4(,), a tungsten film 19 is formed only on the sidewall 18 and on the source and drain using a mixed gas of hydrogen and tungsten 67 nitride using a low pressure CVD method. By selectively growing, the MISFET of the present invention is completed.
発明の効果
本発明の半導体装置によれば、ＭＩＳＦＥＴのドレイン
近傍の電界を緩和できるので、ホットエレクトロンの発
生を抑制でき、さらに、ドレイン側のサイドウオールゲ
ートが、ドレイン電位にな９ぺ−７Effects of the Invention According to the semiconductor device of the present invention, since the electric field near the drain of the MISFET can be relaxed, the generation of hot electrons can be suppressed.
第１図は従来のＭＩＳＦＥＴの構造を示す要部の断面図
、第２図（−）はＬＤＤ−ＭＩＳＦＥＴの断面図、同図
（ｂ）は同図（、）の等価回路図、第３図は本発明に係
るＭＩＳＦＥＴの構造を示す要部の断面図、第４図（−
） −（ｅ）は本発明のＭＩＳＦＥＴの製造方法を説明
するための図である。
１１、、、、、、ｐ型シリコン基板、１２・・・・フィ
ールド酸化膜、１３ ・−第１ゲート酸化膜、１４−・
・第１ゲート電極、１６−・・酸化膜、１６・・・・ｎ
１散層、７・・・第２ゲート酸化膜、１８・・・サイド
ウオール、１９・・・・タングステン膜、２０−・−ソ
ース、２１・・・ドレイン。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第
１ 図
第３図
第４図Figure 1 is a cross-sectional view of the main parts showing the structure of a conventional MISFET, Figure 2 (-) is a cross-sectional view of an LDD-MISFET, Figure (b) is an equivalent circuit diagram of the same figure (,), and Figure 3. is a cross-sectional view of the main part showing the structure of the MISFET according to the present invention, and FIG.
)-(e) are diagrams for explaining the method for manufacturing the MISFET of the present invention. 11,..., p-type silicon substrate, 12...field oxide film, 13...first gate oxide film, 14-...
・First gate electrode, 16-... oxide film, 16...n
1 diffused layer, 7... second gate oxide film, 18... side wall, 19... tungsten film, 20-- source, 21... drain. Name of agent: Patent attorney Toshio Nakao and 1 other person
1 Figure 3 Figure 4
Claims (1)
ドと、同第１のＭＩＳ型ダイオードに自己整合的に隣接
して第２のＭＩＳ型ダイオードが形成された構造を有し
、さらに同第２のＭＩＳ型ダイオードの導電膜の一端が
前記半導体基板中に形成された不純物拡散層と電気的に
接触していることを特徴とする半導体装置。It has a structure in which a first MIS diode and a second MIS diode are formed adjacent to the first MIS diode in a self-aligned manner on a semiconductor substrate of one conductivity type. A semiconductor device characterized in that one end of the conductive film of the second MIS type diode is in electrical contact with an impurity diffusion layer formed in the semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15965484A JPS6136973A (en) | 1984-07-30 | 1984-07-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15965484A JPS6136973A (en) | 1984-07-30 | 1984-07-30 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6136973A true JPS6136973A (en) | 1986-02-21 |
Family
ID=15698427
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15965484A Pending JPS6136973A (en) | 1984-07-30 | 1984-07-30 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6136973A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63168050A (en) * | 1986-12-29 | 1988-07-12 | Hitachi Ltd | Semiconductor device |
| JPH02276251A (en) * | 1989-04-18 | 1990-11-13 | Oki Electric Ind Co Ltd | Semiconductor device |
| WO1997041604A1 (en) * | 1996-04-29 | 1997-11-06 | Siemens Aktiengesellschaft | Lightly doped drain (ldd) mosfet |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS582066A (en) * | 1981-06-26 | 1983-01-07 | Toshiba Corp | High withstand-voltage mos transistor |
| JPS59200465A (en) * | 1983-04-27 | 1984-11-13 | Toshiba Corp | Mis-type transistor and manufacture thereof |
-
1984
- 1984-07-30 JP JP15965484A patent/JPS6136973A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS582066A (en) * | 1981-06-26 | 1983-01-07 | Toshiba Corp | High withstand-voltage mos transistor |
| JPS59200465A (en) * | 1983-04-27 | 1984-11-13 | Toshiba Corp | Mis-type transistor and manufacture thereof |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63168050A (en) * | 1986-12-29 | 1988-07-12 | Hitachi Ltd | Semiconductor device |
| JPH02276251A (en) * | 1989-04-18 | 1990-11-13 | Oki Electric Ind Co Ltd | Semiconductor device |
| WO1997041604A1 (en) * | 1996-04-29 | 1997-11-06 | Siemens Aktiengesellschaft | Lightly doped drain (ldd) mosfet |
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