JP3186298B2 - Method for manufacturing MOS type semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a MOS type semiconductor device used in outer space such as mounted on a geostationary satellite or used in a nuclear facility.

[0002]

2. Description of the Related Art MOS type semiconductor devices include a power MOSFET using only carriers and an insulated gate bipolar transistor using conductivity modulation by two kinds of carriers of electrons and holes. The insulated gate bipolar transistor is also called an IGT or a COMFET, but is hereinafter referred to as an IGBT.

FIG. 2 shows a cross-sectional structure of a conventional power MOSFET. A p-type base layer 3 is selectively formed on a surface layer of an n ⁻ high resistance layer 1 adjacent to an n ⁺ layer 2 serving as a drain layer on one side. The n ⁺ source layer 4 is selectively formed on the surface layer of the base layer 3. A gate electrode 6 is provided from the exposed surface of the n ^- layer 1 to the surface of the n ⁺ source layer 4 via a gate insulating film 51. The source electrode 7 insulated from the gate electrode 6 and the insulating film 52 is a p-type. Base layer 3 and n ⁺
A common contact is made with the source layer 4, but a deep p
⁺ Diffusion layer 8 and shallow p ⁺ diffusion layer 9 are formed. The drain electrode 10 is in contact with the n ⁺ drain layer 2. This MOSFET is usually manufactured by the following steps.

First, an n ⁺ drain layer 2 and an n ⁻ high resistance layer 1
A deep p ⁺ diffusion layer 8 and a shallow p ⁺ diffusion layer 9 are formed by impurity diffusion from the surface of the n ⁻ layer 1 of the semiconductor substrate composed of. Next, after the gate electrode 6 is formed on the surface of the high resistance layer 1 via the gate insulating film 51, a window is opened in the gate electrode 6 by photolithography. Using the gate electrode 6 with the window opened as a mask, the p-type base layer 3 is formed by diffusion. Thereafter, the n ^{+ -type} source layer 4 is formed again using the gate electrode 6 as a part of the mask, the front surface is covered with the insulating film 52, and a window for connection is opened to form the source electrode 7 and the n-type on the back surface. ^The drain electrode 10 is formed in contact with the ⁺ layer 2.
The semiconductor device manufactured in this manner is provided with a gate electrode 6.
When a positive voltage exceeding the threshold value is applied to the source electrode 7, a channel 11 is formed on the surface of the p-type base layer 3 immediately below the gate insulating film 51, and a high resistance A so-called switching element which becomes conductive when electrons are injected into the drain layer composed of the layer 1 and the low-resistance layer 2 and is turned off when the gate electrode 6 is biased to the same potential as the source electrode 7 or negatively. Has a working as.

FIG. 3 shows a conventional IGBT, in which n^-High resistance
On the lower side of layer 1, n as a buffer layer⁺P through layer 2
⁺The drain layer 12 exists, and the drain layer 12
Electrode 10 is in contact. This element has p⁺Drain layer 12
And n⁺Buffer layer 2 and n ^-Semiconductor made of high resistance layer 1
Through the same process as the power MOSFET using the body substrate
Can be manufactured. IGBT is power MOSFET
The difference in operation from T is that the drain layer 12⁺Layer
For example, from source layer 4 to channel 11, n^-Layer 1, n⁺Bag
Through the pha layer 2⁺When electrons are injected into layer 12,
In response to⁺From drain layer 12 to n⁺Through buffer layer 2
Tte n^-Holes are injected into layer 1 and n^-Layer 1 is conductivity modulated
This causes a low resistance.

[0006]

The MOSF shown in FIG.
When the ET is used in an atmosphere where a large amount of radiation exists, such as around a reactor, and is irradiated, the threshold voltage often fluctuates, and the ET does not function as a switching element. The cause of the fluctuation of the threshold voltage will be described with reference to FIG.

The operating principle of the switch function of the MOSFET is that when a positive voltage is applied to the gate electrode 6 and the source electrode 7, the gate insulating film 51 functions as a dielectric and the p-type base layer 3 immediately below the gate insulating film 51 functions as a dielectric. A negative charge is induced on the surface.
When the voltage applied to the gate electrode 6 is further increased, the amount of negative charges induced on the surface of the p-type base layer 3 also increases, and the concentration of the induced negative charges finally exceeds the impurity concentration of the p-type base layer 3. And a channel 11 are formed, and electrons injected from the n ⁺ source layer 4 pass through the channel 11 and pass through the high resistance layer 1.
To the n-type drain layer composed of the low-resistance layer 2 to be in a conductive state. On the other hand, when the gate electrode 6 is biased at the same potential as the source electrode 7 or negatively with respect to the source electrode, a negative charge is not induced in the p-type base layer 3 and the p-type base layer 3 enters a blocking state.

When the radiation 20 is irradiated to the MOSFET having such an operation principle, electrons and holes are induced in the gate insulating film 51. Among them, particularly holes are formed in the gate insulating film 51.
The positive fixed charges 21 are formed.
As a result, a negative charge 22 corresponding to the fixed charge 21 is induced in the p-type base layer 3, and the state is as if a positive charge was applied to the gate electrode. As a result, the threshold value of the voltage applied to the gate electrode 6 is reduced. For example, depending on the radiation irradiation conditions under which the absorbed dose is 10 ⁶ rad or more, the fixed charge generated in the gate insulating film 51
Even when the amount of 21 is large and the gate electrode and the source electrode are at the same potential, a conductive state occurs, and a phenomenon in which the withstand voltage apparently disappears is observed, and there is a problem that the switching function is lost.

As a countermeasure against the fluctuation of the threshold voltage or the loss of the switching function due to the irradiation of the MOS element with radiation, the maximum temperature in the step of forming the gate insulating film 51 and the steps after the formation of the gate insulating film is set to about 900 Efforts have been made to reduce the amount of fixed charges generated in the gate insulating film by lowering the temperature to not more than ° C. But,
In the current manufacturing process, a self-alignment method of forming the p-type base layer 3 and the n ⁺ source layer 4 using the gate electrode 6 as the same mask is employed. The diffusion of the base layer 3 and the annealing of the source layer 4 are performed at a high temperature. Efficient production is performed using short-time process conditions. On the other hand, when the temperature of the gate insulating film forming step and the subsequent steps are lowered to improve the radiation resistance, the gate insulating film 51 forming step, the p-type base layer 3 forming step, the source layer (4) The heating or diffusion time in the forming step or the like becomes very long, several tens to several hundred times longer than that in a normal high temperature condition, and the manufacturing process becomes inefficient.

On the other hand, when the p-type base layer 3 and the source layer 4 are formed before the gate insulating film is formed, the resist is temporarily removed during the formation of the p-type base layer in order to introduce impurities using a resist mask. Therefore, a self-alignment structure is not obtained, and as a result, the channel length becomes longer, and R
_This is a disadvantageous process in which the _{DS (on)} increases and the electrical characteristics of the device decrease.

[0011] This problem is similar in IGBTs, as well as in devices exposed to radiation for use in space. An object of the present invention is to solve the above-mentioned problems, and to perform the diffusion or annealing step at a high temperature in a short time, but to prevent the formation of the gate insulating film and the subsequent steps from being performed at a high temperature so that the characteristics by radiation irradiation can be reduced. It is an object of the present invention to provide an efficient method for manufacturing a MOS semiconductor device, which prevents deterioration and does not deteriorate characteristics due to an increase in channel length.

[0012]

In order to achieve the above object, the present invention provides a method for forming a first region of a second conductivity type selectively on a surface layer of a semiconductor layer of a first conductivity type; Selectively forming a third region of the second conductivity type at a higher impurity concentration and shallower than the first region in the first region; and selectively extending from the surface layer of the first region onto the third region. Forming a second region of the formed first conductivity type, forming a gate insulating film on the surface of the semiconductor layer, and forming a gate electrode on the gate insulating film, In a method for manufacturing a MOS type semiconductor device having a gate electrode on a portion sandwiched between a first region and a second region via a gate insulating film, the first region is introduced by introducing impurities using a first mask. Is formed, and the third region is formed by introducing impurities using the second mask. Forming a second region by introducing impurities using the first mask and the third mask after removing the second mask, and forming a gate insulating film and a gate electrode after these steps. Shall be performed. Alternatively, a step of selectively forming a first region of the second conductivity type on the surface layer of the semiconductor layer of the first conductivity type; Forming a fourth region with a high concentration and a depth, selectively forming a third region in the first region with a higher impurity concentration and shallower than the first region with a second conductivity type; Forming a second region of the first conductivity type selectively formed so as to extend from the surface layer to the third region; and forming a gate insulating film on the surface of the semiconductor layer; Forming a gate electrode thereon, comprising: a step of forming a gate electrode on the portion between the first region and the second region;
Impurity introduction for forming the fourth region is performed in advance, the first region is formed by impurity introduction using the first mask, and the third region is formed by impurity introduction using the second mask. Forming a second region by introducing impurities using the first mask and the third mask after removing the mask, and performing a step of forming a gate insulating film and a gate electrode after these steps. I do. Then, a call first mask is made of a thermal oxide film is effective. Further, it is effective that the MOS type semiconductor element to be manufactured is used in an artificial satellite or a nuclear facility.

[0013]

The first region serving as a base layer and the second region serving as a source layer of a MOSFET or an IGBT are formed by a self-alignment method using a first identical mask, thereby forming an edge of a second region sandwiching a channel forming region. The portion and the edge of the first region can be made close to each other with high accuracy, and the channel resistance becomes very small, so that the on-resistance can be kept low. Further, since the gate insulating film is formed after the formation of the first to fourth regions, even if the diffusion or annealing step is performed at a high temperature, the maximum temperature in the formation of the gate insulating film and the subsequent steps can be kept low. The amount of fixed charge generated in the gate insulating film by irradiation can be reduced.

[0014]

1 (a) to 1 (i) sequentially show the steps of manufacturing an n-channel MOS type semiconductor device according to one embodiment of the present invention.
The same parts as those in FIG. 3 are denoted by the same reference numerals. First, a thick oxide layer 13 is grown on the surface of the n ^- silicon substrate 1 on which the deep p ⁺ diffusion layer 8 has already been formed. And
A thin oxide film 14 is formed by photolithography and etching while leaving a mask portion, and boron ions (B ⁺ ) 15
If B is implanted with appropriate energy, B ⁺ is implanted only into the thin oxide film [FIG. Next, a p-type base layer 3 is formed by diffusion [FIG. Thereafter, a resist mask 16 is formed by photolithography, and B ⁺ 15 is implanted at an appropriate energy.
(c)] Then, the resist mask 16 is peeled off and annealed to form the p ⁺ layer 9 (FIG. 2 (d)). After that, a resist mask 17 is formed again by photolithography,
Using the mask and the oxide layer mask 13, arsenic ions (As
⁺ ) 18 is implanted with appropriate energy (Fig. (E)),
After the resist mask 17 is removed, annealing is performed to form the n ⁺ source layer 4 (FIG. 4F). Next, the oxide film 14 and the oxide layer mask 13 are removed by etching [FIG.
], And a gate insulating film 51 is formed on the surface [FIG.
]. Then, a polycrystalline silicon layer is formed thereon, photolithography and etching are performed to form a gate electrode 6, and an insulating layer is formed, and photolithography and patterning are performed by etching to form an insulating film 52. The structure is completed (FIG. (I)).

The material of the mask 13 is stable even at a high temperature when the base layer 3 is formed, and is unlikely to be cracked, deformed, or changed in film quality. When removing by etching in the step of 1 (g), the base layer 3 including the source layer 4 and the high impurity concentration regions 8 and 9 can be relatively easily formed with a buffered hydrofluoric acid solution.
The thermal silicon oxide film is excellent in that it can be performed without etching the surface of the drain layer 2.

According to these steps, the length l of the channel region is reduced to half or less as compared with the manufacturing method using a resist mask, and the channel resistance is reduced, so that R _{DS (on)} is also reduced. In addition, the diffusion of the base layer 3 and the annealing of the source layer 4 are performed in comparison with a manufacturing method in which the diffusion of the base layer 3, the annealing of the high impurity concentration layer 9, and the annealing of the source layer 4 are performed at a low temperature after the gate insulating film 51 is formed. Since the process can be performed at a high temperature, the process time can be shortened to a few hundredths to a few hundredths in a very short time.

FIGS. 5A to 5I show the steps of another embodiment for manufacturing an n-channel MOS type semiconductor device, and parts common to FIGS. 1, 2 and 3 are shown in FIG. The same reference numerals are given. In this case, n ^- silicon substrate 1 to form an oxide film 14 thinner on, deposited silicon oxide by a CVD method, a mask layer 23 made of polycrystalline silicon or silicon nitride on it, open windows by photolithography Is performed to form a mask pattern, and B ⁺ 15 is implanted with appropriate energy [FIG. That follow, the figure formed of the base layer 3 in (b), formation of the resist mask 16 in FIG. (C) and B ⁺ 1
5, the peeling of the resist mask 16 and the formation of the p ⁺ layer 9 in FIG. 5D, the formation of the resist mask 17 and the implantation of As ⁺ 18 in FIG.
Of the resist mask 17 and formation of the source layer 4 in FIG. 2, the oxide film 14 and the mask layer 2 in FIG.
3, formation of a gate insulating film 51 in FIG. 4H, formation of a gate electrode 6 in FIG.
The film formation and patterning of No. 2 are the same as in FIGS.

In the steps according to these steps, as in the above-described steps, the channel region length 1 is less than one half of that in the manufacturing method using only a resist mask, the channel resistance is reduced, and R _{DS (on )} Can be formed and the diffusion of the base layer 3, the annealing of the high impurity concentration layer 9 or the annealing of the source layer 4 after the formation of the gate insulating film 51 can be formed in a very short time as compared with the manufacturing method in which the annealing is performed at a low temperature.

In the above embodiment, only the n-channel element has been described. However, it is needless to say that this can be applied to the p-channel element and also to the MOS type semiconductor element other than the power MOSFET and the IGBT. .

[0020]

According to the present invention, the formation of the first region and the second region for supplying charges to the channel, in which a part of the MOS type semiconductor element is a channel formation region immediately below the gate electrode, is performed by using the gate electrode. By using a mask formed on the surface and introducing impurities by a self-alignment method without using a mask, the process of forming those regions or forming a high impurity concentration layer for preventing latch-up is performed by a gate insulating film. Since it is performed before the formation, it can be performed at a high temperature, and the process time is shortened. And the gate insulating film
It can be formed at temperatures as low as 900 ° C or less, and will not be exposed to temperatures above 900 ° C in subsequent processes.
The amount of fixed charges generated in the gate insulating film during irradiation with radiation can be reduced, and a radiation-resistant MOS semiconductor device can be manufactured at low cost. In addition, since the first and second regions can be formed by the self-alignment method, the accuracy of the positional relationship between the two is good, the channel length is short, and an element with low on-resistance can be obtained.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a process of manufacturing a MOS semiconductor device according to an embodiment of the present invention in the order of (a) to (i).

FIG. 2 is a sectional view showing the structure of a power MOSFET.

FIG. 3 is a sectional view showing the structure of the IGBT.

FIG. 4 is a cross-sectional view showing a behavior when irradiating a MOS type semiconductor element with radiation.

FIG. 5 is a sectional view showing the steps of manufacturing a MOS type semiconductor device according to another embodiment of the present invention in the order of (a) to (i).

[Explanation of symbols]

Reference Signs List 1 n ^- silicon substrate 3 p-type base layer 4 n ⁺ source layer 51 gate insulating film 6 gate electrode 13 oxide layer mask 14 oxide film 15 boron ion 17 resist mask 18 arsenic ion 23 mask layer

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/334-21/336 H01L 29/78

Claims (4)

(57) [Claims] A step of selectively forming a first region of a second conductivity type in a surface layer of a semiconductor layer of a first conductivity type; and a step of selectively forming a first region of a second conductivity type in the first region. Forming a third region with a higher impurity concentration and shallower, and forming a second region of the first conductivity type selectively formed to extend over the third region from the surface layer of the first region. Forming a gate insulating film on the surface of the semiconductor layer, and forming a gate electrode on the gate insulating film, on the portion sandwiched between the first region and the second region In a method for manufacturing a MOS type semiconductor device having a gate electrode with a gate insulating film interposed therebetween, a first region is formed by introducing impurities using a first mask, and a first region is formed by introducing impurities using a second mask. After forming the three regions and removing the second mask, the first mask and the third mask The second region is formed by introduction of impurities using click, and performing the step of forming a gate insulating film and the gate electrode after these steps MO
A method for manufacturing an S-type semiconductor device. 2. A step of selectively forming a first region of a second conductivity type on a surface layer of a semiconductor layer of a first conductivity type; and selectively forming a first region of a second conductivity type on the first region. A step of forming a fourth region with a higher impurity concentration and deeper, and a step of selectively forming a third region with a higher impurity concentration and shallower than the first region with a second conductivity type in the first region selectively; Forming a second region of the first conductivity type selectively formed so as to extend from the surface layer of the first region onto the third region; forming a gate insulating film on the surface of the semiconductor layer; Forming a gate electrode on an insulating film, and manufacturing a MOS type semiconductor device including a gate electrode on a portion sandwiched between the first region and the second region via a gate insulating film. In the method, an impurity for forming the fourth region is introduced in advance, and the first mask is used. Forming a first region by introducing impurities, forming a third region by introducing impurities using a second mask, removing the second mask, and then using the first and third masks. A method for manufacturing a MOS semiconductor device, comprising: forming a second region by introducing impurities; and performing a step of forming a gate insulating film and a gate electrode after these steps. 3. The method according to claim 1, wherein the first mask comprises a thermal oxide film.
3. A method for manufacturing a MOS semiconductor device according to item 2. 4. The method for manufacturing a MOS semiconductor device according to claim 1, wherein the manufactured MOS semiconductor device is used in an artificial satellite or a nuclear facility.