JPH05343667A - Manufacture of conductivity modulation type mosfet - Google Patents

Abstract

PURPOSE:To reduce Vth without latchup a parasitic thyristor by accelerating a switching operation of an IGBT. CONSTITUTION:A method for manufacturing an IGBT for controlling an operation of a bipolar transistor by a MOSFET formed of an emitter region, a base region, a conductivity modulation layer and a gate electrode of the transistor so formed as to be bridged thereover comprises the steps of damaging the modulation layer by irradiating it with an electron beam of the step 1, shortening a life time of minority carrier in the modulation layer, and damaging a gate oxide film by irradiating it with an electron beam of the step 3 to lower Vth.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION This invention relates to a conductivity modulation type MOS.
The present invention relates to an FET manufacturing method.

[0002]

2. Description of the Related Art FIG. 3 shows an n-channel conductivity modulation type MOS.
It is sectional drawing which shows FET (IGBT: insulated gate bipolar transistor). In FIG. 3, 1 is a p ⁺ collector region, 2 is an n ⁺ buffer region for limiting injection of carriers (holes) from the p ⁺ collector region 1, 3 is an n-type body region having high resistivity, and 4 is A p-type base region 5 formed by a method of ion-implanting a p-type impurity into a part of the main surface of the n-type body region 3 is a high-concentration n-type impurity selectively in the p-type base region 4. Is an n ⁺ emitter region formed by ion implantation or diffusion. Reference numeral 6 denotes a gate oxide film formed so as to extend across both ends of two n ⁺ emitter regions. This gate oxide film 6 is also formed on the surface of the n-type body region 3 so as to be integrated between adjacent IGBT cells. Has been formed. Reference numeral 7 is a gate electrode made of polysilicon formed on the gate oxide film 6, and 8 is a metal such as aluminum formed so as to be electrically connected to both the p-type base region 4 and the n ⁻ emitter region 5. Is a metal collector electrode formed on the back surface of the p ⁺ collector region 1.

This conductivity modulation type MOSFET (IGB
T), a positive bias voltage is applied to the gate electrode 7 and a negative bias voltage V _G (gate voltage) is applied to the emitter electrode 8 exceeding Vth (threshold voltage).
Is applied, the n ⁺ emitter region 5 and the n-type body region 3
The surface of the p-type region 41 of the base region 4 sandwiched by is inverted to n-type (inversion layer), the electrons through the inversion layer are injected from the ^n-emitter region 5 in n-type body region 3. Accordingly, holes are injected from p ⁺ collector region 1 through n ⁺ buffer region 2 into n type body region 3. In this way, the IGBT basically operates in a bipolar manner. In this IGBT, a transistor portion formed of ap ⁺ collector region 1, an n-type body region 3 and a p-type base region 4, a MOSFET formed of a gate electrode 7, a gate oxide film 6 and a p-type base region 4 is formed. It is an element that is driven by the base.

The IGBT operates in the bipolar manner as described above, conductivity modulation occurs in the n-type body region 3, the resistance of this region is significantly reduced, and the MOSFET portion undergoes conductivity modulation, so that the withstand voltage is increased. Since a sufficient base current can be supplied to the transistor portion, an element having a high breakdown voltage and a low on-voltage can be obtained as compared with an ordinary MOSFET.

However, as it is, the minority carriers (holes), which are responsible for the conductivity modulation, become the residual carriers in the n-type body region 3 at the time of switching, so that there is a problem that the high speed is obstructed and the turn-off time is long. One of the controls for shortening the lifetime of the residual carrier is electron beam irradiation. Holes (carriers) are generated by damaging the n-type body region 3 by electron beam irradiation.
Life time can be shortened. Also at this time, at the same time,
The gate oxide film 6 is also damaged, and this damage acts as + ion fixed charges, which lowers Vth.

By the way, since these damages are thermally unstable, it is necessary to anneal at a temperature sufficiently higher (about 300.degree. C. or more) than the temperature that actually occurs in order to stabilize it practically. is there. By this annealing, some of the damages formed in the n-type body region 3 and the damages in the gate oxide film 6 are recovered. The degree of this recovery depends on the temperature and the time, and in particular, the dependence on the temperature is strong. When the temperature is raised, the recovery amount of damage due to electron beam irradiation increases. By using this recovery mechanism, a device that is fast and has a strong latch-up resistance can be obtained.

[0007]

Since the higher Vth is, the more electrons can be supplied, the on-voltage can be lowered. However, since the conventional IGBT is manufactured as described above, the gate is formed by the electron beam. Even if the oxide film 6 is damaged and Vth is lowered, the damage of the gate oxide film 6 is recovered by annealing performed to stabilize these damages, and Vth does not decrease as much as in the initial design. there were. On the other hand, another method for reducing Vth is to reduce the impurity concentration of the p-type base region 4 or to reduce the thickness of the gate oxide film 6, but both have an effect on other characteristics.

According to the former method of lowering the impurity concentration of the p-type base region 4, the number of carriers is reduced, and the lateral resistance Rb (FIG. 3) of the p-type base region 4 immediately below the n ⁺ emitter region 5 is increased. The parasitic thyristor composed of the n ⁺ emitter region 5, the p-type base region 4, the n-type body region 3, and the p ⁺ collector region 1 becomes easy to operate (latch-up), and I
The safe operation area as the GBT is reduced. The latter method of thinning the gate oxide film 6 increases the input capacitance and prolongs the switching time.

The present invention has been made to solve the above problems, and an object thereof is to speed up the switching operation of an IGBT and reduce Vth without causing latch-up of a parasitic thyristor.

[0010]

In order to solve the above problems, according to the present invention, a first step of irradiating a substrate with an electron beam and a second step of heating and annealing the substrate subsequent to the first step Step, a third step of irradiating the substrate with an electron beam having lower energy than the first step, and a fourth step of heating the substrate at a temperature lower than that of the second step and annealing the substrate after the third step. It is characterized by including.

[0011]

First, the region where conductivity is modulated by the first electron beam irradiation is damaged, and the lifetime of the decimal carrier at the bottom is shortened. In the subsequent electron beam irradiation, the gate oxide film is damaged and Vth is lowered.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a flowchart showing the manufacturing flow of the present invention. First, a pre-process of forming an IGBT on a wafer will be described with reference to FIG. An n ⁺ buffer having a thickness of 10 to 20 μm and a specific resistance of 0.03 to 0.1 Ωcm is formed on the p ⁺ collector region 1 (substrate) having a specific resistance of about 0.001 to 0.02 Ω / cm containing impurities such as boron. Region 2 is formed by epitaxial growth. Further, epitaxial growth is performed continuously to form the n-type body region 3 having a high resistivity. For example, if the rated voltage is in the 1200 V class, it is formed with a specific resistance of about 50 to 60 Ω / cm and a thickness of about 100 μm.

Next, an oxide film having a thickness of about 800 to 1000 Å is formed on the entire surface on the n-type body region 3, and a polysilicon layer having a thickness of about 5000 to 6000 Å is formed on the oxide film. A gate oxide film 6 and a gate electrode 7 are formed by photolithography on these oxide film and polysilicon layer, and boron is injected by a low temperature injection method using the gate electrode 7 as a mask to form a p-type base region 4. The implantation amount at this time is about 4 to 8 × 10 ¹⁴ cm ⁻² . Further, using the gate electrode 7 as a mask, impurities such as phosphorus and arsenic are selectively implanted or diffused in the p-type base region 4 to form the n ⁺ emitter region 5. And n
^An emitter electrode 8 made of a metal such as aluminum for electrically connecting the ⁺ emitter region 5 and the p-type base region 4 is formed, and a collector electrode 9 ohmic-connected to the p ⁺ collector region 1 is formed (step S1). ).

Next, as step 1 of the present invention, this I
5 ~ at an acceleration voltage of about 0.75 MeV for a GBT wafer
An electron beam with a dose of about 15 × 10 ¹⁴ / cm ² is irradiated (step S2). At this time, the lifetime of the decimal carrier is several tens of ns or less. Also, Vth
Was about 8-10V before electron beam irradiation,
It falls to about -5 to 0V. Next, as a process 2, 330 to 3 in consideration of heat treatment at the time of assembly in a later process.
Anneal at about 50 ° C. for about 1 to 3 hours (step S
3). Then, Vth is recovered to a level about 2 V lower than that before irradiation. At that time, the lifetime of the minority carrier in the n-type body region 3 is about 200 to 300 ns.

Next, in step 3, electron beam irradiation is performed again at an acceleration voltage lower than that in the first irradiation in step 1 (for example, about 200 to 300 keV is appropriate) and a dose amount of about 10 ¹⁵ cm ^-2. (Step S4). At this time, if the energy is as low as 200 to 300 keV, the n-type body region 3 can hardly be damaged to affect the lifetime of the minority carriers, but the gate oxide film 6 can be sufficiently damaged. Vth decreases. V at this time
The th also drops to around 0V. Next, in Step 4, in order to thermally stabilize this Vth, about 300 ° C.
Then, annealing is performed for about 1 hour (step S5). At this stage, the damage that recovers at 330 to 350 ° C. or less has been recovered, so the lifetime of the minority carrier hardly changes, but the damage in the gate oxide film 6 formed by the second electron beam irradiation is small. However, Vth finally becomes about 4 to 6 V which is desirable.

FIG. 2 shows changes in Vth and carrier lifetime after each step. The lifetimes of the minority carriers in the n-type body region 3 are shortened by the processing in the steps 1 and 2,
In the processes of steps 1 to 4, Vth is lowered to a desirable level of about 5V. In addition, the lifetime of the minority carrier shortened in the processes of steps 1 and 2 does not change even after the processes of steps 3 and 4. In this example,
I mentioned n-channel IGBT, but p-channel IG
It goes without saying that it can also be applied to BT.

[0017]

As described above, according to the present invention, the lifetime of the minority carriers in the conductivity modulation layer can be shortened and Vth can be set to an appropriate value by the four steps. Low conductivity modulation type MOS
It becomes possible to manufacture a FET. Further, there is an effect that the operation of the parasitic thyristor is suppressed and the safe operation range of the conductivity modulation type MOSFET is not narrowed.

[Brief description of drawings]

FIG. 1 is a flowchart showing a manufacturing method according to an embodiment of the present invention.

FIG. 2 is an IGBT for each process shown in the flowchart of FIG.
FIG. 5 is a change diagram showing changes in Vth and lifetime of minority carriers in the n-type body region (conductivity modulation layer).

FIG. 3 is a cross-sectional view showing the structure of a conductivity modulation type MOSFET.

[Explanation of symbols]

1 p ⁺ collector region 2 n ⁺ buffer region 3 n type body region 4 p type base region 5 n ⁺ emitter region 6 gate oxide film 7 gate electrode 8 n ⁺ emitter electrode 9 collector electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 21/336

Claims (1)

[Claims] 1. A first conductivity type first impurity semiconductor layer formed on a substrate, and a second conductivity type second impurity semiconductor layer formed on the first impurity semiconductor layer. A third impurity semiconductor layer of the first conductivity type selectively formed on the second impurity semiconductor layer, and a second impurity type semiconductor layer of the second conductivity type selectively formed on the third impurity semiconductor layer. A fourth impurity semiconductor layer, an insulating layer formed on the second impurity semiconductor layer so that both ends thereof extend over the third impurity semiconductor layer and the fourth impurity semiconductor layer, and And a gate electrode formed on the insulating layer, and of a bipolar type including the first impurity semiconductor layer, the second impurity semiconductor layer, the third impurity semiconductor layer, and the fourth impurity semiconductor layer. The transistor portion is formed of the second impurity semiconductor layer and the third impurity semiconductor. In a method of manufacturing a conductivity modulation type MOSFET controlled by a MOSFET part formed of a body layer, a fourth impurity semiconductor layer, an insulating layer and a gate electrode, a first step of irradiating the substrate with an electron beam, A second step of heating and annealing the substrate after the first step, a third step of irradiating the substrate with an electron beam having lower energy than the first step, and a step of following the third step A fourth step of heating the substrate at a temperature lower than that of the second step to anneal the substrate, and a method of manufacturing a conductivity modulation type MOSFET.