JP3369862B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, more specifically, an LC device.
The present invention relates to a technique for improving the operating withstand voltage characteristic of a high withstand voltage MOS transistor for a high power supply voltage (HV-VDD) used in a D driver.

[0002]

2. Description of the Related Art A semiconductor device according to a conventional example will be described below with reference to a sectional view of an LDD type high voltage MOS transistor shown in FIG. In the figure, a gate electrode 53 is formed on a P-type semiconductor substrate (P-Sub) 51 via a gate insulating film 52. Then, the N + type source diffusion layer 54 is formed so as to be adjacent to one end of the gate electrode 53.
Is formed, an N-type drain diffusion layer 56 is formed so as to face the source diffusion layer 54 through the channel region 55, and is further separated from the other end of the gate electrode 53, and is also an N-type drain diffusion layer. An N + type drain diffusion layer 57 is formed so as to be included in 56.

Conventionally, high breakdown voltage (for example, 50 V to 60 V)
(About V), a low concentration N-type drain diffusion layer 5
6 was formed by thermal diffusion at about 1000 ° C. to 1100 ° C., and a gentle concentration gradient and a deep diffusion layer were formed.

[0004]

However, the source-drain voltage (BVDS:
Although the withstand voltage when OFF is high, the sustaining voltage (VSUS: withstand voltage when ON), which is the operating withstand voltage, cannot be increased when both the drain voltage and the gate voltage are high. In the past, the limit was about 30V at most.

The mechanism by which the above-mentioned decrease in operating breakdown voltage occurs will be described below. In such an N-channel type high breakdown voltage MOS transistor, FIG.
, The drain diffusion layer 57 is connected to the collector (N +),
The source diffusion layer 54 serves as the emitter (N +) and the semiconductor substrate 5.
1 is a base (P) lateral bipolar transistor 6
0 is formed parasitically. Even if the source-drain voltage BVDS, which is the withstand voltage when turned off, is high, the operating withstand voltage VSUS is lowered because the parasitic bipolar transistor 60 is turned on. As a result, the operating region of the N-channel type high breakdown voltage MOS transistor is limited, which makes it difficult to operate in the entire region.

The operation of the bipolar transistor 60 will be described below. As shown in FIG. 10, a gate voltage (VG) (> Vt: threshold voltage) is applied to the gate electrode 53,
The drain electrode (V
When the voltage D) (>> VG) is applied and the MOS transistor is in the ON state, a positive feedback loop (see FIG. 12) described below is formed.

That is, electrons in the channel region 62 accelerated in the depletion layer 61 near the drain diffusion layer 57 cause avalanche multiplication in the depletion layer, and electron-hole pairs are generated. The holes flow in the substrate (substrate current: ISub). The substrate current (ISub) creates a potential gradient in the semiconductor substrate 51 and raises the substrate potential.
The source diffusion layer 54-substrate 51 junction is forward biased. Electrons are injected from the source diffusion layer 54 into the substrate 51. The injected electrons reach the drain diffusion layer 57 and further avalanche multiplication occurs.

By thus forming the positive feedback of ~, a large current flows in the device, and the device is destroyed.
Therefore, in designing the N-channel type high breakdown voltage MOS transistor, the conditions are set in consideration of the phenomenon described above. First, as the substrate current (ISub) increases, the operating withstand voltage (VSUS) decreases, so the substrate current (ISub) decreases.
) Is reduced, and secondly, the condition is determined so as to reduce the substrate current (ISub) in the actually used region.

FIG. 4 is a characteristic diagram of the substrate current (ISub) -gate voltage (VG). In the figure, in the conventional N-channel type high breakdown voltage MOS transistor (shown by a dotted line in the figure), the substrate current (ISub) is The double hump characteristic appears, especially in the high gate voltage (VG) region.
) Is rising. Therefore, the operating breakdown voltage (VSUS) was low as shown in the drain current (ID) -drain voltage (VD) characteristic diagram of FIG. 5 and the operating breakdown voltage characteristic diagram of FIG.

The double hump characteristic as described above appears because the depletion layer spreads near the N + drain diffusion layer in the high gate voltage (VG) region, and the electric field concentrates there. Further, in order to improve the operating breakdown voltage (VSUS), it is conceivable to increase the ion implantation amount to increase the concentration of the N-type drain diffusion layer as shown in FIG. In the semiconductor device of 1), the breakdown voltage could not be sufficiently improved. On the contrary, N- shown in FIG.
Since the concentration of the end portion A of the type drain diffusion layer 56 also increases, the depletion layer spreads in the direction of the channel region 55 to increase the short channel effect, and the peak value of the substrate current (ISub) increases. However, problems such as an increase and a decrease in the source-drain voltage (BVDS) will occur, and conventionally there has been no effective means for improving the operating breakdown voltage.

Therefore, it is an object of the present invention to provide a semiconductor device capable of improving the operating breakdown voltage and a manufacturing method thereof.

[0012]

Therefore, the semiconductor device of the present invention is provided with a high-concentration reverse-conductivity type which is separated from the gate electrode from the other end of the gate electrode and is included in the low-concentration reverse-conductivity type drain diffusion layer. A medium-concentration reverse conductivity type layer is provided in a region extending between the drain diffusion layers. In the method for manufacturing a semiconductor device of the present invention, the gate electrode is formed via the gate insulating film after forming the low-concentration reverse conductivity type drain diffusion layer. Next, a high-concentration reverse conductivity type source diffusion layer adjacent to one end of the gate electrode and a high-concentration reverse conductivity type drain diffusion layer separated from the other end of the gate electrode and included in the low-concentration reverse conductivity type drain diffusion layer. A conductive type drain diffusion layer is formed. Subsequently, a medium-concentration reverse conductivity type layer is formed at least in a region extending from the other end of the gate electrode to the low-concentration reverse conductivity type drain diffusion layer.

Further, in the semiconductor device of the present invention, a gate electrode extending over the field oxide film, a low-concentration reverse conductivity type drain diffusion layer formed under the field oxide film, and the drain diffusion are formed. A medium-concentration reverse-conductivity-type drain diffusion layer formed so as to be continuous with the layer, and a high-concentration reverse-conductivity-type drain separated from the other end of the gate electrode and included in the middle-concentration reverse-conductivity-type drain diffusion layer. And a diffusion layer.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of a high breakdown voltage MOS transistor of the present invention will be described below with reference to the drawings showing the manufacturing method thereof. First, as shown in FIG. 1, for example, a phosphorus ion (31P +) is implanted into a semiconductor substrate 1 of one conductivity type, for example, P type, 6E12 / cm2 (6E12 means 6 times 10 to the 12th power, and so on). It is.)
By ion-implanting under the conditions of 1) and thermally diffusing it at about 1100 ° C. for 2 hours, the N-type drain diffusion layer 2 is formed, and then about 1000 Å is formed on the entire surface of the semiconductor substrate 1.
The gate insulating film 3 having the film thickness of is formed.

Next, for example, a polysilicon film is formed on the entire surface, and then the polysilicon film is patterned by using a well-known patterning technique, so that one end is on the N-type drain diffusion layer 2 as shown in FIG. Approximately 400
A gate electrode 4 having a film thickness of 0Å is formed. Then, for example, phosphorus ions (31P
+) About acceleration voltage 80 KeV, injection amount 6E15 / c
ions are implanted in m2 conditions, the N + -type source diffusion layer 5 adjacent to the other end of the gate electrode 4 as shown in FIG. 2, is spaced from a end of the gate electrode 4, and the N- type drain diffusion The N + type drain diffusion layer 6 included in the layer 2 is formed.

[0016] Then, for example, phosphorus ions (@ 31 P +) approximately acceleration voltage 160 KeV, implantation dose ion-implanted under the condition of 2E12 / cm @ 2, said from the one end of the gate electrode 4 as shown in FIG. 3 N-type drain diffusion layer N included in 2
A medium concentration N-type layer 7 is formed in the vicinity of the + -type drain diffusion layer 6. By this step, the N + type drain diffusion layer 6 can be surrounded by the medium concentration N type layer 7 while the concentration at the end of the channel side drain diffusion layer is kept low by the N− type drain diffusion layer 2.

As described above, the high concentration N + type drain diffusion layer 6 is surrounded by the medium concentration N type layer 7 so that the depletion layer does not extend to the N + type drain diffusion layer. In the semiconductor device of the present invention, the double hump characteristic disappears and the substrate current (ISub) in the high gate voltage (VG) region can be reduced as indicated by the solid line. As a result, the operating breakdown voltage (VSUS) is improved as shown in FIGS. In particular, the withstand voltage can be remarkably improved in the high gate voltage (VG) and high drain current (ID) regions.

Next, another embodiment of the present invention will be described. The semiconductor device of the present embodiment is characterized in that a low concentration N-type drain diffusion layer is ion-implanted before the field oxide film is formed to have a concentration distribution between the field oxide film and the active region. And That is, as shown in FIG. 7, the well-known LOCOS (Local oxidation of silicon) is used.
A low concentration N-type drain diffusion layer 13 is formed in a region including the field oxide film 12 formed by the method. Under the field oxide film 12 of the drain diffusion layer 13, the concentration is formed lower than the other regions in the drain diffusion layer 13. That is, first, the drain diffusion layer 1
Phosphorus ion (31P +) is implanted into the region where 3 is formed 4E12
/ Cm2 to 6E12 / cm2 by ion implantation,
In addition, after ion implantation for forming a channel stopper layer is performed under the formation region of the field oxide film 12, field oxidation is performed so that phosphorus ions (31 P +) are generated during the oxidation in the growing portion of the field oxide film 12. 1
The field oxide film 12
A low concentration N--type drain diffusion layer 13A is formed below, and the concentration of the N--type drain diffusion layer 13A (the other end of the field oxide film 12) is slightly lower than that of the N--type drain diffusion layer 13A. The high N− type drain diffusion layers 13 are formed so as to be continuous.

Then, a gate electrode 15 is formed so as to extend on the field oxide film 12 via a gate insulating film 14.
And a high-concentration N + type source diffusion layer 16 is formed so as to be adjacent to one end of the gate electrode 15.
Further, a high-concentration N + type drain diffusion layer 17 which is separated from the other end of the gate electrode 15 and is included in the N type drain diffusion layer 13 is formed.

The concentration distribution of the semiconductor device thus formed can be gradually increased from the drain end A on the channel side toward the N + type drain diffusion layer 17, as shown in FIG. By reducing the concentration of the end portion A of the − type drain diffusion layer 13 (N−− type drain diffusion layer 13A), the source-drain voltage (BVDS) can be secured and the operating breakdown voltage (VSUS) can be improved.

As described above, in the semiconductor device according to another embodiment of the present invention, the ion implantation for forming the N--type drain diffusion layer is performed before the field oxidation so that the concentration under the field oxide film 12 and the active region is increased. It can be distributed and has good workability. Further, in the semiconductor device having the above-described structure, when the operating breakdown voltage (VSUS) is further increased, the low-concentration N-type layer 7 shown in the first embodiment is surrounded so as to surround the N + -type drain diffusion layer 17. By adding
The operating withstand voltage (VSUS) can be further improved.

[0022]

As described above, according to the present invention, a region which is separated from the gate electrode from the other end of the gate electrode and extends between the high-concentration reverse conductivity type drain diffusion layers included in the low-concentration reverse conductivity type drain diffusion layer. By forming a medium-concentration reverse-conductivity type layer on the substrate, the operating breakdown voltage can be improved.

[Brief description of drawings]

FIG. 1 is a first cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a second cross-sectional view showing the method of manufacturing the semiconductor device of the embodiment of the present invention.

FIG. 3 is a third cross-sectional view showing the method for manufacturing the semiconductor device of the embodiment of the present invention.

FIG. 4 is a diagram showing a substrate current (ISub) -gate voltage (VG) characteristic of each of the semiconductor device of the present invention and the conventional semiconductor device.

FIG. 5 is a diagram showing drain current (ID) -drain voltage (VD) characteristics of a semiconductor device of the present invention and a conventional semiconductor device.

FIG. 6 is a diagram showing operating breakdown voltages of the semiconductor device of the present invention and the conventional semiconductor device.

FIG. 7 is a cross-sectional view showing the method of manufacturing a semiconductor device of another embodiment of the present invention.

FIG. 8 is a diagram showing a substrate concentration distribution of a semiconductor device according to another embodiment of the present invention.

FIG. 9 is a cross-sectional view showing a conventional semiconductor device.

FIG. 10 is a cross-sectional view of a semiconductor device for explaining a conventional mechanism of reduction in operating breakdown voltage.

FIG. 11 is a diagram showing an equivalent circuit of a conventional parasitic bipolar transistor.

FIG. 12 is a diagram showing a positive feedback loop for explaining a conventional mechanism of reduction in operating breakdown voltage.

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Claims (2)

(57) [Claims] 1. A step of forming a low-concentration reverse-conductivity-type drain diffusion layer on a semiconductor substrate of one conductivity type by ion implantation, a step of forming a gate insulating film over the entire surface of the semiconductor substrate , and a step of forming the gate insulating film thereafter. After forming a polysilicon film on the entire surface, patterning is performed and one end is diffused with the low-concentration reverse conductivity type drain.
A step of forming a gate electrode so as to extend over the layer, and then ion-implanting the gate electrode to adjoin the other end of the gate electrode.
As described above, it is common to form a high-concentration reverse conductivity type source diffusion layer.
Is separated from one end of the gate electrode, and
Concentration reverse conductivity contained in the reverse conductivity type drain diffusion layer
Type drain diffusion layer is formed simultaneously with the ion implantation.
And then from the one end of the gate electrode to the low concentration reverse conductivity.
Type high-concentration reverse conductivity type included in the drain diffusion layer
Reverse conduction of medium concentration by ion implantation near the drain diffusion layer
And a step of forming an electrotype layer . 2. A step of forming a medium-concentration reverse-conductivity-type drain diffusion layer on a one-conductivity-type semiconductor substrate by ion implantation , and then forming a field oxide film formed by field oxidation into the medium-concentration some of the opposite conductivity type drain diffusion layer is surrounded by lowering the concentration under the field oxide film, thereby forming a reverse conductivity type drain diffusion region of low concentration under the field oxide film, the Fi
From the other end of the field oxide film to the medium concentration reverse conductivity type drain
Forming such diffusion layer is continuous, then forming a gate electrode via the gate insulating film to extend onto the field oxide film, then, one end of the gate electrode by ion implantation When a high-concentration reverse conductivity type source diffusion layer is formed so as to be adjacent to
To, spaced from the other end of the gate electrode, and that it has a step of forming simultaneously a reverse conductivity type drain diffusion layer of high concentration and the ion implantation to be included in the opposite conductivity type drain diffusion layer of the concentration A method for manufacturing a characteristic semiconductor device.