JPH0728036B2 - Method for manufacturing semiconductor device - Google Patents

Description

TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device, and more specifically, a method for manufacturing a vertical IGBT (Insulated Gate Bipolar Transistor) mainly used as a power switching element. It is related to.

[Conventional technology]

In recent years, this type of power switching element has advantages such as high speed and simplification of a control circuit as an alternative to a bipolar transistor which has been generally used in the past. The shift to vertical power MOS FET (MOS Filed Effect Transistor) is attracting attention. On the other hand, however, in a vertical power MOS FET having a high withstand voltage of 500 V or more, the ON resistance is inevitably high, which makes it difficult to pass a large current.

Then, as a power switching element for solving this point, in 1981, from RCA Corporation of the United States, JP-A-56-15
A vertical IGBT, which is shown as Japanese Patent No. 0870, has been proposed. In this vertical type IGBT, by forming a conductivity type layer opposite to the source region in the drain region, injection from this reverse conductivity type layer to the high resistance layer is caused to cause conductivity modulation in the high resistance layer. Therefore, the on resistance is lowered.

Figure 4 shows the basic configuration of the vertical IGBT according to this proposal.

That is, in the configuration of the conventional example shown in FIG.
^{It is} a high-concentration p ⁺ silicon substrate of about ¹⁹ / cm ³ , and a high-concentration n ^{+ is formed} on this p ⁺ silicon substrate 1 by epitaxial growth.
A layer 2 is formed, an n ⁻ layer 3 having a low impurity concentration is formed on the high concentration n ⁺ layer 2, and DSA (Diffused Self-Alignment) is performed on the main surface of the n ⁻ layer 3. Method, the p well layer 4 and the n ⁺ type source layer 5 in the same layer 4 are selectively formed.

In the DSA method, since the diffusion window for forming the p-well layer 4 is used as a part of the diffusion window for forming the n ⁺ -type source layer 5, the channel region 6 is used for all elements. The n ⁺ type source layer 5 can be formed so as to be constant in the portion.

Then, a gate electrode 8 is formed on the channel region 6 via the gate insulating film 7, and a source electrode 9 is formed so that the n ⁺ type source layer 5 and the p well layer 4 are simultaneously ohmic-contacted. , And the drain electrode 10 is formed on the other surface of the p ⁺ silicon substrate 1 to obtain the intended vertical IGBT 11 .

Therefore, in the case of the vertical IGBT 11 having the above-mentioned configuration,
For the electron current injected from the n ⁺ type source layer 5 to the n ⁻ layer 3 through the channel region 6, holes are injected from the p ⁺ silicon substrate 1 to the n ⁻ layer 3 through the high concentration n ⁺ layer 2. And as a result,
The n ⁻ layer 3 having a high resistance can cause conductivity modulation to reduce the resistance.

[Problems to be solved by the invention]

However, in the vertical IGBT 11 with the configuration of the conventional example,
On the other hand, when this vertical IGBT 11 was turned off, high concentration
There is a problem that the turn-off time becomes long due to the residual holes injected into the n ⁺ layer 2.

Here, generally, in the vertical type IGBT 11 , in order to control the lifetime of the residual holes in the high-concentration n ⁻ layer 2, radiation such as heavy metal or electron beam is applied. The method using the line irradiation is adopted because of the good controllability of the lifetime and the good correlation between the on-voltage and the turn-off time.

However, when the electron beam irradiation method is used, the gate insulating film 7 in the NOS portion is easily damaged by the electron beam irradiation, which is one of the important characteristics of the vertical IGBT 11 of this type. There is an inconvenience that the threshold voltage V _{GS (th)} is significantly reduced.

The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a semiconductor of this kind which does not deteriorate the gate threshold voltage characteristic even after manufacturing. Device manufacturing method, in this case vertical IG
It is to provide a manufacturing method of BT.

[Means for solving problems]

In order to achieve the above object, in the method of manufacturing a semiconductor device according to the present invention, when the channel region is formed, first, the surface concentration of the channel region is set to a threshold voltage of the device structure of about 5 to 10.
It is set to ³ to 5 × 10 ¹⁷ cm ^-3 so that it becomes about V, and then, after being irradiated with an electron beam of an irradiation dose of 5 × 10 ¹³ to 8 × 10 ¹⁴ cm ^-2 , it is kept at about 300 ° C. By annealing at a temperature for 2 to 5 hours, the threshold voltage lowered during electron beam irradiation is restored to about 2 to 5V.

[Action]

That is, in the present invention, the threshold voltage of the device structure after the production is completed by irradiating the device structure in the intermediate stage with electron beam irradiation is maintained within the desired range of about 2 to 5V. In addition, the minimum threshold voltage can be maintained even when the threshold voltage is reduced due to high temperature.

〔Example〕

An embodiment of a method of manufacturing a semiconductor device according to the present invention will be described in detail below with reference to FIGS.

FIG. 1 is a sectional view showing a schematic structure of a vertical IGBT to which the method of this embodiment is applied.

That is, even in the case of the device of this embodiment, p ⁺ silicon substrate
On top of 21, a high concentration n ⁺ layer 2 is formed by epitaxial growth or the like.
2, and the n ⁻ layer 23 having a low impurity concentration are sequentially formed, and the p well layer 24 and the n ⁺ type source layer 25 in the same layer 24 are formed on the main surface of the n ⁻ layer 23 by the DSA method. And are selectively formed to obtain the channel region 26. At this time, the surface concentration of the channel region 26 is set so that the threshold voltage of the device before electron beam irradiation is about 5 to 10V.

Then, a gate electrode 28 is formed on the channel region 26 via the gate insulating film 27, and a source electrode 29 is formed so that the n ⁺ type source layer 25 and the p well layer 24 are simultaneously ohmic-contacted.
A drain electrode 30 is formed on the other surface of the p ⁺ silicon substrate 21, respectively, and then electron beams are irradiated and heat treatment is performed so that the threshold voltage of the device becomes about 2 to 5V. Is.

Therefore, in the vertical IGBT 11 according to the example configuration manufactured as described above, the threshold voltage V _{GS (th) in} the range of about 2 to 5 V is obtained after manufacturing the device, and the temperature The threshold voltage V _{GS (th)} hardly changes even with time. And also, usually 10mV considered
Even at a high temperature V _{GS (th)} of about / ° C, a value of at least about 0.7V can be guaranteed at a high temperature of 150 ° C.

Here, as in the configuration of the conventional example described above, if the threshold voltage V _{GS (th)} set before the electron beam irradiation is about 2 to 5 V, even if annealing is performed after the electron beam irradiation, this The threshold voltage V _{GS (th)} recovers only up to about 1 to 2.5 V, and at the lower limit value of 1 V, when considering the temperature reduction rate up to about 10 mV / ° C, when the temperature is about 150 ° C, Becomes a normally-on state, and this vertical IGBT cannot be controlled.

In order to set the initial threshold voltage V _{GS (th)} before electron beam irradiation in the above conventional configuration to about 2 to 5 V, refer to FIG. To obtain a surface concentration of 1 to 2 × 10 ¹⁷ cm ^-3 for 26 parts, 1 to 2 × 10
For example, B ⁺ ion implantation at ¹⁴ / cm ² is performed. In this case, however, each of the layers 25, 2 due to the decrease in the concentration of the p well region 24 immediately below the n ⁺ type source layer 25
Since the latch-up of the npnp thyristor region at 4,23,21 becomes a problem, it is usually necessary to form the p ⁺ region for the latch-up countermeasure as shown by reference numeral 24.

In contrast to such a conventional example configuration, in the case of this example configuration, the initial threshold voltage V before electron beam irradiation is
_{Since the GS (th)} is set to a high value of about 5 to 10 V, the above-mentioned channel region 26 portion can be made to have a surface concentration of ³ to 5 × 10 ¹⁷ cm ⁻³ , and the portion directly below the n ⁺ type source layer 25 can be obtained. The concentration of the p-well region 24 becomes high, which results in p ⁺
No regions have to be formed, which also simplifies the manufacturing process.

Next, a specific example according to this embodiment method will be described.

2 (a) to 2 (d) are cross-sectional views showing the outline of the manufacturing mode of the vertical IGBT to which the method of this embodiment is applied in the order of steps.

That is, in the case of this embodiment method, first,
0.1Ω on the main surface of p ⁺ type silicon substrate 21 of about 01Ω-cm
High concentration n ⁺ composed of n ⁺ impurity epitaxial layer of about −cm
Layer 22 is formed to a thickness of about 20 μm, and this high-concentration n ⁺ layer is formed.
A n ^- layer 23 with a low impurity concentration of about 50 Ω-cm is formed on
It is formed to a thickness of μm (FIG. 2 (a)).

Then, by oxidizing the surface of the n ⁻ layer 23,
After forming a gate insulating film 27 having a thickness of 1000 to 1500Å, a gate electrode 28 made of polysilicon having a thickness of about 5000Å is formed thereon. After that, by using this gate electrode 28 as a mask, by means such as ion implantation, about 5
Doped with × 10 ¹⁴ / cm ² of B ⁺ and about 10 μm by diffusion
The p-well layer 24 having a certain depth is selectively formed, and only the central portion of the window formed by the gate electrode 28 is covered with an insulating film, and the gate electrode 28 and the insulating film are used as a mask.
As and phosphorus are diffused to selectively form the n ⁺ type source layer 25 in the p well layer 24 to obtain the channel region 26 (FIG. 2B).

Further, a source electrode 29 is formed by simultaneously making ohmic contact with the n ⁺ type source layer 25 and the p well layer 24, and a drain electrode 30 is formed on the other surface of the p ⁺ silicon substrate 21. (Fig. (C)). Here, the initial threshold voltage V _{GS (th)} of the intermediate stage device structure thus obtained is about 5 to 10V.

Further, again, for the element structure at the intermediate stage, an electron beam with an irradiation amount of about 5 × 10 ¹³ to 8 × 10 ¹⁴ cm ⁻² is irradiated (FIG. (D)), and thereafter, Annealing is performed at a temperature of about 300 ° C. for about 2 to 5 hours to complete the vertical IGBT shown in FIG.

In this case, however, as shown in FIG. 3, the threshold voltage V _{GS (th)} after irradiation with the electron beam is reduced to about −4 to 5 V, but it is accompanied by the subsequent annealing treatment. No 2
Recover up to about 5V. That is, with this annealing treatment, the turn-off time gradually recovers with the annealing treatment time, while the threshold voltage V _{GS (th)} is saturated within about 2 to 5 hours. Will end up. On the other hand,
This annealing treatment is preferably performed at a temperature of about 300 ° C. for about 2 to 5 hours.

That is, as described above, it is possible to manufacture the intended vertical IGBT having the above-mentioned actions and effects.

In the method of the embodiment described above, the case where the conductivity type of each component of the element is specified has been described, but it is applicable to the case where these conductivity types are opposite to each other, and the same action,
Of course, the effect can be obtained.

〔The invention's effect〕

As described above in detail, according to the present invention, a thyristor structure is formed by having a source region, a well region, a substrate region, and a drain region which are adjacent to each other in series and have opposite conductivity types, and which has a source region and a well region. In the vertical IGBT in which the channel region is formed on the surface of and by the DSA method in a self-aligning manner and can be controlled by the gate electrode formed through the gate insulating film in the channel region, first, the formation of the channel region is performed. At this time, the surface concentration of this channel region is set to ³ to 5 × 10 ¹⁷ cm ^-3 so that the threshold voltage of the device structure is about 5 to 10 V, and then 5 × from the same surface side. After irradiation with an electron beam at a dose of 10 ¹³ to 8 × 10 ¹⁴ cm ^-2 , annealing was performed at a temperature of about 300 ° C. for 2 to 5 hours, and the threshold voltage decreased during electron beam irradiation. To about 2-5V Therefore, the threshold voltage after electron beam irradiation to the element structure at the intermediate stage and the end of manufacturing is always maintained within a range of about 2 to 5 V which is a predetermined value. In addition, the minimum threshold voltage can be effectively held even if the threshold voltage is reduced due to high temperature, and the latch-up countermeasure in this type of thyristor configuration can be automatically taken. Therefore, it has an excellent feature that the manufacturing process itself can be simplified.

[Brief description of drawings]

FIG. 1 is a sectional view showing a schematic structure of a vertical IGBT to which an embodiment of a method for manufacturing a semiconductor device according to the present invention is applied, and FIGS. FIG. 4 is a cross-sectional view showing an outline of the steps in order, and FIG. 3 is an explanatory view showing the relationship between the annealing voltage and the threshold voltage and turn-off time during the annealing process by the same method. FIG. 7 is a cross-sectional view showing a schematic configuration of a vertical IGBT according to the conventional example. 21 …… p ⁺ silicon substrate, 22 …… high concentration n ⁺ layer, 23 …… low impurity concentration n ⁻ layer, 24 …… p well layer, 25 …… n ⁺ type source layer, 26 …… channel region, 27 ... Gate insulating film, 28 ...
… Gate electrodes 28, 29 …… Source electrode, 30 …… Drain electrode.

 ─────────────────────────────────────────────────── ─── Continued Front Page (56) References Solid-State Electronics, Vol. 26 [12] (Dec. 1983), Baliga et al. "Improving the Revise Recovery of Power MOSFET Integral Diodes by Electron Irradiation," PP. 1133-1114

Claims (1)

[Claims] 1. A DSA having a source region, a well region, a substrate region, and a drain region which are opposite in conductivity type and are adjacent in series, and DSA is provided on the surface of the source region and the well region.
In a rigid IGBT that has a device structure in which a channel region is formed in a self-aligned manner by a method and is controlled by a gate electrode formed through a gate insulating film in the channel region, first, when the channel region is formed, its surface is first formed. The concentration is set to ³ to 5 × 10 ¹⁷ cm ^-3 so that the threshold voltage of the device configuration is about 5 to 10 V, and then 5
After irradiating with an electron beam of a dose of × 10 ¹³ to 8 × 10 ¹⁴ cm ^-2 ,
A semiconductor characterized by being annealed at a temperature of about 300 ° C. for 2 to 5 hours to recover the threshold voltage lowered during electron beam irradiation to about 2 to 5V. Device manufacturing method.