JP3413021B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to, for example, a conductivity modulation type semiconductor device, and more particularly to an IGBT.
It is used for an insulated gate bipolar transistor called (Insulated Gate Bipolar Transistor).

[0002]

2. Description of the Related Art Conventionally, an IGBT is a MOS-FET
It can be understood as a composite structure of BJT and
The structure and basic operation are well known (see, for example, Japanese Patent Laid-Open No. 57-120369).

FIG. 6 shows a schematic configuration of an IGBT taking an N-channel type as an example. For example, P-type collector layer 1
01, a high resistance N ⁻ -type base layer 102 having a low impurity concentration.
Are formed. On the surface of the N ⁻ type base layer 102, P is formed by a DSA (Double Diffusion Self Align) method.
A type base layer 103 and an N ⁺ type emitter layer 104 are selectively formed on the surface of the P type base layer 103, respectively.

A thin insulating film 105 is formed on the surfaces of the N ⁻ type base layer 102 and the P type base layer 103.
A polysilicon gate electrode 106 is provided via the. In addition, the N ⁺ type emitter layer 104 and the P
A metal emitter electrode 107 is provided on the surface of the mold base layer 103 so as to short-circuit each other.

Further, the polysilicon gate electrode 10
6 to the metal gate electrode 108, and also to the P-type collector layer 101 to connect to the metal collector electrode 109.
Are provided respectively.

Next, a general method of manufacturing the N-channel IGBT will be described. First, the P-type collector layer 1
01 as a P ⁺ type substrate, on which an N ⁻ type base layer 1
02 is vapor-grown to form a P ⁺ -N ^- wafer.

After that, an insulating film 105 is formed on the surface of the N ^-- type base layer 102, and a polysilicon gate electrode 106 is further formed thereon. Next, the polysilicon gate electrode 106 is partially opened, and the P-type base layer 103 is formed using this as a mask. In addition, the P-type base layer 103
The upper insulating film 105 is partially opened, and the N ⁺ type emitter layer 104 is formed by using the polysilicon gate electrode 106 and the insulating film 105 as a mask.

Then, an insulating film 105 is formed again on the polysilicon gate electrode 106 and the P-type base layer 103, and the insulating film 105 is partially removed. Then, the polysilicon gate electrode 106 and the N ⁺ -type emitter layer 104 are formed. A metal is deposited on the exposed portion of the P-type base layer 103 including the metal gate electrode 108 and the metal emitter electrode 107, respectively.

Thereafter, a metal collector electrode 109 is formed under the P ⁺ -type collector layer 101, and the IGB shown in FIG.
T is obtained. Even if a P ⁺ -N ^- wafer is used in which the N ⁻ -type base layer 102 is an N ⁻ -type substrate and the P-type collector layer 101 is provided by impurity diffusion, the IGB is similarly used.
T is obtained.

Next, the operating principle of the N-channel IGBT described above will be described. When turning on the IGBT, the metal emitter electrode 107 is grounded and the metal collector electrode 1 is turned on.
09, a positive voltage is applied to the metal gate electrode 10
8 by applying a positive voltage to the metal emitter electrode 107.

That is, when a positive voltage is applied to the metal gate electrode 108, an inversion channel is formed on the surface of the P-type base layer 103 like the MOS-FET, and the N ⁺ -type emitter layer 104 passes through this inversion channel. Electrons are introduced into the N ⁻ type base layer 102.

On the other hand, holes are injected from the P-type collector layer 101 into the N ^-- type base layer 102 so as to satisfy the charge neutrality condition, and the P-type collector layer 101 and the N ^-- type base layer 102 are separated from each other. The PN junction becomes forward biased.
As a result, the N ⁻ type base layer 102 causes conductivity modulation, and brings the element into a conductive state.

As described above, when the N ^- type base layer 102 having a high resistance is subjected to conductivity modulation, the IGBT is turned on.
The resistance component becomes extremely small. For this reason, even in a high breakdown voltage element having a low concentration of the N ⁻ type base layer 102 and a thick high breakdown voltage element, the characteristics of extremely low on-resistance can be obtained.

On the other hand, turn-off of the IGBT is realized by applying a negative voltage to the metal gate electrode 108 with respect to the metal emitter electrode 107. That is, when a negative voltage is applied to the metal gate electrode 108, the inversion channel disappears and the inflow of electrons from the N ⁺ type emitter layer 104 stops. However, electrons are still present in the N ⁻ -type base layer 102.

Most of the holes accumulated in the N ^- type base layer 102 flow out to the metal emitter electrode 107 through the P-type base layer 103, but a part of the holes accumulate in the N ^- type base layer 10.
It recombines with the electrons existing in 2 and disappears.

When all the holes accumulated in the N ^-- type base layer 102 have disappeared, the device enters the blocking state and the turn-off is completed. The IGBT is an excellent element that exhibits extremely low on-resistance among the high breakdown voltage elements, but since it is a minority carrier element, the turn-off time is MOS-.
It is longer than unipolar elements such as FETs.

Therefore, in order to speed up the turn-off time of the IGBT, conventionally, for example, as shown in FIG. 7, diffusion of heavy metals such as Au and Pt or irradiation with radiation such as neutron rays, gamma rays, and electron beams has been used. ^- type base layer 1
A carrier lifetime is shortened by generating a defect 110 which becomes a recombination center in the whole area of 02.

However, in this method, the turn-off time is improved, but at the same time, the carrier lifetime in the entire region of the N ⁻ type base layer 102 is shortened. Therefore, conduction in the entire region of the N ⁻ type base layer 102 is reduced. The degree of degree modulation also decreases, and there is a problem that the low on-resistance characteristic, which is the greatest advantage of the IGBT, is deteriorated.

In recent years, instead of the above-mentioned lifetime control method by diffusion of heavy metals or irradiation with radiation, for example, as shown in FIG. 8, by irradiating an ion species such as He ³⁺ or H ²⁺ , the N ^- type base layer is irradiated. Attempts have been made to locally shorten the lifetime in the depth direction within 102.

Ion species such as He ³⁺ and H ²⁺ change the accelerating voltage at the time of irradiation, or irradiate the Al thin film as an absorber with a constant accelerating voltage, thereby irradiating the N ⁻ -type base layer 102 with Defect 11 which becomes a recombination center at an arbitrary depth
0 can be generated locally.

[0021] When the life time control method according to the ion beam irradiation, N ^- since -type base layer 102 defects 110 optionally localized in the depth direction of the can forming, N ^- type base layer 102 in The hole distribution can be optimally controlled (that is, the degree of conductivity modulation can be optimized), and the speed can be increased without increasing the on-resistance as compared with the case of the lifetime control method by radiation irradiation.

However, the above-mentioned lifetime control method by ion beam irradiation still has the following problems. The blocking voltage of the IGBT is
It is substantially determined by the base open breakdown voltage V _CBO of the PNP-Tr parasitic in the IGBT. Therefore, in the blocking state, for example, as shown in FIG. 9, the depletion layer 111 grows and the base layer (N ⁻ type base layer 102) of the parasitic PNP-Tr is depleted.

At this time, the Early effect occurs in the PNP-Tr, and the effective base width W _B is modulated (shortened). As the effective base width W _B becomes shorter, the grounded-emitter current gain β _o of the parasitic PNP-Tr increases based on the following equation (2).

[0024]

[Equation 2]

However, L _P is the diffusion length of holes, W _B is the effective base width, and N _E and N _B are the emitter concentration and the base concentration, respectively. Meanwhile, related to the open-base breakdown voltage V _CBO and its leakage current I _{CB O} of PNP-Tr, the emitter opening breakdown voltage V _CEO and its leakage current I _CEO, number of the following formula 3, such as the number 4 .

[0026]

[Equation 3]

[0027]

[Equation 4]

Here, the increase of the grounded emitter current gain β _o of the parasitic PNP-Tr accompanying the modulation of the effective base width W _B is the decrease of the emitter open breakdown voltage V _{CEO and} the increase of its leakage current I _CEO , that is, This suggests that it causes a decrease in V _CES and an increase in I _CES of the IGBT, and is unstable in terms of reliability.

As described above, when the lifetime of the entire N ⁻ type base layer 102 is reduced by electron beam irradiation or the like, depletion progresses, and even if the effective base width W _B becomes small, non-depletion is performed. Since the hole diffusion length L _{P in the} charge region is sufficiently low, the grounded emitter current gain β of the parasitic PNP-Tr is
_o hardly increases.

On the other hand, the low lifetime layer (defect 1) localized in the N ^-- type base layer 102 by ion beam irradiation.
In the case of forming 10), if the localized low lifetime layer is taken into the depletion layer 111, the grounded emitter current gain β _o of the parasitic PNP-Tr rapidly increases. This causes V _CES to drop and I _CES to increase, causing thermal runaway and sometimes thermal breakdown of the device. Next, problems in switching operation will be described. The collector current I _{C of the} IGBT is represented by the following equation (5).

[0031]

[Equation 5]

Here, Z is the channel peripheral length, L is the channel length, μn is the mobility, C _o is the gate insulating film capacitance, V _G is the gate voltage, V _T is the threshold voltage, and V _C is the collector voltage. .

Also in this switching operation, when the low lifetime layer localized at the time of switching turn-off is taken into the depletion layer 111 as in the above case, the grounded emitter current gain β _o of the parasitic PNP-Tr is reduced. With the increase, the collector current I _{C of the} IGBT is changed, which is a current-voltage product at the time of switching off.
There is a problem that switching turn-off loss increases (see FIG. 10).

[0034] With respect to these issues, for example, N ^-
It can be solved to some extent by designing the thickness and concentration of the mold base layer 102 so as to satisfy Expression 6 below.

[0035]

[Equation 6]

Where W _B is the effective base width, ε _S , ε _O
Is the permittivity and vacuum permittivity of silicon, Vbi is the internal voltage of the PN junction between the P-type base layer 103 and the N ⁻ type base layer 102, and V is the collector voltage ((desired withstand voltage value) is negative in the case of reverse bias. , N _B is the base concentration,
q is the amount of charge.

The first term of the equation (6) represents the width of the depletion layer 111 at a given applied voltage, and the second term
The term is the distribution width of the defects 110 formed by ion beam irradiation.

The defect distribution width in the case of irradiating silicon with ion species such as He ³⁺ , H ²⁺ is about 40 μm according to the SR (Spreding Resistance) method, as shown in FIG. It is hardly affected by the dose of ionic species and the substrate concentration.

Therefore, if the effective base width W _B is set so as to have a desired breakdown voltage so as to satisfy the above equation (6), the localized low lifetime formed by the irradiation of the ion beam is achieved. Even if the layer breaks down, it stays within the non-depleted region, thus maintaining a sufficiently low grounded emitter current gain β _o .

That is, if the effective base width W _B is set to 40 μm or more, modulation (increase) of the grounded emitter current gain β _o of the parasitic PNP-Tr can be suppressed, deterioration of breakdown voltage and increase of leakage current, and It is possible to avoid problems such as an increase in switching turn-off loss.

However, even when the condition of the equation (6) is satisfied, the following problem still occurs. That is, as described above, the turn-off of the IGBT is mostly controlled by the carrier lifetime, but like the other bipolar devices such as BJT, the P-type base layer 103 and the N ⁻ -type base layer 102 are turned off at the time of turn-off.
The depletion layer formed by reversely biasing the PN junction of the and is also largely influenced by the minority carriers (holes) in the N ⁻ type base layer 102 being forced out.

Therefore, when the power supply voltage is equal to or lower than the withstand voltage of the element (usually about half of the standard is used in most cases), for example, as shown in FIG. The tail current increases due to the excess area and the large excess minority carrier remaining.

This problem can be solved by simply increasing the dose amount at the time of ion beam irradiation, but as a matter of course, the on-voltage sharply deteriorates. Incidentally, in the prior art, for example, as shown in FIG. 13, a structure in which an N ⁺ type buffer layer 120 is provided between a P type collector layer 101 and an N ⁻ type base layer 102 (P ⁺ −N ⁺ −N ⁻ wafer). ) IGBT has also been put to practical use, but in this IGBT as well, the above-mentioned IGBT
There was a problem similar to T.

[0044]

As described above, in the conventional case, the effective base width W _B is reduced by reducing the breakdown voltage, increasing the leakage current, and increasing the switching turn-off loss.
In the case of avoiding it by setting the withstand voltage, there is a problem that the tail current increases when the power supply voltage is low.

Therefore, according to the present invention, the breakdown voltage is not deteriorated and the leakage current is not increased, the reliability is high, the tail current is small even when the power supply voltage is relatively low, and the on-voltage and the turn-off time are small. It is an object of the present invention to provide a semiconductor device capable of improving the trade-off.

[0046]

In order to achieve the above object, in a semiconductor device of the present invention, a first region formed of a semiconductor layer of a first conductivity type and one of the first region are formed. A second region formed of a semiconductor layer of the second conductivity type selectively formed on the main surface, and a second region formed of a semiconductor layer of the first conductivity type selectively formed on one main surface of the second region. The third region, the fourth region formed of the second conductivity type semiconductor layer formed on the other main surface of the first region, and at least a part of the second region, A control electrode formed on the second region via an insulating film, a first electrode formed on the second region and including at least a part of the third region, and a fourth region. a second conductive electrode formed on the upper, arranged localized in the first region, the fourth region
It is composed of a plurality of recombination center lattice defects having a deeper recombination order .

According to the semiconductor device of the present invention, it is possible to substantially shorten the lifetime of almost the entire non-depleted region. This makes it possible to reduce the excess minority carriers in the non-depleted region even when the external power supply voltage is relatively low and the non-depleted region remains excessive.

[0048]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a semiconductor device of conductivity modulation type according to an embodiment of the present invention, so-called IGBT (Insulated Gate Bipolar Transistor).
FIG. Here, an N-channel type IGBT will be described as an example of a 1200V-system IGBT.

For example, a P-type base layer (second region) 12 is selectively formed on the surface of a high resistance N ^-- type base layer (first region) 11 having a low impurity concentration. This P
An N ⁺ type emitter layer (third region) 13 is selectively formed on the surface of the type base layer 12.

Then, on the surface of the N ⁻ type base layer 11 and the P type base layer 12 adjacent to the N ⁻ type base layer 11, a polysilicon gate electrode (control layer) is formed via a thin insulating film 14. The electrode) 15 is provided.

The surfaces of the N ⁺ type emitter layer 13 and the P type base layer 12 sandwiched by the N ⁺ type emitter layer 13 are short-circuited to each other.
A metal emitter electrode (first electrode) 16 is provided.

Further, the polysilicon gate electrode 15
A metal gate electrode 17 is provided above and connected to it. On the other hand, a P-type collector layer (fourth region) 18 is formed on the back surface of the N ⁻ type base layer 11, and a metal collector electrode (second electrode) 19 is provided so as to be connected to the P-type collector layer 18. ing.

Then, in the N ^-- type base layer 11,
For example, 20 μm from the contact surface with the P-type collector layer 18
The first low lifetime layer (recombination center lattice defect) 21 having a defect peak at about m m and the second low lifetime layer having a defect peak at about 60 μm from the contact surface with the P-type collector layer 18. The lifetime layers 22 and 22 are arranged respectively.

The first and second low lifetime layers 21,
The formation of 22 is performed, for example, by irradiating H ²⁺ ion species from the side of the metal collector electrode 19 using Al thin films having different thicknesses as absorbers.

Next, a method of manufacturing the above N-channel IGBT will be described. First, for example, silicon is doped with impurities such as phosphorus to prepare a substrate (N ⁻ -type base layer 11) having a low impurity concentration and a specific resistance of 70 Ω · cm and having a thickness of 280 μm.

Then, a BSG film is CVed on the back surface of the substrate.
After being formed by the D (Chemical Vapor Deposition) method, the P-type collector layer 18 is formed with a thickness of 80 μm using this as a diffusion source.
Diffusion is formed with a thickness of m.

After removing the BSG film, the N ^-- type base layer 1
The surface of No. 1 is oxidized to form an insulating film 14 with a film thickness of about 1000 angstroms, and polysilicon is formed thereon with a thickness of about 5000 angstroms.

After that, polysilicon is partially opened to form a polysilicon gate electrode 15, and boron is 8 μm with the polysilicon gate electrode 15 as a mask.
The P-type base layer 12 is formed by being diffused with a certain thickness.

Then, the insulating film 14 between the polysilicon gate electrodes 15 is partially opened, and it is used as a mask for forming an emitter, and ions of As are used under the condition of a dose amount of about 5 × 10 ¹⁵ cm ^−2. Implantation is performed and heat treatment is performed to form an N ⁺ -type emitter layer 13 in the P-type base layer 12.

After again forming the insulating film 14 on the surface by the CVD method to a thickness of about 15000 Å,
The insulating film 14 is selectively removed, and the polysilicon gate electrode 15, the P-type base layer 12 and the N ⁺ are removed.
Opening is performed so that parts of the mold emitter layer 13 are exposed.

Then, a metal film of Al or the like is formed on the surface so as to fill the inside of the opening, and is patterned to form the metal emitter electrode 16 and the metal gate electrode 17, respectively.

On the other hand, V or Au is formed on the surface of the P type collector layer 18 formed on the back surface of the N ⁻ type base layer 11.
A metal film such as a metal film is formed on the metal collector electrode 19
And

On the metal collector electrode 19, 75 μ
An Al thin film having a thickness of about m is formed as an absorber to protect the back surface of the element, and from this back surface, an acceleration voltage of 4.5 MeV and a dose amount of 1 × 10 ¹⁰ to 1 × 10 ¹² cm ^{-2 are applied.}
Under the conditions described above, the first irradiation of H ²⁺ is performed to form the first low lifetime layer 21 in the N ⁻ type base layer 11.
At this time, in the first low lifetime layer 21, a defect peak is formed in the vicinity of 20 μm from the P-type collector layer 18, and the distribution width is ± 20 μm with respect to the peak position.

Subsequently, the back surface of the element is protected by using an Al thin film having a thickness of about 35 μm as an absorber, and from this back surface,
Acceleration voltage 4.5 MeV, dose amount 1 × 10 ⁹ to 1 × 10
¹¹ under conditions of m ^-2, performs irradiation of the second H ^2+, N ^-
A second low lifetime layer 22 is formed in the mold base layer 11. At this time, in the second low lifetime layer 22, a defect peak is formed in the vicinity of 60 μm from the P-type collector layer 18, and the distribution width is ± 20 μm with respect to the peak position.

As described above, in the structure shown in FIG.
The N-channel type IGBT is completed. FIG. 2 shows a state of hole distribution in the N ⁻ type base layer 11 with the formation of the low lifetime layers 21 and 22 in the N channel type IGBT described above.

According to this structure, even if the power supply voltage is relatively low and the non-depleted region 11a remains excessively,
Since the non-depleted region 11a has a substantially reduced lifetime almost entirely by the first and second irradiations with H ²⁺ , the excess minority carriers in the non-depleted region 11a are small and the tail current is reduced. It can be reduced efficiently.

That is, in the case of this IGBT, the thickness of the N ⁻ -type base layer 11 satisfies the condition of the equation (6) so that the effective base width W _B becomes about 190 μm.
Is set to. As a result, for example, the power supply voltage is 6
At 00V, the extension width of the depletion layer 11b is about 110 μm, and the remaining width of the non-depletion region 11a is about 80 μm, but since the localized second low lifetime layer 22 exists near 60 μm. The entire lifetime in the non-depleted region 11a is completely reduced.

The dose of H ^{2+ for} the second irradiation is lower than that for the first irradiation by one order, that is, the low lifetime layer 22 by the second ion beam irradiation is the low lifetime layer by the first ion beam irradiation. Since it is shallower than the recombination order of No. 21, the on-voltage is not extremely increased.

Moreover, the low lifetime layer 21 localized and formed by the first irradiation of H ²⁺ causes parasitic P
Since the grounded-emitter current gain β _o of NP-Tr is rate-controlled, the power supply voltage rises, and the low lifetime layer 22 formed by being localized by the second irradiation of H ²⁺ is taken into the depletion layer 11b. Even in this case, the modulation of the grounded-emitter current gain β _o can be ignored, and the breakdown voltage is not lowered and the I _CES and the switching turn-off loss are not increased.

FIG. 3 shows a trade-off curve in the IGBT (element of the present invention) having the above-mentioned structure, in comparison with the conventional element. Incidentally, here, an IGBT formed by forming a localized low lifetime layer by one-time ion beam irradiation is shown as a conventional element.

As is apparent from this figure, according to the element of the present invention, the fall time (switching characteristic) tf is obtained even when the power supply voltage is equal to or lower than the element withstand voltage (600 V).
It can be seen that the collector-emitter saturation voltage V _CE (on-voltage characteristic) with respect to is smaller than that of the conventional device, and the trade-off is improved.

As described above, substantially the entire lifetime of the non-depleted region in the N ^-- type base layer can be shortened. That is, the localized low lifetime layers are formed in the N ⁻ -type base layer at the positions of 20 μm and 60 μm from the P-type collector layer. As a result, even when the external power supply voltage is relatively low and the non-depletion region is excessively left, the entire lifetime of the non-depletion region can be shortened. Therefore, the excess minority carriers in the non-depleted region can be reduced, and the tail current can be efficiently reduced.

Moreover, since the low lifetime layer localized and formed near 60 μm is shallower than the recombination order of the low lifetime layer localized and formed near 20 μm, the on-voltage is reduced. It does not cause an extreme increase in

Further, since the low lifetime layer formed localized near 20 μm is designed not to be taken into the depletion layer, the breakdown voltage is lowered and the leakage current is increased. There is no increase in switching turn-off loss.

In the above-described embodiment of the present invention, the case of irradiating H ²⁺ for forming the low lifetime layer has been described, but the present invention is not limited to this, and for example, He ³⁺ or heavy ^ions may be used. The same can be done by irradiating with protons (Deuteron) or the like.

Further, instead of performing the ion beam irradiation twice, the ion beam irradiation may be performed a plurality of times with different ranges, if necessary. Further, it is possible to combine not only ion beam irradiation but also light electron beam irradiation.

Further, as shown in FIG. 4, the P-type collector layer 18 'may be formed to have an uneven shape.
In this case, if the effective base width W _B is determined by the convex portion of the P-type collector layer 18 ′, an effect substantially equivalent to that of the IGBT having the structure shown in FIG. 1 can be expected.

Moreover, in the concave portion, the effective base width W _B becomes longer, the grounded-emitter current gain β _o in this region becomes larger, and the IGBT having the structure shown in FIG. Is more advantageous than.

Further, as shown in FIG. 5, the N ⁺ type buffer layer 3 is provided between the N ⁻ type base layer 11 and the P type collector layer 18.
It is also applicable to an IGBT having a configuration in which 0 is provided. Furthermore, it is not limited to the 1200V system N-channel IGBT,
For example, it goes without saying that it can be applied to a P-channel type IGBT in the same manner.
The same is applicable to BT. Of course, various modifications can be made without departing from the scope of the invention.

[0080]

As described above in detail, according to the present invention, the tail current is highly reliable without causing deterioration of breakdown voltage and increase of leakage current and also when the power supply voltage is relatively low. It is possible to provide a semiconductor device that is small and that can improve the trade-off between the on-voltage and the turn-off time.

[Brief description of drawings]

FIG. 1 is a sectional view showing a schematic configuration of an N-channel type IGBT according to an embodiment of the present invention.

FIG. 2 is an N-type IGBT in which N
^- schematic diagram showing the state of distribution of holes in the mold base layer.

FIG. 3 is a schematic diagram showing a trade-off curve of an N-channel IGBT in comparison with a conventional device.

FIG. 4 is a schematic cross-sectional view of an N-channel type IGBT according to another embodiment of the present invention.

FIG. 5 shows an N according to still another embodiment of the present invention.
FIG. 3 is a schematic cross-sectional view of a channel type IGBT.

FIG. 6 is shown for explaining the related art and its problems,
FIG. 3 is a schematic cross-sectional view of an N-channel type IGBT.

FIG. 7 is a schematic diagram similarly shown for explaining a low carrier lifetime method by electron beam irradiation.

FIG. 8 is a schematic diagram for explaining a low carrier lifetime method by ion beam irradiation.

FIG. 9 is a schematic diagram showing growth of a depletion layer and its equivalent circuit in a blocking state of an IGBT.

FIG. 10 is a schematic diagram showing an IGBT turn-off waveform.

FIG. 11 is a schematic diagram for explaining the dependency of the dose distribution on the defect distribution profile due to ion beam irradiation.

FIG. 12 is a schematic diagram similarly illustrating the dependence of the tail current on the power supply voltage.

FIG. 13 is a schematic cross-sectional view showing another configuration of the N-channel type IGBT similarly.

[Explanation of symbols]

11 ... N ^- type base layer 11a ... Non-depleted region 11b ... Depletion layer 12 ... P type base layer 13 ... N ⁺ type emitter layer 14 ... Insulating film 15 ... Polysilicon gate electrode 16 ... Metal emitter electrode 17 ... Metal gate electrode 18 ... P-type collector layer 19 ... Metal collector electrode 21 ... First low lifetime layer 22 ... Second low lifetime layer

Claims (7)

(57) [Claims] 1. A first region made of a semiconductor layer of a first conductivity type, and a second region made of a semiconductor layer of a second conductivity type selectively formed on one main surface of the first region. A third region formed of a semiconductor layer of the first conductivity type selectively formed on one main surface of the second region, and a second conductivity type of the second region formed on the other main surface of the first region. A fourth region including a semiconductor layer, and at least a part of the second region, the first region
The control electrode formed on the area of the second electrode via an insulating film, and the second electrode including at least a part of the third area.
Of a first electrode formed on a region, and a second conductive electrode formed on the fourth region, the disposed localized in the first region, said fourth
A semiconductor device having a plurality of recombination center lattice defects having a deeper recombination order closer to the region . 2. A first region made of a semiconductor layer of a first conductivity type, and a second region made of a semiconductor layer of a second conductivity type selectively formed on one main surface of the first region. A third region formed of a semiconductor layer of the first conductivity type selectively formed on one main surface of the second region, and a second conductivity type of the second region formed on the other main surface of the first region. A fourth region including a semiconductor layer, and at least a part of the second region, the first region
The control electrode formed on the area of the second electrode via an insulating film, and the second electrode including at least a part of the third area.
A first electrode formed on a region of a second conductive electrode formed on the fourth region, and a plurality of recombination centers lattice defects disposed localized in the first region comprising a, among the plurality of recombination centers lattice defects, the deepest recombination
A recombination center lattice defect with an order is
The peak value is such that the width of the non-depleted region is at least 40 μm or less.
Near 20 μm from the other main surface of the above-mentioned first region
The semiconductor device characterized in that 3. A first region made of a semiconductor layer of a first conductivity type, and a second region made of a semiconductor layer of a second conductivity type selectively formed on one main surface of the first region. A third region formed of a semiconductor layer of the first conductivity type selectively formed on one main surface of the second region, and a second conductivity type of the second region formed on the other main surface of the first region. A fourth region including a semiconductor layer, and at least a part of the second region, the first region
The control electrode formed on the area of the second electrode via an insulating film, and the second electrode including at least a part of the third area.
A first electrode formed on a region of a second conductive electrode formed on the fourth region, and a plurality of recombination centers lattice defects disposed localized in the first region comprising a first region, almost the entire surface of the non-depleted region, the real
A semiconductor device characterized by a qualitatively reduced lifetime . 4. A first region made of a semiconductor layer of a first conductivity type, and a second region made of a semiconductor layer of a second conductivity type selectively formed on one main surface of the first region. A third region formed of a semiconductor layer of the first conductivity type selectively formed on one main surface of the second region, and a second conductivity type of the second region formed on the other main surface of the first region. A fourth region including a semiconductor layer, and at least a part of the second region, the first region
The control electrode formed on the area of the second electrode via an insulating film, and the second electrode including at least a part of the third area.
A first electrode formed on a region of a second conductive electrode formed on the fourth region, and a plurality of recombination centers lattice defects disposed localized in the first region comprising a first region of the effective width (W _B) and its concentration (N _B) Contact
And the breakdown voltage (V) is expressed by the following equation 1 (However, ε _S and ε _O are the permittivity and
And vacuum permittivity, V _bi is PN between the second region and the first region
The internal voltage of the junction, q is the amount of charge. ) Is substantially satisfied
A semiconductor device comprising: 5. The plurality of recombination center lattice defects are He.
^{5. The element according to} any one of claims 1 to 4, which is formed by irradiation with an ionic species of any one of ³⁺ , H2 ⁺ and deuteron.
A semiconductor device according to any one of the above. Region of wherein said fourth semiconductor device according to any one of claims 1 to 4, characterized in that contact surface between the first region is formed to have an uneven. 7. A fifth region made of a semiconductor layer of the first conductivity type is further formed between the first region and the fourth region. Through 4
The semiconductor device according to any one of claims.