JPS63186476A - Vertical mosfet - Google Patents

Abstract

PURPOSE:To obtain a conductivity modulation type MOSFET which can properly suppress the operation of a parasitic bi-polar transistor to improve the secondary breakdown resistance and can improve the manufacturing yield by providing a source electrode connected to a body region and a source region through a silicide layer formed in the body region. CONSTITUTION:A body region 3 of a second conductivity type is formed on the surface side of a base region 2 of a first conductivity type which effectively acts as a drain, and a source region 4 of the first conductivity type is formed on the surface side of the body region 3. And on the body region 3 between the source region 4 and said base region 2, a gate electrode 7 inducing a channel 5 in the body region 3 is provided through a gate insulating film 6. Further, through a silicide layer 8 formed in said body region 3 and becoming a conductor, a source electrode 12 connected to the body region and the source region 4 is provided. For instance, on an Si wafer becoming a P<+> anode region 1, said respective regions are formed wherein the first conductivity type is an N-type, and an anode electrode 13 is further provided, constructing a conductivity modulation type vertical MOSFET.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Field of Application) The present invention relates to a vertical MO8FET in which the operation of a parasitic bipolar transistor is suppressed.

(Prior art) The conventional vertical MO8FET has been replaced with a conductivity modulated vertical MO8FET.
Taking FET as an example, this will be explained using Fig. 5 (IEDM8
3. p79-83).

In FIG. 5, 21 is a P4 anode region that serves as a hole injection source, 23 is an N base region that essentially acts as a drain, and between the P+ anode region 21 and the N base region 23, the P+ anode region is 21 to N base territory 1a
An N+ buffer layer 22 is formed to suppress the efficiency of ball injection into the ball 23.

On the surface side of the N base region 23, DSA (DHfusi
On 3clr AIignment) technology, the base resistance Rt of the bipolar transistor described later
P+ body area 24, P body @ area 25 to lower
and N+ source regions 26 are formed, respectively.

Further, on the P body region 25 between the N'' source region 26 and the N base region 23, a gate electrode 29 for inducing a channel 27 in the P body region 25 is provided with a gate oxide film 28 interposed therebetween.

31 is a source electrode, and the source electrode 31 is connected to the P body region 25 via the N'' source region 26 and the P+ body region [24]. 32 is an anode electrode.

As described above, the conductivity modulated vertical MO8FET can be considered to have a structure in which a P'' anode region 21 is added to the region corresponding to the drain of a normal vertical MO3FET.

Then, a required value of positive voltage is applied to the anode electrode 32,
When a gate voltage equal to or higher than the threshold voltage is applied to the gate electrode 29, a channel 27 is induced directly under the gate electrode 29, the surface layer of the P body region 25 becomes conductive, and the N+ and -S regions V
Electron current flows into the N base region 23 from A26 through the channel 27. On the other hand, a large number of holes (minority carriers) are transferred from the P" anode region 21 to the N base region 23.
is injected. At this time, the N+ buffer layer 22 acts to suppress the injection efficiency.

The balls implanted in the N base region 23 are connected to the channel 27
A part of it flows into the P body region 1ff125 while recombining with the electrons that have flowed in from the source electrode 31. However, a large amount of carrier accumulation still occurs in the N base region Li 123, causing conductivity modulation and reducing the on-resistance during operation.

In this way, the conductivity modulated vertical MO8FET has the characteristics of extremely low on-resistance during operation and high breakdown voltage.

However, the conductivity modulation type vertical MO8FET has the P+ anode region 21 as described above, the N+ buffer layer 22 and the N base region 23 exist on the P+ anode region M21, and the N base region 23 has a P+ body. Region 24, P body region 25 and N+ source region 26 are formed.

Because of this structure, as shown in the equivalent circuit of FIG.
An N-type transistor Q2 is generated miraculously, and the combination of these two transistors Gh and Q2 forms a PNPN thyristor. In FIG. 6, Rb is the base resistance of the NPN type transistor Q2, and is from the P body region 25 to the N+
This occurs over a portion of the P+ body region 24 directly below the source region 26.

Therefore, P1 corresponding to the emitter of transistor Q1
Among the holes injected from the anode region 21, the P body region 25 corresponding to the collector remains unrecombined.
Assuming that the current reaching the current is rb, a voltage drop of Ib-Rb occurs at the base resistor Rb, and when this voltage drop exceeds the base threshold voltage (ko, 6V) of the transistor Q2, the transistor Q2 turns on. This causes an increase in its collector current, that is, the base current of the other transistor Q1. As a result, a positive feedback loop is created in which the collector current Ib of the transistor Q+ increases and the base current of the transistor Q2 increases, resulting in a latch-up phenomenon. When a latch-up phenomenon occurs, thyristor operation occurs and the original state cannot be restored unless the power is turned off.

Therefore, in order to prevent the latch-up phenomenon from occurring, it is important to make the base resistors R, b and the current 1b flowing therein as small as possible.

For this reason, in the conventional conductivity modulation type vertical MO3FET, a P+ body region 24 is provided, and an N+ buffer layer 22 is provided in contact with the P+ anode region 21 to reduce the hole injection efficiency, and furthermore, the ALJ A lifetime killer has been introduced into the N base region 23 by diffusion or electron beam irradiation to reduce the current amplification factors of the parasitic transistors Q+ and Q2.

Each of the above means can be used alone, but
Each of the above-mentioned means is often used in combination, as each means will cause different problems if used alone.

On the other hand, FIG. 7 shows an equivalent circuit of a normal vertical MO8FET that does not have a P+7 node region.

In the case of a normal vertical MO8FET, a thyristor is not formed, but N between the source and drain of the vertical MO8FET is
A PN type transistor Q3 is parasitic. The base resistor Rb is located between the base and emitter of this transistor Q3.

Therefore, even in a normal vertical MO8FET, in a region where the drain voltage is high, the transistor Q3 turns on and the thickness of the safe operating region is limited due to secondary breakdown. In order to improve this, it is effective to reduce the base resistance Rb, and for this reason, even in the normal vertical MO8FET, a P+ body region is provided as in the case of the conductivity modulation vertical MO8FET. .

(Problems to be solved by the invention) In the conventional conductivity modulation type vertical MO8FFT, P
Even if the +body region 24 is provided, since the N+ resource region 26 extends over this P1 body region 24, the N+
It is difficult to reduce the pinch resistance that occurs directly below the source region 26, and therefore it is difficult to sufficiently reduce the base resistance Rb of the parasitic bipolar transistor.

In order to make the base resistance Rb sufficiently small, P+ body region 2
If the diffusion of No. 4 is made deeper, the lateral diffusion becomes correspondingly larger, increasing the device area and causing an increase in on-resistance. In addition, if the N+ buffer layer 22 is EH-pulled so as to be in contact with the P+ anode region 21 to reduce the efficiency of hole injection into the N base region 23 which is the electric power modulation region, the on-resistance during operation can be made sufficiently low. However, if a lifetime killer is introduced into the N base region 23 by ALJ diffusion or electron beam irradiation, the on-resistance increases and the lifetime killer becomes Since it is distributed throughout the board,
This has a problem in that it affects the original operation of the MO8FET, tends to cause variations in the gate voltage, and lowers the manufacturing yield.

Ordinary vertical MO8FE without P+ anode area
Even in T, it is difficult to reduce the pinch resistance that occurs directly under the N+ source region by simply forming a P+ body region, and therefore it is difficult to sufficiently reduce the base resistance of the parasitic bipolar transistor. There were some problems similar to those mentioned above.

The present invention was made by focusing on such conventional problems, and it is a conductive material that can accurately suppress the operation of parasitic bipolar transistors, improve secondary breakdown strength, and improve manufacturing yield. The present invention aims to provide a degree modulation type MO8FET.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention includes a base region of a first conductivity type that substantially acts as a drain, and a base region formed on the surface side of the base region. a body region of a second conductivity type,
A source region of a first conductivity type formed on the surface side of the body region, and a channel formed on the body region via a gate insulating film on the body region between the source region and the base region. The gist of the present invention is to include a gate electrode that induces , and a source electrode connected to the body region and the source region via a silicide layer formed in the body region and serving as a conductor.

(Operation) A low-resistance silicide layer serving as a conductor is formed in the body region of the second conductivity type in which the source region is formed, and the source electrode is connected to the source region via this silicide layer. Therefore, there is no need to provide a contact region with the source MV7A in the source region, and it is sufficient to form the source region narrow enough to reach the region in contact with the channel. As a result, the pinch resistance generated in the body region immediately below the source region becomes negligible, and the base resistance of the parasitic transistor is extremely reduced.

Therefore, even if the output current value exceeds a certain level, the on-operation of the parasitic transistor is suppressed, and the withstand capability against secondary breakdown based on the on-operation of the parasitic transistor is improved.

<Example) Embodiments of the present invention will be described below based on the drawings.

FIG. 1 and FIG. 2 are diagrams showing one embodiment of the present invention. This example is a conductivity modulated vertical MO8FET.
It was used repeatedly.

First, to explain the configuration, in FIG. 1, 1 is a P+ anode region which serves as a hole injection source, and conductivity is modulated by hole (minority carrier) injection from the P1 anode region 1 into the P1 anode region 1-H. At the same time, an N base region 2 is formed which essentially acts as a drain.

Note that when the N type is made the first s conductivity type, the P type, which is the opposite conductivity type, becomes the second conductivity type.

A P body region 3 is formed on the surface side of the N base 2,
An N+ source region 4 is formed within this P body region 3. The N+ source region 4 is formed to have a relatively shallow diffusion depth by using arsenic As having a diffusion rate of π as a diffusion impurity, and its width L1 is approximately 1 μm or less using the sidewall technique described later. The width of the source region is extremely narrow compared to the width L2 of the source region in the conventional example shown in FIG. In the P body region 3-[between the N+ source region 4 and the N base region 2, the P body region tji! A gate electrode 7 for inducing a channel 5 in the gate electrode 3 is provided via a gate oxide III (insulating film) 6.

Further, a silicide layer 8 that becomes a part of the electrode conductor is formed on the surface of the P body region 3.

The silicide layer 8 is made of w, pt or Mo as described later.
'J high melting point metal is used to form an intermetallic compound with the silicon in the P body region 3, and compared to a normal P+ or N+ diffusion layer, it is about an order of magnitude higher. It has low resistivity. The thickness of the silicide layer 8 is equal to or greater than the diffusion depth of the N+ source region 4, and the end portion is in ohmic contact with the N+ source region 4.

Furthermore, the silicide layer 8 is connected to the P+ body region 9 via the P+ body region 9
It is in ohmic contact with the body region 3. P+ body region 9 is provided to reduce the contact resistance between silicide layer 8 and P body region 3, and is doped with a high concentration of P type impurity and formed thin.

11 is an interlayer insulating film formed by depositing PSG; 12
is a source electrode formed of a /l film, and source electrode 1
2 is connected to source region 4 and P body region 3 via silicide layer 8 .

13 is an anode electrode.

Next, an example of the manufacturing process will be explained using <8) to (Q) in FIG. 2, and the structure will be further detailed. In the following description, the item symbols (a) to (Q) correspond to (a) to (q) in FIG. 2, respectively.

(a) On a P-type silicon wafer, which will become the P+ anode region Vi1, an N base region 2 is formed by an epitaxial method with an impurity concentration of 1X101'cm-3 and a thickness of 50 to 10 cm.
It is grown to a thickness of approximately 0 μm. This N base territory [
A gate oxide film 6 is formed on the surface of 2 by thermal oxidation to a thickness of approximately 1000 mm.
Formed to a thickness of angstroms.

Polycrystalline silicon is deposited on gate oxide film 6 to a thickness of about 5000 angstroms, and unnecessary portions are removed by photoetching to form gate electrode 7. Next, using this gate ff1Vi7 as a mask, the N base f
Boron B+ is ion-implanted into r4hi2 at a concentration of about 3 to 5XIOI3cm-2.

(b) Heat treatment is performed once at 1200° C. for about 3 hours to diffuse boron B+ and form P body region 3. Next, a required portion of the surface of the P body region 3 is masked with a resist 14, and arsenic As+ is applied at approximately 1× to the portion where the N+ source region 4 is to be formed.
Ions are implanted to a concentration of 10'5 cm-2. As an impurity for forming the N+ source region 4, arsenic As+ has a slow diffusion rate.
The reason for using this is to form the N+ source region 4 with a shallow diffusion depth.

(C) The surface of the polycrystalline silicon forming the gate electrode 7 is thermally oxidized to form oxide 115 (Si02) 15 to a thickness of about 3000 angstroms.

(d) By an anisotropic etching method using reactive ion etching, the portion where the silicide layer is to be formed and the oxide film 15 on the gate electrode 7 are etched, and a side wall 15a of SiO2 is formed on the side of the gate electrode +1i7.
form.

(e) A high melting point metal 16 such as W, PT, or Mo for forming a silicide layer is milled to a required thickness, and boron B+ for forming a P+ body region is ion-implanted thereon.

(f) A heat treatment is performed to form a silicide layer 8 on the surface of the P body region 3 and to form a shallow P+ body region 9 on the bottom surface of the silicate layer 8. At this time, the entire surface of the silicon on which the refractory metal 16 is deposited is silicided to form the silicide layer 8, so the width L+ of the N+ source region 4 is determined in a self-aligned manner by the sidewall 15a, and is, for example, 1 μm. It is formed to have an extremely narrow width of about the following. Further, the surface portion of the gate electrode 7 is also silicidized at the same time to form a gate silicide 7a.

(o) The interlayer insulating film 11 made of PSG has a thickness sufficient to insulate the gate electrode 7 and the source electrode 12, for example.
After depositing on the order of μm and opening a contact hole,
An AM film is deposited to a thickness of about 3 μm and patterned to form a wiring layer including the source electrode 12.

Next, the action will be explained.

The N+ source region 4 is formed to be relatively shallow, and its width L1 is formed to be extremely narrow, 1 μm or less, and exists only in a part of the region in contact with the channel 5. Therefore, the pinch resistance generated in the E) body region 3 directly below the N+ source region 4 becomes negligibly small. Also, compared to the conventional example shown in FIG. 5, the N+
A portion of the source region is replaced by a low resistance silicide layer 8, and the extremely narrow N+ source region 4 described above is formed at the end of the silicide layer 8.

Therefore, the base resistance Rb of the parasitic transistor Q2 shown in FIG. 6 is extremely reduced.

Then, a required positive voltage is applied to the drain electrode 13,
When a gate voltage equal to or higher than the threshold voltage is applied to the gate electrode 7, the surface layer of the P body region 3 directly under the gate electrode 7 is inverted to form a channel 5, and the N" source region 4 and the N base region acting as a drain are formed. 2 are electrically connected.

On the other hand, a large amount of holes (minority carriers) are injected from the P+ anode region 1 to the N base region 3.

The injected holes recombine with the electrons that flowed in from channel 5, and some of them are transferred to P body region 1!3 and channel 5.
and flows out from the source electrode 12.

At this point, conductivity modulation occurs due to a large amount of minority carriers still accumulated in the N base region 2, and the on-resistance decreases, resulting in a large current output characteristic.

Even if this peak current value exceeds a certain level, as described above, the base resistance Rb1f of the parasitic transistor Q2
The parasitic transistor Q2 is made small because it is ih
The rise in the base potential of is suppressed.

Therefore, the ON operation of the anomalous transistor Q2 and the thyristor operation are prevented, and the resistance to latch-up is significantly improved while maintaining a low on-resistance.

Next, FIGS. 3 and 4 show other embodiments of the present invention.

In this embodiment, the region where the silicide layer is formed is made into a concave region, and the formation of the N+ source region around the bottom surface of the silicide layer is almost completely prevented, thereby further reducing the base resistance Rb of the parasitic transistor Q2. be.

As shown in FIG. 3, the silicide layer 18 is in the recessed region.
It is formed deeper than the diffusion depth of the N+ source region 4.

An example of the manufacturing process will be described with reference to FIG. 4. The manufacturing steps of the embodiment, steps (a) to (d) in FIG. 2, are the same as those described above. Therefore, only the subsequent steps will be explained using FIGS. 4(e) to 4(h).

(e) Using the sidewall 15a as a mask, the surface of the P body region 3 where the silicide layer will be formed is etched by reactive ion etching along with the excess portion of the N'' diffusion layer forming the N+ source region 4. A deep concave region 17 is formed.

(f) A high melting point metal 16 for forming a silicide layer is deposited to a required thickness, and boron B+ for forming a P+ body region is ion-implanted thereon.

A (Cl) heat treatment is performed to form a silicide layer 18 in the recessed region 17, and a P+ body region 9 is formed on the lower surface thereof.

(h) After depositing a living room insulating film 11 made of PSG and opening a contact hole, an Al film is deposited and patterned to form a wiring layer including the source electrode 12.

The vertical MO8F E of this example formed as described above
T is compared with that shown in FIG. 1, which is an example, as follows.
The low-resistance silicide IFi 18, which becomes part of the electrode conductor, is formed deeper within the P body region 3, and the formation of the N1 source region 4 around the lower surface of this silicide layer 18 is almost completely prevented. , parasitic transistor Q2
The base resistance Rb of the transistor is further reduced, and the resistance against latch-up is further improved.

In addition, although each of the above-mentioned embodiments describes the case where this invention is applied to a conductivity modulation type vertical MO8FET, this invention can also be applied to a vertical type MO8FET other than a lightning conductivity modulation type that does not have a P1 anode region. . Vertical M like this
In the O8FET, a parasitic transistor occurs between the source and drain as shown in Figure 7, but in the case of the device to which this invention is applied, the base resistance of the parasitic transistor is reduced, the on-operation is suppressed, and the secondary The breakdown tolerance is increased and the safe operating area of the device is expanded.

[Effects of the Invention] As explained above, according to the present invention, a low-resistance silicide layer serving as a conductor is formed in the body region of the second conductivity type in which the source region is formed, and the source electrode is made of this silicide layer. Since the source region is connected to the source region through the layer, there is no need to provide a contact region with the source electrode in the source region, and the region in contact with the channel can be formed with an extremely narrow width. Therefore, the pinch resistance generated in the body region immediately below the source region becomes negligibly small, and the base resistance of the parasitic transistor is extremely reduced.

As a result, even if the output current exceeds a certain level, the on-operation of the parasitic transistor is suppressed, and the resistance to secondary breakdown due to the on-operation of the parasitic transistor is significantly improved, and the safe operating area of the device is expanded. It has the advantage of being expanded.

Furthermore, in conductivity modulated vertical MO3FETs, there is no need to provide an N+ buffer layer to reduce hole injection efficiency, and there is no need to introduce a lifetime killer into the substrate, so the manufacturing process can be simplified. There is an advantage that the amount is reduced and the yield is improved.

[Brief explanation of the drawing]

FIG. 1 is a vertical cross-sectional view showing one embodiment of a linear MO8FET according to the present invention, FIG. 2 is a process diagram showing an example of the manufacturing process of the same embodiment, and FIG. 3 is a diagram showing another embodiment of the invention. 4 is a process diagram showing an example of the manufacturing process of another embodiment of the same as above, FIG. 5 is a longitudinal sectional view of a conventional vertical MO8FET, and FIG. FIG. 7 is a circuit diagram showing an equivalent circuit including a parasitic transistor in another conventional example. 2: N base region, 3: P body region, 4: N+ source region, 5: channel, 6: gate oxide film (insulating film), 7: gate electrode, 8.18: silicide layer, 9: P′″ body Area, 12: Source electrode, 13 Near-node electrode. Agent Patent Attorney Yasuo Miyoshi 1J 7Jg1 Figure 2 (a) Figure 2 (e) 11° Figure 2 (d) j Figure 3 H ÷ 3 ] Figure 5 Figure 6

Claims (1)

[Scope of Claims] A base region of a first conductivity type that substantially acts as a drain, a body region of a second conductivity type formed on the surface side of the base region, and a body region of the second conductivity type formed on the surface side of the body region. a source region of a first conductivity type; a gate electrode provided on the body region between the source region and the base region via a gate insulating film to induce a channel in the body region; A vertical MOSFET characterized by having a source electrode connected to the body region and the source region through a silicide layer formed as a conductor.