JPS62283669A - Conductivity modulation type mosfet - Google Patents
Conductivity modulation type mosfetInfo
- Publication number
- JPS62283669A JPS62283669A JP12761486A JP12761486A JPS62283669A JP S62283669 A JPS62283669 A JP S62283669A JP 12761486 A JP12761486 A JP 12761486A JP 12761486 A JP12761486 A JP 12761486A JP S62283669 A JPS62283669 A JP S62283669A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- type
- gate electrode
- source
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000012535 impurity Substances 0.000 claims abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 4
- 238000013461 design Methods 0.000 abstract description 3
- 238000009792 diffusion process Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 239000000758 substrate Substances 0.000 description 5
- 230000001066 destructive effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
Abstract
Description
【発明の詳細な説明】 ［発明の目的コ （産業上の利用分野） 本発明は、導電変調型Ｍ ＯＳ Ｆ Ｅ Ｔに関する。[Detailed description of the invention] [Purpose of the invention] (Industrial application field) The present invention relates to a conductivity modulated MOS FET.
（従来の技術）
近年、電力用スイッチング素子として、Ｄ Ｓ Ａ （
Ｄ １ｆｆｕｓｉｏｎ Ｓ ｅｌｆ Ａ ｌｉｎｇ
ｎ ）法によりソースおよびチャネル領域を形成するパ
ワーＭＯ８ＦＥＴが市場に現れている。しかしこの素子
は１０００Ｖ以上の高耐圧ではオン抵抗が高くなってし
まい、大電流を流すことが難しい。これに代わる有力な
素子として、ドレイン領域にソースとは逆の導電型層を
設けることにより、高抵抗層に導電変調を起こさせてオ
ン抵抗を下げるようにした、いわゆる導電変調型ＭＯ８
ＦＥＴが知られている。導電変調型Ｍ ＯＳ Ｆ Ｅ、
Ｔは一般に次のように形成される。ドレイン層となる
ｐ”Ｓｉ基板にｎ１型バッファ層を介してｎ−型高抵抗
層が形成される。この高抵抗層上にゲート絶縁膜を介し
てストライブ状の開口を有するゲート電極が形成され、
このゲート電極をマスクとして不純物の二重拡散を行う
ことにより、ｐ型代−ス層とその端部に自己整合された
ｎ型ソース層が形成される。(Prior art) In recent years, DSA (
D 1ffusion S elf A ring
Power MO8FETs whose source and channel regions are formed by the n) method have appeared on the market. However, this element has a high on-resistance at a high breakdown voltage of 1000V or more, making it difficult to flow a large current. A promising alternative element is the so-called conductivity modulation type MO8, which lowers the on-resistance by causing conductivity modulation in the high-resistance layer by providing a layer of conductivity type opposite to that of the source in the drain region.
FET is known. conductivity modulation type MOS F E,
T is generally formed as follows. An n-type high-resistance layer is formed on a p'' Si substrate that will serve as a drain layer via an n1-type buffer layer.A gate electrode having a striped opening is formed on this high-resistance layer via a gate insulating film. is,
By performing double diffusion of impurities using this gate electrode as a mask, a p-type source layer and a self-aligned n-type source layer are formed at the ends thereof.
これにより、ゲート電極下のｎ型ソース層とｎ−型高抵
抗層で挟まれたｐ型ベース層表面にチャネル領域が形成
される。ソース層とベース層には双方にコンタクトする
ソース電極が形成され、ドレイン層にはドレイン電極が
形成される。As a result, a channel region is formed on the surface of the p-type base layer sandwiched between the n-type source layer and the n-type high-resistance layer under the gate electrode. A source electrode is formed in contact with both the source layer and the base layer, and a drain electrode is formed in the drain layer.
この導電変調型ＭＯ３ＦＥＴでは、ゲートＮ極に正電圧
を印加してターンオンする際、ｎ“型ソース層からチャ
ネル領域を通ってｎ−型高抵抗層に注入される電子電流
に対して、ｐ１型ドレイン層から正孔注入が起り、この
結果ｎ−型高抵抗層には多義のキャリア蓄積による導電
変調が起こる。In this conductivity modulation type MO3FET, when turning on by applying a positive voltage to the gate N pole, the p1 type Hole injection occurs from the drain layer, and as a result, conductivity modulation occurs in the n-type high resistance layer due to ambiguous carrier accumulation.
ｎ−型高抵ｉｓに注入された正孔電流は、ｎ＋梨型ソ一
層下のｐ型代−ス層を通り、ソース電極にぬける。ソー
ス電極はｎ＋型ソース層とｐ型代−ス層を短絡している
ため、サイリスタ動作は阻止される。ゲート・ソース１
ｉ１ｉ１圧を零とすれば、素子はターンオフする。The hole current injected into the n-type high-resistance layer passes through the p-type substitute layer below the n+ pear-shaped layer to the source electrode. Since the source electrode short-circuits the n+ type source layer and the p type substitute layer, thyristor operation is prevented. gate source 1
When the i1i1 pressure is reduced to zero, the element is turned off.
この導電変調型ＭＯ８ＦＥＴは、高耐圧化した場合にも
、従来のパワーＭＯ８ＦＥＴに比べて導電変調の結果と
して十分に低いオン電圧が得られる。This conductive modulation type MO8FET can obtain a sufficiently lower on-voltage as a result of conductive modulation than a conventional power MO8FET even when the withstand voltage is increased.
しかしながらこの導電変調型ＭＯ８ＦＥＴにも未だ問題
がある。第１に、素子を流れる電流の密度が大きくなる
と、ソース層下の横方向抵抗による電圧降下が大きくな
る。そしてｐ型代−ス層とｎ＋型ソース層間が順バイア
スされるようになるとサイリスタ動作に入り、ゲート・
ソース間バイアスを零にしても素子がオフしない、いわ
ゆるラッチアップ現象が生じる。この問題を解決する方
法として従来、ｐ型代−ス層を深く拡散する方法、ｐ型
ベース層内に重ねて深くρ型層を拡散する方法等が採用
されている。しかしこれらの方法では、オン電圧の上昇
を沼く。第５図はその様子を示すもので、ｐ型代−ス層
の拡散深さＸｐとオン電圧ＶＦおよびラッチアップ電流
ＩＬの関係を示す。However, this conductivity modulation type MO8FET still has problems. First, as the density of current flowing through the device increases, the voltage drop due to the lateral resistance under the source layer increases. When forward bias is applied between the p-type source layer and the n+-type source layer, thyristor operation begins, and the gate
A so-called latch-up phenomenon occurs in which the device does not turn off even if the source-to-source bias is reduced to zero. Conventionally, methods for solving this problem include a method of deeply diffusing a p-type substituent layer, a method of deeply diffusing a ρ-type layer superimposed on the p-type base layer, and the like. However, these methods result in an increase in on-voltage. FIG. 5 shows this situation, and shows the relationship between the diffusion depth Xp of the p-type substitute layer, the on-voltage VF, and the latch-up current IL.
図示のようにｐ型代−ス層の拡散深ざＸｐを大きくする
くこれは、チャネル長を大きくすることに対応する〉と
、ラッチアップ電流は増大するが、オン電圧も上昇して
しまう。第２に、従来の導電変調型ＭＯ８ＦＥＴでは負
荷短絡耐量がまだ不十分である。導電変調型ＭＯ８ＦＥ
Ｔをインバータ￥装置等に用いて負荷が短絡した場合、
ドレイン・ソース間にはＥｌ電圧電圧がそのままかかり
過大な電流が流れるために、この状態が続くと導電変調
型ＭＯ３ＦＥＴは破壊される。これを防止するためには
保護回路が用いられるが、負荷短絡が発生してから保護
回路が作動するまでの概略１０μｓｅｃの時間破壊しな
い耐量を有することが要求される。これが負荷短絡耐ｉ
である。素子の順方向阻止電圧が高くなると取扱い電圧
も高くなり、負荷短絡耐量も大きくしなければならない
。If the diffusion depth Xp of the p-type substitute layer is increased as shown in the figure, which corresponds to an increase in the channel length, the latch-up current will increase, but the on-voltage will also increase. Second, the load short-circuit withstand capability of the conventional conduction modulation type MO8FET is still insufficient. Conductivity modulation type MO8FE
If the load is short-circuited when T is used in an inverter, etc.,
Since the El voltage is directly applied between the drain and source and an excessive current flows, if this state continues, the conductivity modulation type MO3FET will be destroyed. In order to prevent this, a protection circuit is used, but it is required that the protection circuit has the ability to withstand breakdown for approximately 10 μsec from the occurrence of a load short circuit to the activation of the protection circuit. This is the load short circuit resistance i
It is. As the forward blocking voltage of the element increases, the handling voltage also increases, and the load short-circuit withstand capability must also be increased.
（発明が解決しようとする問題点）
以上のように従来の導電変調型ＭＯ８ＦＥＴは、オン電
圧を上昇させることなくラッチアップ電流の大幅な増大
を図ることが難しく、負荷短絡耐量が不十分である、と
いう問題があった。(Problems to be Solved by the Invention) As described above, it is difficult to significantly increase the latch-up current without increasing the on-voltage in the conventional conduction modulation type MO8FET, and the load short circuit resistance is insufficient. There was a problem.
本発明はこの様な問題を解決した導電変調型ＭＯ８ＦＥ
Ｔを提供することを目的とする。The present invention is a conductive modulation type MO8FE that solves these problems.
The purpose is to provide T.
［発明の構成］
（問題点を解決するための手段）
本発明にかかる導電度ｒＡ型ＭＯ８ＦＥＴは、第１導電
型ドレイン層上に第２導電型の低抵抗バッファ層を介し
て第２導電型の高抵抗層を有し、この高抵抗層上にゲー
ト絶縁膜を介して格子状のゲート電極が配設され、この
ゲート電極の開口部からの不純物拡散により第１′ｓ電
型ベース層およびこのベース層内に位置する第２導電型
ソース層が形成され、ドレイン層にコンタクトするトレ
イン電極、およびソース層とベース層に同時にコンタク
トするソース電極を有する。この様な導電変調型ＭＯ８
Ｆ Ｅ Ｔにおいて、本発明は、ゲート電極直下のソー
ス層と高抵抗Ｗ！１間に挟まれるベース層表面に形成さ
れるチャネル領域のチャネル長をｌ、ゲート電極の幅を
ＬＧ、ベース層とドレイン層に挟まれる高抵抗層の幅を
Ｗｎとしたとき、２≧５．５μｍ
しｑ≧３０μｍ
ｗｎ≧１２０μ而
なる条件を満たすようにしたことを特徴とする。[Structure of the Invention] (Means for Solving Problems) The conductivity rA type MO8FET according to the present invention has a second conductivity type drain layer formed on a first conductivity type drain layer via a second conductivity type low resistance buffer layer. A lattice-shaped gate electrode is disposed on this high-resistance layer via a gate insulating film, and impurity diffusion from the opening of this gate electrode forms a first base layer and A second conductivity type source layer located within the base layer is formed and has a train electrode in contact with the drain layer and a source electrode in simultaneous contact with the source layer and the base layer. Such conductivity modulation type MO8
In FET, the present invention has a source layer directly under the gate electrode and a high resistance W! 1, the width of the gate electrode is LG, and the width of the high resistance layer sandwiched between the base layer and the drain layer is Wn, and 2≧5. It is characterized by satisfying the following conditions: 5 μm, q≧30 μm, and wn≧120 μm.
（作用）
上述のような設計パラメータを限定することにより、後
に具体的なデータを挙げて説明するように導電変調型Ｍ
Ｏ８ＦＥＴの特性の大幅な改善が図られる。即ち、チャ
ネル長２およびゲート電極幅ＬＧを大きくすることによ
り、オン電圧を上昇させることなくラッチアップ電流の
増大を図る。(Function) By limiting the design parameters as described above, conductive modulation type M
The characteristics of O8FET are significantly improved. That is, by increasing the channel length 2 and the gate electrode width LG, the latch-up current is increased without increasing the on-voltage.
ことができ、また高抵抗層幅Ｗｎを大きく設定すること
により負荷短絡耐量の改善を因ることができる。In addition, by setting the high resistance layer width Wn large, the load short-circuit withstand capability can be improved.
（実施例） 以下、本発明の詳細な説明する。(Example) The present invention will be explained in detail below.
第１図（ａ）（ｂ）は−実施例の導電変調型ＭＯ８ＦＥ
Ｔを示す平面図とそのＡ−Ａ’断面図である。１１はｐ
＋型トド１４２層１１あり、この上にｎ＋型バッファ層
１２を介してｎ−型高抵抗１１３が形成されている。こ
の高抵抗１１１３上にゲート絶縁膜１４を介して例えば
多結晶シリコン膜によりゲート電極１５が形成されてい
る。ゲート絶縁膜１５は第１図（ａ）に斜線を施して示
したように、ストライプ状の間隙（開口部）１６を有す
る格子状に配設形成される。このゲート電極１５をマス
クとしてＤＳＡ法による不純物拡散を行うことにより、
ｐ型ベース層１７およびｎ＋＋ソース層１８が形成され
ている。これにより、ｐ型ベース層の端部、即ちソース
層１８と＾抵抗層１３に挟まれた領域のｐ型ベース１１
１７表面にチャネルａ域１９が形成される。２０はソー
ス層１８とベース層１７に同時にコンタクトするソース
電橋であり、２１はドレイン１慟である。ｐ型ベース層
１７の中央部には、その横方向抵抗を小さくするために
ｐ＋型！１２２が拡散形成されている。Figures 1(a) and 1(b) show - Example conductivity modulation type MO8FE
It is a top view which shows T, and its AA' sectional view. 11 is p
There is a + type layer 142 layer 11, on which an n- type high resistance layer 113 is formed with an n + type buffer layer 12 interposed therebetween. A gate electrode 15 made of, for example, a polycrystalline silicon film is formed on this high resistance 1113 with a gate insulating film 14 in between. The gate insulating film 15 is arranged in a lattice shape having stripe-shaped gaps (openings) 16, as shown by hatching in FIG. 1(a). By performing impurity diffusion using the DSA method using this gate electrode 15 as a mask,
A p-type base layer 17 and an n++ source layer 18 are formed. As a result, the p-type base 11 at the end of the p-type base layer, that is, the region sandwiched between the source layer 18 and the resistance layer 13
A channel a region 19 is formed on the surface of 17. 20 is a source bridge that contacts the source layer 18 and the base layer 17 at the same time, and 21 is a drain bridge. In the center of the p-type base layer 17, a p+ type! 122 is formed by diffusion.
この様な構成においてこの実施例では４、チャネル長ρ
を５．５μｍ以上、ゲート電極幅Ｌａを３０μ扉以上に
設定し、またｐ型ベース層１７とドレイン層１１の間（
より正確には、ｐ＋＋層２２とｎ＋＋バッフ？層１２の
間）の高抵抗層１３の幅Ｗｎを１２０μｍ以上に設定す
る。In this embodiment, in such a configuration, the channel length ρ is 4.
is set to 5.5 μm or more, the gate electrode width La is set to 30 μm or more, and between the p-type base layer 17 and the drain layer 11 (
More precisely, the p++ layer 22 and the n++ buffer? The width Wn of the high resistance layer 13 (between the layers 12) is set to 120 μm or more.
この素子の具体的な製造工Ｐｉ！例を説明すると、次の
通りである。先ず０．００１〜０．００４Ω・口のｐ＋
型Ｓ１塁板と、１００〜１５０Ω・ｃｒｔｔのｎ−型５
ｉ基板を用意する。ｎ−型Ｓ１基板の一方の鏡面研磨面
にドーズ量０．５〜１×１ｏｌＳ／ｃ！Ａ２のリン・イ
オン注入を行い熱処理する。次にｐ４″型Ｓｉ基板の鏡
面研磨面とｎ−型ＳｉＷ板のリン・イオン注入面を、直
接接着技術により接合させる。これにより、ｐ型ドレイ
ンＷＡ１ ｉ−ｎ′″型バッフ７１１２−ｎ−型高抵抗
層１３のウェーハが得られる。ここでｎ°型Ｓｉ基板の
厚さは、最終的に高抵抗層１３の幅Ｗｎが１２Ｃ１７Ｆ
Ｌ以上となるように予め調整しておく。この後ｎ−型高
抵抗１１１３表面にゲート絶縁１１４として１０００人
の熱酸化膜を形成し、この上に５０００人の多結晶シリ
コン膜を堆積する。そしてこの多結晶シリコン膜を、周
期的な開口部１６を有するようにエツチング加工してゲ
ート電極１５とする。ゲート電極１５の４！ｌＬ ａは
３０μｍ以上とする。次にこのゲート電極１４をマスク
としてボロンを７μｍ以上拡散形成してｐ型ベース層１
７を形成する。更にゲート電極１５をマスクの一部とし
て用いて、ヒ素をドーズ量５ Ｘ １０” ／ａｒｔ２
イオン注入して熱処理し、ソース層１８を形成する。こ
れによりチャネル領域１９が形成され、チャネル長λは
５．５μｍ以上になる。この後全面をＣＶＯｍ化膜で覆
い、これにコンタクト孔を開けてソース電１！！２０を
形成する。基板裏面には、Ｖ−Ｎｉ−Ａｕｌｌの蒸着に
よりドレイン電極２１を形成する。The specific manufacturer of this element Pi! An example is as follows. First, 0.001-0.004Ω・mouth p+
Type S1 base plate and n-type 5 of 100-150Ω・crtt
Prepare the i-board. A dose of 0.5 to 1×1 olS/c was applied to one mirror-polished surface of the n-type S1 substrate! A2 phosphorus ion implantation is performed and heat treatment is performed. Next, the mirror-polished surface of the p4'' type Si substrate and the phosphorus ion-implanted surface of the n-type SiW plate are bonded together by direct bonding technology. A wafer with molded high resistance layer 13 is obtained. Here, the thickness of the n° type Si substrate is such that the final width Wn of the high resistance layer 13 is 12C17F.
Adjust in advance so that it is equal to or larger than L. Thereafter, a 1,000-layer thermal oxide film is formed as a gate insulator 114 on the surface of the n-type high-resistance layer 1113, and a 5,000-layer polycrystalline silicon film is deposited thereon. This polycrystalline silicon film is then etched to form a gate electrode 15 so as to have periodic openings 16. Gate electrode 15 no 4! lLa is 30 μm or more. Next, using this gate electrode 14 as a mask, boron is diffused to a thickness of 7 μm or more to form a p-type base layer 1.
form 7. Furthermore, using the gate electrode 15 as part of a mask, arsenic is applied at a dose of 5×10”/art2.
A source layer 18 is formed by ion implantation and heat treatment. As a result, a channel region 19 is formed, and the channel length λ becomes 5.5 μm or more. After that, the entire surface is covered with a CVOm film, a contact hole is opened in this, and the source voltage 1! ! Form 20. A drain electrode 21 is formed on the back surface of the substrate by vapor deposition of V-Ni-Aull.
以上のようにして、チャネル長Ｃ≧５．５μｍ１ゲート
電極幅Ｌｏ≧３０ｔ、ｔｍ、高抵抗層幅ｗｎ≧１２０μ
ｍの導電変調型ＭＯ８ＦＥＴが得られる。As described above, channel length C≧5.5 μm, gate electrode width Lo≧30t, tm, high resistance layer width wn≧120 μm.
m conduction modulation type MO8FET is obtained.
以上のような構造パラメータの設定により優れた素子特
性が得れる理由を、具体的な実験データに基づいて次に
説明する。前述したようにラッチアップ電流の増大を図
るために単にチャネル長λを大きくするだけでは、オン
電圧が急激に増大する。The reason why excellent device characteristics can be obtained by setting the structural parameters as described above will be explained below based on specific experimental data. As described above, if the channel length λ is simply increased in order to increase the latch-up current, the on-state voltage will increase rapidly.
第２図は、ゲート電極幅しＧとオン電圧ＶＦの関係を、
チャネル長２をパラメータとして測定した結果である。Figure 2 shows the relationship between the gate electrode width G and the on-voltage VF.
This is the result of measurement using channel length 2 as a parameter.
チャネル長２が３．２μｍでは、ゲート電極幅し０の変
化に対してオン電圧ＶＦの変化は余り認められない。こ
れに対して、チャネル長２が５．５μｎではオン電圧Ｖ
Ｆはゲート電極１１Ｌｏに大きく依存し、Ｌａが３０μ
ｍ以上になるとチャネル長ｆｆ１−３．２μ乳の場合と
殆ど変わらないオン電圧ＶＦが得られることが分る。When the channel length 2 is 3.2 μm, there is not much change in the on-voltage VF with respect to a change in the gate electrode width. On the other hand, when the channel length 2 is 5.5 μn, the on-voltage V
F largely depends on the gate electrode 11Lo, and La is 30μ
It can be seen that when the channel length is ff1-3.2μ, an on-voltage VF that is almost the same as in the case of the channel length ff1-3.2μ can be obtained.
またゲート電極幅Ｌｏを大きくすると一般には単位面積
当たりのベース層に流入する電流が増大して、ラッチア
ップ電流が低下すると考えられる。Furthermore, it is considered that when the gate electrode width Lo is increased, the current flowing into the base layer per unit area generally increases and the latch-up current decreases.
しかしチャネル艮２をある値以上にするとこれを防止で
きることが実験的に明らかになった。第３図がその結果
である。第３図の縦軸はＬｏ−２０μｍにおけるラッチ
アップ電流を１とした時のラッチアップ電流の変化率を
示す。図示のようにチャネル長２が５．５μｍ未満では
、ゲート電極幅し。が大きくなるとラッチアップ電流は
低下しているが、チャネル長２が５．５μｍ以上ではゲ
ート電極幅Ｌｏが大きくなってもラッチアップ電流の低
下は認められない。However, it has been experimentally revealed that this can be prevented by increasing channel 2 to a certain value or more. Figure 3 shows the results. The vertical axis in FIG. 3 shows the rate of change in latch-up current when the latch-up current at Lo-20 μm is set to 1. As shown in the figure, when the channel length 2 is less than 5.5 μm, the gate electrode width is small. The latch-up current decreases as becomes larger, but when the channel length 2 is 5.5 μm or more, no decrease in the latch-up current is observed even if the gate electrode width Lo increases.
以上を纒めると、チャネル長２を５．５μｍ以上、ゲー
ト電極幅しＧを３０μｍ以上に設定することにより、オ
ン電圧ＶＦを余り上昇させることなく、効果的にラッチ
アップ電流の増大を図ることができる。In summary, by setting the channel length 2 to 5.5 μm or more and the gate electrode width G to 30 μm or more, the latch-up current can be effectively increased without increasing the on-voltage VF too much. be able to.
次に負荷短絡耐量について説明する。順方向阻止電圧が
１０００Ｖ以上の導電変調型ＭＯ８ＦＥＴでは、取扱い
電圧が５００Ｖ以上になる。またゲート電圧は１５Ｖで
ある。従って、電ａ電圧１０００Ｖ、ゲート電圧１５Ｖ
の条件で負荷短絡通電をお°こない、１ｏμｓｅｃの間
素子が非破壊であれば、負荷短絡耐】は十分であるとい
える。そこで種々の構造パラメータについて実験を行っ
た結果、負荷短絡耐量はベース層とドレイン層に挟まれ
る高抵抗層の幅Ｗｎに依存することが明らかになった。Next, load short-circuit tolerance will be explained. A conduction modulation type MO8FET with a forward blocking voltage of 1000V or more has a handling voltage of 500V or more. Further, the gate voltage is 15V. Therefore, the electric voltage is 1000V, and the gate voltage is 15V.
It can be said that the load short circuit resistance is sufficient if the element is not destroyed for 1 μsec when the load short circuit is energized under the following conditions. As a result of conducting experiments on various structural parameters, it became clear that the load short-circuit withstand capability depends on the width Wn of the high-resistance layer sandwiched between the base layer and the drain layer.
第４図がそのデータであり、Ｗｎと素子の非破壊率の関
係をヒストグラムで表わしたものである。因から明らか
なように、Ｗｎが１２０μｍ以上になると非−壊率が急
激に高くなり、負荷短絡耐量が十分大きくなることが分
る。なお、ｗｎが同一のとき、低抵抗バッファ層がある
場合とない場合とでは、ある場合の方が負荷短絡耐量が
大きいことが確認された。FIG. 4 is the data, and is a histogram representing the relationship between Wn and the non-destructive rate of the element. As is clear from the above, when Wn is 120 μm or more, the non-destructive rate increases rapidly, and the load short-circuit resistance becomes sufficiently large. Note that, when wn is the same, it was confirmed that the load short-circuit tolerance is greater in the case with and without the low-resistance buffer layer.
なお本発明は上記実施例に限られるものではなく、その
趣旨を逸脱しない範囲で種々変形して実施することがで
きる。Note that the present invention is not limited to the above-mentioned embodiments, and can be implemented with various modifications without departing from the spirit thereof.
［発明の効果］
以上述べたように本発明によれば、素子パラメータの最
通設計により、オン電圧の上昇をもたらすことなくラッ
チアップ電流の増大を図ることができ、また負荷短絡耐
量の向上を図った導電変調型ＭＯ８ＦＥＴを得ることが
できる。[Effects of the Invention] As described above, according to the present invention, the latch-up current can be increased without causing an increase in the on-voltage, and the load short-circuit resistance can be improved by the flexible design of the element parameters. The desired conductivity modulation type MO8FET can be obtained.
第１図（ａ）（ｂ）は本発明の一実施例の導電変調型Ｍ
Ｏ５ＦＥＴを示す平面図とそのＡ−Ａ’断面図、第２図
はゲート電極幅ＬＧとオン電圧ＶＦの関係を示す図、第
３図は同じくゲート電極幅し。とラッチアップ電流ＩＬ
の関係を示す図、第４図は高抵抗層幅Ｗｎと素子の非破
壊率の関係を示す図、第５図はｐ型ベース圏の拡ｗ１深
さとオン電圧ＶＦおよびラッチアップ電ＲＩ Ｌの関係
を示す図である。
１１・・・ｐ１型ドレイン層、１２・・・ｎ＋型バッフ
ァＷｉ、１３・・・ｎ−型高抵抗層、１４・・・ゲート
絶縁膜、１５・・・ゲート電極、１６・・・間隙（開口
部）、１７・・・ｐ型ベース層、１８・・・ｎ４′型ソ
一ス層、１９・・・チャネル領域、２０・・・ソース電
極、２１・・・トレイン電極、２２・・・ｐ＋型層。
出願人代理人 弁理士 鈴江武彦
第２図
ＬＧ ［μｍ］
第３図
第４図FIGS. 1(a) and 1(b) show a conductive modulation type M according to an embodiment of the present invention.
A plan view showing an O5FET and its AA' cross-sectional view, FIG. 2 is a diagram showing the relationship between gate electrode width LG and on-voltage VF, and FIG. 3 is a diagram showing the relationship between gate electrode width LG and on-voltage VF. and latch-up current IL
4 is a diagram showing the relationship between the high resistance layer width Wn and the non-destructive rate of the element, and FIG. 5 is a diagram showing the relationship between the width Wn of the high resistance layer and the non-destructive rate of the element. It is a figure showing a relationship. DESCRIPTION OF SYMBOLS 11... p1 type drain layer, 12... n+ type buffer Wi, 13... n- type high resistance layer, 14... gate insulating film, 15... gate electrode, 16... gap ( opening), 17... p-type base layer, 18... n4' type source layer, 19... channel region, 20... source electrode, 21... train electrode, 22... p+ type layer. Applicant's agent Patent attorney Takehiko Suzue Figure 2 LG [μm] Figure 3 Figure 4
Claims (1)
た領域に前記高抵抗層より不純物濃度が高い第２導電型
の低抵抗バッファ層を有し、前記高抵抗層上にゲート絶
縁膜を介して格子状のゲート電極が配設され、このゲー
ト電極の間隙部からの不純物拡散により第１導電型ベー
ス層およびこのベース層内に位置する第２導電型ソース
層が形成され、前記ドレイン層にコンタクトするドレイ
ン電極、および前記ベース層とソース層の双方にコンタ
クトするソース電極を有する導電変調型ＭＯＳＦＥＴお
いて、前記ゲート電極直下のソース層と高抵抗層間に挟
まれたベース層表面に形成されるチャネル領域のチャネ
ル長をｌ、前記ゲート電極の幅をＬ＿Ｇ、前記ドレイン
層とベース層に挟まれる高抵抗層の幅をＷｎとしたとき
、 ｌ≧５．５μｍ Ｌ＿Ｇ≧３０μｍ Ｗｎ≧１２０μｍ を満たすことを特徴とする導電変調型ＭＯＳＦＥＴ。Claims: A low-resistance buffer layer of a second conductivity type having a higher impurity concentration than the high-resistance layer is provided in a region sandwiched between the drain layer of the first conductivity type and the high-resistance layer of the second conductivity type; A lattice-shaped gate electrode is disposed on the resistance layer via a gate insulating film, and impurity is diffused from the gap between the gate electrodes to form a first conductivity type base layer and a second conductivity type source located within the base layer. In a conductivity modulation type MOSFET, which has a drain electrode in contact with the drain layer, and a source electrode in contact with both the base layer and the source layer, the conductivity modulation type MOSFET has a conductivity modulation type MOSFET in which a conductivity modulation type MOSFET has a drain electrode in contact with the drain layer, and a source electrode in contact with both the base layer and the source layer. When the channel length of the channel region formed on the surface of the base layer is l, the width of the gate electrode is L_G, and the width of the high resistance layer sandwiched between the drain layer and the base layer is Wn, l≧5.5 μm. A conductive modulation type MOSFET that satisfies L_G≧30μm and Wn≧120μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12761486A JPS62283669A (en) | 1986-06-02 | 1986-06-02 | Conductivity modulation type mosfet |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12761486A JPS62283669A (en) | 1986-06-02 | 1986-06-02 | Conductivity modulation type mosfet |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62283669A true JPS62283669A (en) | 1987-12-09 |
Family
ID=14964445
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12761486A Pending JPS62283669A (en) | 1986-06-02 | 1986-06-02 | Conductivity modulation type mosfet |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62283669A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4990975A (en) * | 1988-12-16 | 1991-02-05 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate bipolar transistor and method of manufacturing the same |
| JPH0382162A (en) * | 1989-08-25 | 1991-04-08 | Fuji Electric Co Ltd | P channel insulated gate bipolar transistor |
| US5489788A (en) * | 1993-03-09 | 1996-02-06 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device with improved short-circuit tolerance |
| JPH0897168A (en) * | 1994-07-04 | 1996-04-12 | Sgs Thomson Microelettronica Spa | Manufacture of high dense mos type electric power device andhigh dense type electric power device manufactured by its method |
| US5569941A (en) * | 1992-10-20 | 1996-10-29 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device with a buried gapped semiconductor region |
| US5616938A (en) * | 1994-08-08 | 1997-04-01 | Asea Brown Boveri Ag | MOS-controlled power semiconductor component for high voltages |
-
1986
- 1986-06-02 JP JP12761486A patent/JPS62283669A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4990975A (en) * | 1988-12-16 | 1991-02-05 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate bipolar transistor and method of manufacturing the same |
| JPH0382162A (en) * | 1989-08-25 | 1991-04-08 | Fuji Electric Co Ltd | P channel insulated gate bipolar transistor |
| US5569941A (en) * | 1992-10-20 | 1996-10-29 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device with a buried gapped semiconductor region |
| US5489788A (en) * | 1993-03-09 | 1996-02-06 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device with improved short-circuit tolerance |
| JPH0897168A (en) * | 1994-07-04 | 1996-04-12 | Sgs Thomson Microelettronica Spa | Manufacture of high dense mos type electric power device andhigh dense type electric power device manufactured by its method |
| US5616938A (en) * | 1994-08-08 | 1997-04-01 | Asea Brown Boveri Ag | MOS-controlled power semiconductor component for high voltages |
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