JP2585505B2 - Conduction modulation type MOSFET - Google Patents
Conduction modulation type MOSFETInfo
- Publication number
- JP2585505B2 JP2585505B2 JP59204427A JP20442784A JP2585505B2 JP 2585505 B2 JP2585505 B2 JP 2585505B2 JP 59204427 A JP59204427 A JP 59204427A JP 20442784 A JP20442784 A JP 20442784A JP 2585505 B2 JP2585505 B2 JP 2585505B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- type
- diffusion layer
- source
- resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 claims description 8
- 239000011159 matrix material Substances 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 description 57
- 230000003071 parasitic effect Effects 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 230000002093 peripheral effect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
Description
【発明の詳細な説明】 〔発明の技術分野〕 本発明は、導電変調型MOSFETに関する。Description: TECHNICAL FIELD The present invention relates to a conduction modulation type MOSFET.
導電変調型MOSFETは、通常のパワーMOSFETのドレイン
領域をソース領域とは逆の導電型にしたものである。従
来の導電変調型MOSFETの構造を第７図に示す。41はp+ド
レイン層、42はn-型高抵抗層であり、この高抵抗層42の
表面にｐ型ベース拡散層43が形成され、更にこのｐ型ベ
ース拡散層43内にn+型ソース拡散層44が形成されてい
る。そして、ソース拡散層44と表面に露出している高抵
抗層42に挟まれたｐ型ベース層43部分をチャネル領域49
として、この上にゲート絶縁膜45を介してゲート電極46
を配設し、また、ソース拡散層44とベース拡散層43の双
方にコンタクトするソース電極47を形成している。ドレ
イン層41の表面にはドレイン電極48が形成されている。The conductivity modulation type MOSFET is obtained by changing the drain region of a normal power MOSFET to the conductivity type opposite to that of the source region. FIG. 7 shows the structure of a conventional conduction modulation type MOSFET. 41 p + drain layer, 42 the n - is the type high-resistance layer, the p-type base diffusion layer 43 on the surface of the high resistance layer 42 is formed, further n + -type source to the p-type base diffusion layer 43 A diffusion layer 44 is formed. Then, a portion of the p-type base layer 43 sandwiched between the source diffusion layer 44 and the high resistance layer 42 exposed on the surface is formed into a channel region 49.
As a gate electrode 46 over the gate insulating film 45.
Are formed, and a source electrode 47 that contacts both the source diffusion layer 44 and the base diffusion layer 43 is formed. On the surface of the drain layer 41, a drain electrode 48 is formed.
この導電変調型MOSFETでは、ゲート電極46にソース電
極47に対して正の電圧を印加するとチャネル領域49に反
転層が形成され、ソース拡散層44からの電子がこのチャ
ネル領域49を通ってn-型高抵抗層42に注入される。注入
された電子は高抵抗層42を拡散してドレイン電極48へ抜
けるが、このときドレイン層41から正孔の注入を引起こ
す。この正孔の注入により、高抵抗層42にはキャリアの
蓄積による導電変調が起こり、この高抵抗層42の抵抗が
低下する。これにより、通常のパワーMOSFETより低いオ
ン抵抗を持ったMOSFETが得られることになる。In this conduction modulation type MOSFET, when a positive voltage is applied to the gate electrode 46 and to the source electrode 47, an inversion layer is formed in the channel region 49, and electrons from the source diffusion layer 44 pass through the channel region 49 and n − Is injected into the mold high-resistance layer 42. The injected electrons diffuse through the high-resistance layer 42 and escape to the drain electrode 48. At this time, holes are injected from the drain layer 41. Due to the injection of holes, conductivity modulation due to accumulation of carriers occurs in the high-resistance layer 42, and the resistance of the high-resistance layer 42 decreases. As a result, a MOSFET having a lower on-resistance than a normal power MOSFET can be obtained.
ところでこの様な導電変調型MOSFETでは、p+型ドレイ
ン層41-n-型高抵抗層42−ｐ型ベース拡散層43-n+型ソー
ス拡散層44の四層がサイリスタを構成する。この寄生サ
イリスタが導通すると、ゲート・ソース間電圧を零にし
ても素子はオフできなくなり、多くの場合素子破壊に繋
がる。この寄生サイリスタがオンになる原因は、p+型ド
レイン層41から注入された正孔がソース電極47へ抜ける
際にｐ型ベース拡散層43を通ることにある。即ち、この
ような正孔電流が流れ、ベース拡散層43のベース拡散層
44直下の抵抗による電圧降下がベース・ソース間のビル
トイン電圧を越えると、ソース層44からの電子注入をも
たらし、寄生サイリスタがオンしてしまう。Incidentally, in such a conduction modulation type MOSFET, the four layers of the p + -type drain layer 41-n -- type high resistance layer 42-p-type base diffusion layer 43-n + -type source diffusion layer 44 constitute a thyristor. When the parasitic thyristor conducts, the element cannot be turned off even if the gate-source voltage is reduced to zero, which often leads to element destruction. The reason that the parasitic thyristor is turned on is that holes injected from the p + -type drain layer 41 pass through the p-type base diffusion layer 43 when they escape to the source electrode 47. That is, such a hole current flows, and the base diffusion layer 43
If the voltage drop due to the resistor immediately below the gate exceeds the built-in voltage between the base and the source, electrons are injected from the source layer 44, and the parasitic thyristor is turned on.
このような寄生サイリスタのラッチング現象を防止す
るため、第８図に示すようにｐ型ベース拡散層43に高濃
度のp+型ベース拡散層50を形成してｐ型ベース拡散層の
抵抗を下げることが行われている。しかし、このように
しても、従来の導電変調型MOSFETでは高々200A/cm2程度
の電流しかオフすることができない、という問題があっ
た。その根本的な理由を追及した結果、従来の導電変調
型MOSFETが、通常のパワーMOSFETと同じソース、ゲート
のパターンを用いていることにあることが明らかになっ
た。この点を以下に詳細に説明する。In order to prevent such a parasitic thyristor latching phenomenon, a high-concentration p + -type base diffusion layer 50 is formed in the p-type base diffusion layer 43 as shown in FIG. 8 to reduce the resistance of the p-type base diffusion layer. That is being done. However, even in this case, there is a problem that the conventional conductive modulation type MOSFET can turn off only a current of at most about 200 A / cm 2 . As a result of pursuing the fundamental reason, it became clear that the conventional conduction modulation type MOSFET uses the same source and gate pattern as a normal power MOSFET. This will be described in detail below.
第９図は第８図の導電変調型MOSFETの拡散層パターン
を示している。図のようにｐ型ベース拡散層43は六角形
状に複数個拡散形成され、それぞれの周辺部にチャネル
領域49が形成されるパターンとなっている。このような
パターンはパワーMOSFETでは、ゲート面積を大きくして
オン抵抗を小さくする意味で有効なものであった。しか
しながら、寄生サイリスタをオンさせてはならない、と
いう要請がある導電変調型MOSFETでは、このようなパタ
ーンでは次のような不都合があった。FIG. 9 shows a diffusion layer pattern of the conduction modulation type MOSFET shown in FIG. As shown in the figure, a plurality of p-type base diffusion layers 43 are diffused and formed in a hexagonal shape, and have a pattern in which a channel region 49 is formed in each peripheral portion. Such a pattern is effective for a power MOSFET in terms of increasing the gate area and decreasing the on-resistance. However, in the conductive modulation type MOSFET which requires that the parasitic thyristor not be turned on, such a pattern has the following disadvantages.
第１に、寄生サイリスタ動作を防止する、即ちラッチ
アップを防止するためには、チャネル領域49からp+型ベ
ース拡散層50の開口部までの抵抗ができるだけ小さいこ
とが望ましい。ところが第９図のパターンでは、p+型ベ
ース拡散層50のソース電極とのコンタクトがｐ型ベース
拡散層43の中心部に形成されていて、その周囲長はｐ型
ベース拡散層43の周辺にあるチャネル領域49の長さに比
べて小さく、その広がり抵抗のためチャネル領域49とp+
型ベース拡散層50のソース電極とのコンタクトの間の抵
抗を十分小さくすることができない。このため、ラッチ
アップを効果的に防止することができなかった。First, in order to prevent the parasitic thyristor operation, that is, to prevent latch-up, it is desirable that the resistance from the channel region 49 to the opening of the p + -type base diffusion layer 50 be as small as possible. However, in the pattern of FIG. 9, the contact with the source electrode of the p + -type base diffusion layer 50 is formed at the center of the p-type base diffusion layer 43, and its peripheral length is around the p-type base diffusion layer 43. It is smaller than the length of a certain channel region 49, and because of its spreading resistance, the channel region 49 and p +
The resistance between the mold base diffusion layer 50 and the contact with the source electrode cannot be sufficiently reduced. For this reason, latch-up could not be effectively prevented.
第２に、第９図のパターンでは、n-型高抵抗層42の基
板ウェーハ表面に露出する開口部の幅LG、即ちゲート電
極が配設される部分のおよその幅が大きいことがサイリ
スタ動作をし易くしていることが本発明者等の研究によ
り明らかになった。Second, in the pattern of FIG. 9, the thyristor indicates that the width L G of the opening of the n − -type high resistance layer 42 exposed on the surface of the substrate wafer, that is, the approximate width of the portion where the gate electrode is provided, is large. Research by the present inventors has revealed that the operation is facilitated.
寄生サイリスタのラッチング時のドレイン電流がLGに
逆比例することは次のように示される。ゲート絶縁膜下
には略一様に電流が流れこれがｐ型ベース層に流れ込む
ので、チャネル領域49の単位長さの横幅のゲート絶縁膜
下には次の電流IPが流れ込む。The drain current at the time of latching of the parasitic thyristor is inversely proportional to L G are shown as follows. Since a substantially uniform current flows under the gate insulating film which flows into the p-type base layer, the next current I P flowing in under the gate insulating film of the horizontal width of the unit length of the channel region 49.
IP＝SG・JP/T ……（１） ここでJPは正孔電流密度であり、SGは単位面積当りのn-
型高抵抗層開口部の面積、Ｔは単位面積当りのｐ型ベー
ス拡散層の周囲長である。この電流がソース拡散層下の
ベース拡散層に流れ込み、ソース拡散層下の抵抗RBによ
る電圧降下がベース・ソース間のビルトイン電圧Vbiよ
り高くなると、寄生サイリスタがオンする。これを式で
表わすと、 Vbi＝IP・RB/T ＝SG・JP・RB/T ……（２） となる。但しRBは単位の周囲長当りのｐ型ベース層のチ
ャネルからp+コンタクトまでの抵抗である。これをJPに
ついて解くと、 JP＝Vbi・T/（SG・RB） ……（３） となる。ターンオフ時にはチャネルの反転層は消失し、
殆ど正孔電流になるので、ラッチングする電流密度J
Lは、 JL＝Vbi・T/（SG・RB） ……（４） となる。SG/Tは概略LGとなり、JLはLGに逆比例すること
になる。このことは、本発明者らの実験データである第
11図からも明らかである。 I P = S G · J P / T ...... (1) where J P is the hole current density, S G is per unit area n -
The area of the opening of the type high resistance layer, T is the perimeter of the p-type base diffusion layer per unit area. Flows the current to the base diffusion layer below the source diffusion layer, the voltage drop due to the resistance R B under the source diffusion layer is higher than the built-in voltage Vbi between the base and source, the parasitic thyristor is turned on. Denoting this formula, the Vbi = I P · R B / T = S G · J P · R B / T ...... (2). However R B is the resistance of the channel of the p-type base layer per peripheral length of the unit to the p + contact. Solving this for J P gives J P = Vbi · T / (S G · R B ) (3) At the time of turn-off, the channel inversion layer disappears,
Since the current becomes almost a hole current, the latching current density J
L is expressed by J L = Vbi · T / (S G · R B ) (4) S G / T is next outline L G, J L will be inversely proportional to L G. This is based on the experimental data of the present inventors.
This is clear from FIG.
一方、例えば第10図の斜視図に示すように、ゲート電
極46を多結晶シリコン膜461とAl膜462の積層構造とした
場合、Al膜462の幅を30μｍとすると、多結晶シリコン
膜461の幅は50〜60μｍ必要である。即ち、n-型高抵抗
層42の開口部の幅LGとして50〜60μｍ必要になる。この
場合、第11図からも分かるように、ラッチアップする電
流密度JLが低くなってしまう。On the other hand, for example, as shown in the perspective view of FIG. 10, when the gate electrode 46 and the polycrystalline silicon film 46 1 and the Al film 46 2 of the laminated structure, when the 30μm width of the Al film 46 2, polycrystalline silicon the width of film 46 1 is required 50-60. That, n - 50-60 required as the width L G of the opening of the -type high resistance layer 42. In this case, as can be seen from FIG. 11, the latch-up current density J L becomes low.
以上のようなことが、従来の導電変調型MOSFETのラッ
チアップを効果的に防止することができない理由となっ
ていたのである。The above is the reason why latch-up of the conventional conduction modulation type MOSFET cannot be effectively prevented.
上述の如く、従来の導電変調型MOSFETはラッチアップ
を効果的に防止することができないという問題があっ
た。As described above, the conventional conduction modulation type MOSFET has a problem that latch-up cannot be effectively prevented.
本発明は、上記事情を考慮してなされたもので、その
目的とするところは、ラッチアップが起こり難い導電変
調型MOSFETを提供することにある。The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a conductive modulation type MOSFET in which latch-up hardly occurs.
上記の目的を達するための本発明の導電変調型MOSFET
は、高濃度、第１導電型のドレイン層および第２導電型
の高抵抗層を有する半導体基板ウェーハと、前記高抵抗
層部分に形成された第１導電型のベース層と、このベー
ス層内に形成された高濃度、第２導電型のソース層と、
このソース層および前記高抵抗層に挟まれたチャネル領
域となる前記ベース層上にゲート絶縁膜を介して形成さ
れたゲート電極と、前記ソース層および前記ベース層の
双方にコンタクトするソース電極と、前記ドレイン層に
コンタクトするドレイン電極とを備えた導電変調型MOSF
ETにおいて、前記高抵抗層の前記ウェーハ表面に露出し
た開口部が前記ベース層に完全に囲まれた複数の島状を
なしていることを特徴とする。To achieve the above object, a conductive modulation type MOSFET of the present invention
A semiconductor substrate wafer having a high-concentration, first-conductivity-type drain layer and a second-conductivity-type high-resistance layer; a first-conductivity-type base layer formed in the high-resistance layer portion; A high-concentration, second-conductivity-type source layer formed at
A gate electrode formed on the base layer serving as a channel region interposed between the source layer and the high-resistance layer via a gate insulating film; a source electrode contacting both the source layer and the base layer; A conductive modulation type MOSF having a drain electrode contacting the drain layer
In the ET, an opening portion of the high-resistance layer exposed on the wafer surface has a plurality of islands completely surrounded by the base layer.
本発明では、高抵抗層のウェーハ表面に露出する部分
がベース拡散層を取り囲む従来のパターンとは逆に、高
抵抗層のウェーハ表面に露出する部分がベース拡散層に
囲まれて複数の島状に配置されるパターンを採用してい
る。According to the present invention, the portion of the high-resistance layer exposed on the wafer surface surrounds the base diffusion layer, and the portion of the high-resistance layer exposed on the wafer surface is surrounded by the base diffusion layer, thereby forming a plurality of islands. Is adopted.
このようなパターンを採用すると、チャネル領域下の
ベース層抵抗が従来よりも小さくなるのでラッチアップ
が起こる電流密度が高くなり、効果的にラッチアップを
防止できる。When such a pattern is employed, the resistance of the base layer under the channel region becomes smaller than in the conventional case, so that the current density at which the latch-up occurs increases, and the latch-up can be effectively prevented.
以下、図面を参照しながら実施例を説明する。 Hereinafter, embodiments will be described with reference to the drawings.
第１図は、本発明の実施例を示す導電変調型MOSFETの
平面図である。FIG. 1 is a plan view of a conductive modulation type MOSFET showing an embodiment of the present invention.
p+型ドレイン層（不図示）の上にn-型高抵抗層（不図
示）があり、このn-型高抵抗層の表面にｐ型ベース拡散
層13が形成され、更にベース拡散層13内にn+型ソース拡
散層14が形成されている。そして、n+型ソース拡散層14
とn-型高抵抗層のウェーハ表面開口部との間をチャネル
領域21として、この上にゲート絶縁膜（不図示）を介し
て多結晶シリコン膜によるゲート電極17が形成されてい
る。ソース拡散層14とベース拡散層13の双方にコンタク
トするソース電極18が設けられ、ウェーハ裏面のドレイ
ン層にはドレイン電極（不図示）が設けられている。多
結晶シリコン膜ゲート電極17はチャネル領域21と高抵抗
層の長方形状開口部を覆うように基板ウェーハ全面に連
続的に配設され、この上のソース電極18が走らない部分
にストライプ状のAlゲート電極20が配列される。この多
結晶シリコン膜ゲート電極17上に重ねたAl電極20の下に
高濃度のp+型ベース拡散層（不図示）を形成して、ｐ型
ベース拡散層13とp+型ベース拡散層によってn-型高抵抗
層の長方形開口部を囲っている。An n -- type high resistance layer (not shown) is provided on the p + -type drain layer (not shown), and a p-type base diffusion layer 13 is formed on the surface of the n -- type high resistance layer. An n + type source diffusion layer 14 is formed therein. Then, the n + type source diffusion layer 14
A gate electrode 17 made of a polycrystalline silicon film is formed on a channel region 21 between the substrate and the opening of the wafer surface of the n − -type high resistance layer via a gate insulating film (not shown). A source electrode 18 that contacts both the source diffusion layer 14 and the base diffusion layer 13 is provided, and a drain electrode (not shown) is provided on a drain layer on the back surface of the wafer. The polycrystalline silicon film gate electrode 17 is continuously disposed on the entire surface of the substrate wafer so as to cover the channel region 21 and the rectangular opening of the high resistance layer, and a stripe-shaped Al is formed on a portion where the source electrode 18 does not run. Gate electrodes 20 are arranged. A high-concentration p + -type base diffusion layer (not shown) is formed under the Al electrode 20 overlying the polycrystalline silicon film gate electrode 17, and the p-type base diffusion layer 13 and the p + -type base diffusion layer Surrounds the rectangular opening of the n - type high resistance layer.
ここで第２図に、第１図では見えていない本発明の特
徴部分、すなわち複数の島状をなしている、n-型高抵抗
層の長方形開口部を取り出した概略平面図を示す。また
第３図〜第５図はそれぞれ第２図のＡ−Ａ′断面図、Ｂ
−Ｂ′断面図、Ｃ−Ｃ′断面図である。なお第１図と第
３図〜第５図とでは素子の構造が若干異なる。Here, FIG. 2 is a schematic plan view showing a characteristic portion of the present invention that is not visible in FIG. 1, that is, a rectangular opening of the n − -type high-resistance layer, which has a plurality of islands. 3 to 5 are sectional views taken along line AA 'of FIG.
It is a sectional view taken along the line -B 'and CC'. 1 and FIGS. 3 to 5 have slightly different element structures.
p+型ドレイン層11の上にn-型高抵抗層12があり、この
高抵抗層12の表面にｐ型ベース拡散層13が形成され、更
にベース拡散層13内にn+型ソース拡散層４が形成されて
いる。またｐ型ベース拡散層13には高濃度のp+型ベース
拡散層15が形成されている。そしてソース拡散層14と高
抵抗層12のウェーハ表面開口部との間をチャネル領域21
として、この上にゲート絶縁膜16を介して多結晶シリコ
ン膜によるゲート電極17が形成されている。ソース拡散
層14とベース拡散層15の双方にコンタクトするソース電
極18が設けられ、ウェーハ裏面のドレイン層11にはドレ
イン電極19が設けられている。さらに第３図、第４図に
示すような部分にもp+型ベース層15が形成されている。An n − -type high-resistance layer 12 is provided on the p + -type drain layer 11, a p-type base diffusion layer 13 is formed on the surface of the high-resistance layer 12, and an n + -type source diffusion layer 4 are formed. A high concentration p + -type base diffusion layer 15 is formed in the p-type base diffusion layer 13. A channel region 21 is formed between the source diffusion layer 14 and the opening on the wafer surface of the high-resistance layer 12.
On this, a gate electrode 17 of a polycrystalline silicon film is formed via a gate insulating film 16. A source electrode 18 that contacts both the source diffusion layer 14 and the base diffusion layer 15 is provided, and a drain electrode 19 is provided on the drain layer 11 on the back surface of the wafer. Further, the p + -type base layer 15 is formed also in the portion as shown in FIGS.
これらの実施例の特徴は、第１に、ゲート電極17の下
に開口する高抵抗層12の部分を第１図、第２図に幅LGで
示される略長方形として複数個マトリクス状に配列し、
少なくともその長辺に沿ってチャネル領域21を形成して
いることである。長方形を用いた理由は、n-型高抵抗層
12を島状とするときに、チャネル領域21の横幅を最も長
くできるからである。第２の特徴は、そのような複数の
長方形の開口部がベース拡散層にそれぞれ完全に囲まれ
て島状になるようにしていることである。Features of these embodiments, the first, first view a portion of the high-resistance layer 12 which opens under the gate electrode 17, a plurality matrix in sequence as substantially rectangular represented by the width L G in Figure 2 And
That is, the channel region 21 is formed at least along the long side. The reason for using the rectangle is that the n - type high resistance layer
This is because the width of the channel region 21 can be maximized when the islands 12 are formed. A second feature is that such a plurality of rectangular openings are completely surrounded by the base diffusion layer so as to form an island shape.
なお実際の素子構造は、例えばドレイン層11となるp+
型Si基板を出発基板としてこれにn-型高抵抗層12をエピ
タキシャル成長させたウェーハを用い、これに不純物拡
散、電極形成を順次行なう。n-型高抵抗層12を出発基板
としてももちろん良い。Note that the actual element structure is, for example, p +
Using a silicon substrate as a starting substrate, a wafer on which an n − -type high resistance layer 12 is epitaxially grown is used, and impurity diffusion and electrode formation are sequentially performed on the wafer. Of course, the n - type high resistance layer 12 may be used as a starting substrate.
これらの実施例から明らかなように、ゲート電極17の
下に開口する長方形の高抵抗層12の周囲にあるチャネル
領域21の全横幅と、ソース電極18とコンタクトするベー
ス拡散層の開口部の周囲長とはほぼ等しい。このため、
第９図のような従来の構造に比べて広がり抵抗がないの
で、ソース拡散層14の下のベース拡散層抵抗が小さい。
また第１図〜第５図のいずれも、高抵抗層12がウェーハ
表面に開口する部分の上は多結晶シリコン膜によるゲー
ト電極17のみでありAlゲート電極がないから、この部分
のゲート電極幅LGは十分小さくできる。このLGは前述し
たようにラッチングする電流密度に逆比例する。実際の
試作例ではLG＝15μｍとしている。したがって、これら
の実施例によれば従来より効果的にラッチアップ現象を
防止することができ、ラッチアップの電流密度750A/cm2
が得られている。また全動作面積20mm2として150Aまで
の電流をターンオフすることができた。As is apparent from these examples, the entire width of the channel region 21 around the rectangular high-resistance layer 12 opening below the gate electrode 17 and the area around the opening of the base diffusion layer in contact with the source electrode 18. It is almost equal to length. For this reason,
Since there is no spreading resistance as compared with the conventional structure as shown in FIG. 9, the resistance of the base diffusion layer under the source diffusion layer 14 is small.
In each of FIGS. 1 to 5, only the gate electrode 17 of the polycrystalline silicon film is present above the portion where the high-resistance layer 12 is opened on the wafer surface, and there is no Al gate electrode. L G can be made sufficiently small. The L G is inversely proportional to the current density latching as previously described. In an actual prototype, L G = 15 μm. Therefore, according to these embodiments, it is possible to prevent the latch-up phenomenon more effectively than before, and the current density of the latch-up is 750 A / cm 2
Has been obtained. Also it was possible to turn off the current to 150A as full operating area 20 mm 2.
本発明は上記実施例に限られない。例えば、ウェーハ
表面に露出する高抵抗層部分の形状は必ずしも長方形で
なくてもよい。従来の第９図のパターンに対応させてソ
ース電極とのコンタクトをとるp+型ベース拡散層とゲー
ト電極下に開口するn-型高抵抗層の配置をこれと逆にし
た場合の実施例のパターンを第６図に示す。なお第６図
において第１図〜第５図と対応する部分には同じ符号を
付してある。このようなパターンを用いれば、第９図と
の比較で本発明の効果が説明し易い。いま、ソース拡散
層14の幅Lnが第９図と同じであり、かつチャネル領域21
の長さおよび横幅Ｔ（周囲長）がやはり第９図と同じと
する。第６図の場合、ゲート電極下の高抵抗層12からチ
ャネル領域21下を通ってp+型ベース拡散層15に抜ける正
孔電流の電流経路は第９図の従来のものとは逆である。
したがって、同じ周辺長の高抵抗層開口部からのp+型ベ
ース拡散層のソース電極とのコンタクト部までのチャネ
ル領域下のベース抵抗は、第９図のようにp+型ベース拡
散層がチャネル領域に囲まれて中心にある場合に比べて
明らかに小さい。これにより、本発明のパターンの方が
従来よりラッチアップしにくいことになる。The present invention is not limited to the above embodiment. For example, the shape of the high resistance layer portion exposed on the wafer surface is not necessarily rectangular. In the embodiment in which the arrangement of the p + -type base diffusion layer for making contact with the source electrode and the n -- type high resistance layer opening under the gate electrode is reversed in accordance with the conventional pattern of FIG. The pattern is shown in FIG. In FIG. 6, parts corresponding to those in FIGS. 1 to 5 are denoted by the same reference numerals. If such a pattern is used, the effect of the present invention can be easily explained in comparison with FIG. Now, the width Ln of the source diffusion layer 14 is the same as in FIG.
And the width T (perimeter) is also the same as in FIG. In the case of FIG. 6, the current path of the hole current flowing from the high-resistance layer 12 under the gate electrode to the p + -type base diffusion layer 15 through below the channel region 21 is opposite to the conventional one in FIG. .
Accordingly, the base resistance under the channel region to the contact portion between the source electrode of the p + -type base diffusion layer of the high-resistance layer openings of the same peripheral length, p + -type base diffusion layer channel as FIG. 9 It is clearly smaller than in the center when surrounded by the area. As a result, the pattern of the present invention is less likely to latch up than in the past.
また、島状の高抵抗層部分は、少なくとも平行な二辺
を有する長方形に類似の形状であって、それぞれの四辺
または二つの長辺に沿ってチャネル領域が形成されるよ
うにしてもよい。Further, the island-like high resistance layer portion may have a shape similar to a rectangle having at least two parallel sides, and a channel region may be formed along each of four sides or two long sides.
また、一般的に（４）式において、SGは高抵抗層の開
口部の面積、Ｔは同開口部の周辺長即ちチャネルの横幅
であるから、第６図と第９図でＴが同じである場合、SG
・RBは第９図の方が大きいので、一般的に第９図の方が
ラッチアップする電流密度JLは小さい。従来のパワーMO
SFETで用いられた第９図のようなパターンは現在では全
く使われていない。それは高耐圧パワーMOSFETでは、高
抵抗層の開口部の面積SGや周囲長Ｔを大きくしないとオ
ン抵抗が増大してしまうことが明らかになったためであ
る。しかし、導電変調型MOSFETはn-型高抵抗層は導電変
調を受けて抵抗が低くなっているため開口部の面積をパ
ワーMOSFETのように広くする必要がない。Further, in general formula (4), S G is the area of the opening of the high-resistance layer, T is because the lateral width of the perimeter or channels of the openings, the T in FIG. 6 and FIG. 9 same , Then S G
Since · R B is is larger in FIG. 9, the current density J L of the general public to FIG. 9 to latch-up is small. Conventional power MO
The pattern shown in FIG. 9 used in the SFET is not used at all at present. This is because it has been clarified that the on-resistance of the high voltage power MOSFET increases unless the area SG and the perimeter T of the opening of the high resistance layer are increased. However, since the resistance of the n - type high resistance layer of the conductivity modulation type MOSFET is reduced due to the modulation of the conductivity, the opening area does not need to be widened as in the power MOSFET.
以上の説明から明らかなように、本発明を導電変調型
MOSFETに適用するとパワーMOSFETに適用した場合とは全
く異なる大きい効果を発揮することができる。As is apparent from the above description, the present invention relates to a conductive modulation type.
When applied to a MOSFET, a great effect completely different from that when applied to a power MOSFET can be exhibited.
第１図は本発明の実施例に係る導電変調型MOSFETの平面
図、第２図は本発明の実施例に係る導電変調型MOSFETの
概略平面図、第３図は第２図の導電変調型MOSFETのＡ−
Ａ′断面図、第４図は第２図の導電変調型MOSFETのＢ−
Ｂ′断面図、第５図は第２図の導電変調型MOSFETのＣ−
Ｃ′断面図、第６図は本発明の他の実施例に係る導電変
調型MOSFETの拡散層パターンを示す図、第７図は従来の
導電変調型MOSFETの断面図、第８図は従来の他の導電変
調型MOSFETの断面図、第９図は従来の導電変調型MOSFET
の拡散層パターンを示す図、第10図は従来の導電変調型
MOSFETの斜視図、第11図はラッチング特性を示す実験デ
ータである。 11……p+型ドレイン層、12……n-型高抵抗層、13……ｐ
型ベース拡散層、14……n+型ソース拡散層、15……p+ベ
ース拡散層、16……ゲート絶縁膜、17……多結晶シリコ
ン膜ゲート電極、18……ソース電極、19……ドレイン電
極、20……Alゲート電極、21……チャネル領域。FIG. 1 is a plan view of a conductive modulation type MOSFET according to an embodiment of the present invention, FIG. 2 is a schematic plan view of a conductive modulation type MOSFET according to an embodiment of the present invention, and FIG. 3 is a conductive modulation type MOSFET of FIG. MOSFET A-
FIG. 4 is a sectional view taken along line A 'of FIG.
FIG. 5 is a sectional view taken along the line B 'of FIG.
FIG. 6 is a view showing a diffusion layer pattern of a conduction modulation type MOSFET according to another embodiment of the present invention, FIG. 7 is a sectional view of a conventional conduction modulation type MOSFET, and FIG. FIG. 9 is a cross-sectional view of another conduction modulation type MOSFET, and FIG. 9 is a conventional conduction modulation type MOSFET.
Fig. 10 shows the diffusion layer pattern of Fig. 10.
FIG. 11 is a perspective view of a MOSFET, and FIG. 11 is experimental data showing latching characteristics. 11 ...... p + -type drain layer, 12 ...... n - -type high resistance layer, 13 ...... p
Type base diffusion layer, 14 ...... n + -type source diffusion layer, 15 ...... p + base diffusion layer, 16 ...... gate insulating film, 17 ...... polycrystalline silicon film gate electrode, 18 ...... source electrode, 19 ...... Drain electrode, 20 ... Al gate electrode, 21 ... Channel region.
フロントページの続き (72)発明者 渡辺 君則 川崎市幸区小向東芝町１番地 株式会社 東芝総合研究所内 (72)発明者 大橋 弘通 川崎市幸区小向東芝町１番地 株式会社 東芝総合研究所内 (56)参考文献 特開 昭59−149058（ＪＰ，Ａ) 特開 昭58−197771（ＪＰ，Ａ)Continued on the front page (72) Inventor Kiminori Watanabe 1 Toshiba, Komukai Toshiba-cho, Kawasaki-shi Toshiba Research Institute, Inc. In-house (56) References JP-A-59-149058 (JP, A) JP-A-58-197771 (JP, A)
Claims (3)
２導電型の高抵抗層を有する半導体基板ウェーハと、前
記高抵抗層部分に形成された第１導電型のベース層と、
このベース層内に形成された高濃度、第２導電型のソー
ス層と、このソース層および前記高抵抗層に挟まれたチ
ャネル領域となる前記ベース層上にゲート絶縁膜を介し
て形成されたゲート電極と、前記ソース層および前記ベ
ース層の双方にコンタクトするソース電極と、前記ドレ
イン層にコンタクトするドレイン電極とを備えた導電変
調型MOSFETにおいて、前記高抵抗層の前記ウェーハ表面
に露出した開口部が前記ベース層に完全に囲まれた複数
の島状をなしていることを特徴とする導電変調型MOSFE
T。A semiconductor substrate wafer having a high-concentration, first-conductivity-type drain layer and a second-conductivity-type high-resistance layer; a first-conductivity-type base layer formed on the high-resistance layer portion;
A high-concentration, second-conductivity-type source layer formed in the base layer and a gate insulating film formed on the base layer serving as a channel region sandwiched between the source layer and the high-resistance layer. In a conductive modulation type MOSFET including a gate electrode, a source electrode contacting both the source layer and the base layer, and a drain electrode contacting the drain layer, an opening exposed on the wafer surface of the high resistance layer A plurality of islands completely surrounded by the base layer.
T.
とも平行な二辺を有する形状であることを特徴とする特
許請求の範囲第１項記載の導電変調型MOSFET。2. The conductive modulation type MOSFET according to claim 1, wherein said plurality of island-like high resistance layer portions have a shape having at least two parallel sides.
れ長方形をなしてマトリクス状に配列形成され、それぞ
れの長辺に沿ってチャネル領域が形成されていることを
特徴とする特許請求の範囲第１項記載の導電変調型MOSF
ET。3. A plurality of island-shaped high-resistance layer portions are each formed in a rectangular shape and arranged in a matrix, and a channel region is formed along each long side. 2. The conductive modulation type MOSF according to claim 1,
ET.
Priority Applications (13)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59204427A JP2585505B2 (en) | 1984-09-29 | 1984-09-29 | Conduction modulation type MOSFET |
| US06/738,188 US4672407A (en) | 1984-05-30 | 1985-05-28 | Conductivity modulated MOSFET |
| DE3546745A DE3546745C2 (en) | 1984-05-30 | 1985-05-30 | Variable conductivity power MOSFET |
| DE19853519389 DE3519389A1 (en) | 1984-05-30 | 1985-05-30 | VARIABLE CONDUCTIVITY MOSFET |
| GB08513599A GB2161649B (en) | 1984-05-30 | 1985-05-30 | Conductivity modulated mosfet |
| US07/019,337 US4782372A (en) | 1984-05-30 | 1987-02-26 | Lateral conductivity modulated MOSFET |
| US07/116,357 US4881120A (en) | 1984-05-30 | 1987-11-04 | Conductive modulated MOSFET |
| US07/146,405 US5093701A (en) | 1984-05-30 | 1988-01-21 | Conductivity modulated mosfet |
| US07/205,365 US4928155A (en) | 1984-05-30 | 1988-06-10 | Lateral conductivity modulated MOSFET |
| US07/712,997 US5086323A (en) | 1984-05-30 | 1991-06-10 | Conductivity modulated mosfet |
| US07/799,311 US5286984A (en) | 1984-05-30 | 1991-11-27 | Conductivity modulated MOSFET |
| US08/261,254 US5780887A (en) | 1984-05-30 | 1994-06-14 | Conductivity modulated MOSFET |
| US09/104,326 US6025622A (en) | 1984-05-30 | 1998-06-25 | Conductivity modulated MOSFET |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59204427A JP2585505B2 (en) | 1984-09-29 | 1984-09-29 | Conduction modulation type MOSFET |
Related Child Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10864194A Division JP2645219B2 (en) | 1994-05-23 | 1994-05-23 | Conduction modulation type MOSFET |
| JP6108640A Division JPH0789588B2 (en) | 1994-05-23 | 1994-05-23 | Lateral conductivity modulation type MOSFET |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6182477A JPS6182477A (en) | 1986-04-26 |
| JP2585505B2 true JP2585505B2 (en) | 1997-02-26 |
Family
ID=16490355
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59204427A Expired - Lifetime JP2585505B2 (en) | 1984-05-30 | 1984-09-29 | Conduction modulation type MOSFET |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2585505B2 (en) |
Families Citing this family (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5212396A (en) * | 1983-11-30 | 1993-05-18 | Kabushiki Kaisha Toshiba | Conductivity modulated field effect transistor with optimized anode emitter and anode base impurity concentrations |
| US4809045A (en) * | 1985-09-30 | 1989-02-28 | General Electric Company | Insulated gate device |
| JP2513640B2 (en) * | 1986-09-17 | 1996-07-03 | 株式会社東芝 | Conduction modulation type MOSFET |
| JPH0821713B2 (en) * | 1987-02-26 | 1996-03-04 | 株式会社東芝 | Conduction modulation type MOSFET |
| US5237186A (en) * | 1987-02-26 | 1993-08-17 | Kabushiki Kaisha Toshiba | Conductivity-modulation metal oxide field effect transistor with single gate structure |
| US5105243A (en) * | 1987-02-26 | 1992-04-14 | Kabushiki Kaisha Toshiba | Conductivity-modulation metal oxide field effect transistor with single gate structure |
| JP2732495B2 (en) * | 1987-09-24 | 1998-03-30 | 株式会社日立製作所 | Insulated gate semiconductor device |
| JPS6490561A (en) * | 1987-09-30 | 1989-04-07 | Mitsubishi Electric Corp | Semiconductor device |
| JPH0828506B2 (en) * | 1988-11-07 | 1996-03-21 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
| US5171696A (en) * | 1988-11-07 | 1992-12-15 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of manufacturing the same |
| JP2752184B2 (en) * | 1989-09-11 | 1998-05-18 | 株式会社東芝 | Power semiconductor device |
| EP0696054B1 (en) * | 1994-07-04 | 2002-02-20 | STMicroelectronics S.r.l. | Process for the manufacturing of high-density MOS-technology power devices |
| WO2006125330A1 (en) * | 2005-05-24 | 2006-11-30 | Abb Schweiz Ag | Cathode cell design |
| JP2014038896A (en) * | 2012-08-13 | 2014-02-27 | Sumitomo Electric Ind Ltd | Silicon carbide semiconductor device |
| US9214572B2 (en) * | 2013-09-20 | 2015-12-15 | Monolith Semiconductor Inc. | High voltage MOSFET devices and methods of making the devices |
| US9991376B2 (en) | 2013-09-20 | 2018-06-05 | Monolith Semiconductor Inc. | High voltage MOSFET devices and methods of making the devices |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| IE55992B1 (en) * | 1982-04-05 | 1991-03-13 | Gen Electric | Insulated gate rectifier with improved current-carrying capability |
| JPS59149058A (en) * | 1983-02-15 | 1984-08-25 | Matsushita Electric Works Ltd | Metal oxide semiconductor type transistor |
-
1984
- 1984-09-29 JP JP59204427A patent/JP2585505B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6182477A (en) | 1986-04-26 |
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