JPH0512868B2 - - Google Patents
Info
- Publication number
- JPH0512868B2 JPH0512868B2 JP59110244A JP11024484A JPH0512868B2 JP H0512868 B2 JPH0512868 B2 JP H0512868B2 JP 59110244 A JP59110244 A JP 59110244A JP 11024484 A JP11024484 A JP 11024484A JP H0512868 B2 JPH0512868 B2 JP H0512868B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- base layer
- source
- mosfet
- conductivity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000969 carrier Substances 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 description 8
- 238000009792 diffusion process Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Description
【発明の詳細な説明】 〔発明の技術分野〕 本発明は、導電変調型MOSFETに関する。[Detailed description of the invention] [Technical field of invention] The present invention relates to a conductivity modulation type MOSFET.
〔発明の技術的背景とその問題点〕
近年、電力用スイツチング素子として、DSA
（Diffusion Self Align）法によりソースおよび
チヤネル領域を形成するパワーMOSFETが市場
に現れている。しかしこの素子は1000V以上の高
耐圧ではオン抵抗が高くなつてしまい、大電流を
流すことが難しい。これに代わる有力な素子とし
て、ドレイン領域にソースとは逆の導電型層を設
けることにより高抵抗層に導電変調を起こさせて
オン抵抗を下げるようにした、いわゆる導電変調
型MOSFETが知られている。その基本的な構造
を第１図に示す。１１はp+−Si基板（ドレイン
層）であつて、この上に低不純物濃度の高抵抗
n-層（第１ベース層）１２が形成され、このn-
層１２の表面にDSA法によりｐベース層（第２
ベース層）１３とn+ソース層１４が形成されて
いる。即ちｐベース層１３を拡散形成した拡散窓
をそのままn+ソース層１４の拡散窓の一部とし
て用いて二重拡散することにより、ｐベース層１
３の端部に自己整合的にチヤネル領域１９を残し
た状態でn+ソース層１４が形成される。そして、
チヤネル領域１９上にはゲート絶縁膜１５を介し
てゲート電極１６が形成され、ソース層１４上に
はベース層１３に同時にオーミツクコンタクトす
るソース電極１７が形成される。基板１１の裏面
にはドレイン電極１８が形成されている。[Technical background of the invention and its problems] In recent years, DSA has been used as a power switching element.
Power MOSFETs whose source and channel regions are formed using the Diffusion Self Align method have appeared on the market. However, this element has a high on-resistance at high withstand voltages of 1000V or higher, making it difficult to conduct large currents. As a promising alternative element, a so-called conductivity modulation type MOSFET is known, in which a conductivity type layer opposite to that of the source is provided in the drain region to cause conductivity modulation in the high resistance layer and lower the on-resistance. There is. Its basic structure is shown in Figure 1. 11 is a p + -Si substrate (drain layer), on which a high resistance layer with a low impurity concentration is
An n - layer (first base layer) 12 is formed, and this n - layer (first base layer) 12 is formed.
A p base layer (second layer) is formed on the surface of layer 12 by DSA method.
A base layer) 13 and an n + source layer 14 are formed. That is, by double-diffusing the p-base layer 13 by using the diffusion window in which the p-base layer 13 is diffused as a part of the diffusion window of the n + source layer 14, the p-base layer 1
An n + source layer 14 is formed with a channel region 19 remaining in self-alignment at the end of the n + source layer 14 . and,
A gate electrode 16 is formed on the channel region 19 with a gate insulating film 15 interposed therebetween, and a source electrode 17 is formed on the source layer 14 simultaneously in ohmic contact with the base layer 13. A drain electrode 18 is formed on the back surface of the substrate 11.
この導電変調型MOSFETでは、ソース層１４
からチヤネル領域１９を通つてn-層１２に注入
される電子電流に対して、p+基板１１から正孔
注入が起こり、この結果n-層１２には多量のキ
ヤリア蓄積による導電変調が起こる。n-層１２
に注入された正孔電流はｐベース層１３のソース
層１４直下を通り、ソース電極１７へ抜ける。 In this conductivity modulation type MOSFET, the source layer 14
Holes are injected from the p + substrate 11 in response to electron current injected into the n - layer 12 through the channel region 19, and as a result, conductivity modulation occurs in the n - layer 12 due to a large amount of carrier accumulation. n - layer 12
The hole current injected into the p base layer 13 passes directly under the source layer 14 and exits to the source electrode 17.
この構造はサイリスタと似ているがサイリスタ
動作はしない。ソース電極１７がｐベース層１３
とn+ソース層１４を短絡してサイリスタ動作を
阻止しており、ゲート・ソース間電圧を零とすれ
ば素子はターンオフする。またこの構造は従来の
パワーMOSFETとも似ているが、ドレイン領域
にパワーMOSFETとは逆の導電型層を設けて、
バイポーラ動作を行なわせている点で異なる。 This structure is similar to a thyristor, but it does not operate as a thyristor. The source electrode 17 is the p base layer 13
The thyristor operation is prevented by short-circuiting the n + source layer 14, and the device is turned off when the gate-source voltage is reduced to zero. This structure is also similar to a conventional power MOSFET, but a layer of the opposite conductivity type to that of the power MOSFET is provided in the drain region.
The difference is that bipolar operation is performed.
この導電変調型MOSFETは、高耐圧化した場
合にも、従来のパワーMOSFETに比べて導電変
調の結果として十分低いオン抵抗が得られる。 This conduction modulation type MOSFET can achieve sufficiently low on-resistance as a result of conduction modulation compared to conventional power MOSFETs even when the breakdown voltage is increased.
しかしながらこの導電変調型MOSFETにも未
だ問題がある。即ち素子を流れる電流密度が大き
くなると、ソース層１４下の横方向抵抗による電
圧降下が大きくなる。そしてｐベース層１３と
n+ソース層１４の間が順バイアスされるように
なるとサイリスタ動作に入り、ゲート・ソース間
バイアスを零にしても素子がオフしない、いわゆ
るラツチアツプ現象を生じる。 However, there are still problems with this conductivity modulation type MOSFET. That is, as the current density flowing through the device increases, the voltage drop due to the lateral resistance under the source layer 14 increases. And p base layer 13
When the n + source layer 14 becomes forward biased, it enters into a thyristor operation, and a so-called latch-up phenomenon occurs in which the device does not turn off even if the gate-source bias is reduced to zero.
この問題を解決するために従来は、第２図に示
すように、深いp+層２０を拡散形成して、ｐベ
ース層１３の抵抗を下げることが行われている。 In order to solve this problem, conventionally, as shown in FIG. 2, a deep p + layer 20 is formed by diffusion to lower the resistance of the p base layer 13.
しかしこの方法だけでは、十分高い電流密度ま
でラツチアツプ現象を防ぐことができない。 However, this method alone cannot prevent the latch-up phenomenon up to sufficiently high current densities.
本発明は上記の点に鑑みてなされたもので、パ
ターン設計により効果的に大電流領域までラツチ
アツプ現象を生じないようにした導電変調型
MOSFETを提供することを目的とする。
The present invention has been made in view of the above points, and is a conductive modulation type that effectively prevents the latch-up phenomenon even in the large current region by pattern design.
The purpose is to provide MOSFET.
本発明は、第１導通型ドレイン層に接して高抵
抗、第２導電型の第１ベース層が形成され、この
第１ベース層にDSA法により第１導電型の第２
ベース層とその表面に第２導電型ソース層が形成
される導電変調型MOSFETにおいて、ドレイン
側からベース層に注入されるキヤリアのうちソー
ス層下を通る成分を少なくして、ソース層下の横
方向抵抗による電圧降下を少なくし、もつて大電
流までラツチアツプを生じないようにする。この
ようにソース層下を通る電流成分を少なくするに
は、ソース電極と、第２ベース層が形成されてい
ない第１ベース層開孔部の間にMOSFET動作を
しない部分を周期的に形成すればよい。より具体
的には、例えば、ソース層を不連続的に形成する
のが一つの方法である。またチヤネル領域をしき
い値の低い部分と高い部分が周期的に形成される
ようにしてもよい。そのためには、第２ベース層
内に、高濃度第１導電型層を、チヤネル領域に終
端する部分とソース層下に終端する部分が現れる
ように凹凸パターンのエツジをもつて形成すれば
よい。
In the present invention, a first base layer of a high resistance and second conductivity type is formed in contact with a first conduction type drain layer, and a second base layer of a first conductivity type is formed on this first base layer by a DSA method.
In a conductivity modulation type MOSFET in which a base layer and a second conductivity type source layer are formed on the surface thereof, the component of carriers injected into the base layer from the drain side that passes under the source layer is reduced, and the lateral side under the source layer is To reduce voltage drop due to directional resistance and prevent latch-up even at large currents. In order to reduce the current component passing under the source layer, it is necessary to periodically form a portion that does not operate as a MOSFET between the source electrode and the first base layer opening where the second base layer is not formed. Bye. More specifically, one method is to form the source layer discontinuously, for example. Alternatively, the channel region may be formed such that portions with low thresholds and portions with high thresholds are periodically formed. For this purpose, a highly concentrated first conductivity type layer may be formed in the second base layer with an edge pattern of concave and convex portions so that a portion terminating in the channel region and a portion terminating under the source layer appear.
本発明によれば、パターン設計によつて簡単且
つ効果的に導電変調型MOSFETのラツチアツプ
現象を抑制することができ、大電流まで動作する
導電変調型MOSFETが得られる。
According to the present invention, the latch-up phenomenon of a conduction modulation type MOSFET can be suppressed simply and effectively by pattern design, and a conduction modulation type MOSFET that operates up to a large current can be obtained.
本発明の実施例を以下に説明する。第３図は一
実施例の導電変調型MOSFETを示すもので、ａ
は模式的平面図、ｂはａのＡ−A′断面図である。
この実施例は第２ベース層であるｐベース層がス
トライプ状に基板上に形成された例である。第１
図、第２図と対応する部分にはそれらと同じ符号
を付してある。これを製造工程に従つて説明す
る。p+Si基板（ドレイン層）１１を用意し、これ
にエピタキシヤル成長により低不純物濃度で比抵
抗50Ωcm以上のn-層（第１ベース層）１２を
100μｍ程度形成する。次にこのn-層１２の表面
を酸化してゲート酸化膜１５を形成し、その上に
5000ÅのポリSi膜によるゲート電極１６を形成す
る。この後ゲート電極１６をマスクとしてボロン
を8μｍ程度拡散してｐベース層（第２ベース層）
１３を形成する。次いでゲート電極１６による窓
の中にソース層形成用の開孔を持つ酸化膜（図示
せず）を形成し、この酸化膜とゲート電極１６を
マスクとしてソース層形成のためのドーズ量５×
1015／cm2のASイオン注入を行ない、熱処理して
n+ソース層１４を形成する。第３図ａから明ら
かなようにソース層１４は、チヤネル領域１９及
びゲート１６に沿つて不連続的に複数個配列形成
される。この後、ｐベース層１３内に高濃度の
p+層２０を拡散形成し、このp+層２０とn+ソー
ス層１４にコンタクトするソース電極１７を形成
する。基板裏面にはＶ−Ni−Au膜の蒸着により
ドレイン電極１８を形成する。チヤネル領域１９
は、通常のMOSFET動作をする実効的チヤネル
部分１９ａと、ソースがないためにMOSFET動
作をしない部分１９ｂとが交互に配列された状態
となる。
Examples of the present invention will be described below. Figure 3 shows an example of a conductivity modulation type MOSFET.
is a schematic plan view, and b is a sectional view taken along line A-A' of a.
This embodiment is an example in which a p base layer, which is a second base layer, is formed in stripes on a substrate. 1st
The same reference numerals are given to the parts corresponding to those in FIG. 2 and FIG. This will be explained according to the manufacturing process. A p + Si substrate (drain layer) 11 is prepared, and an n - layer (first base layer) 12 with a low impurity concentration and a resistivity of 50 Ωcm or more is formed on this by epitaxial growth.
Form about 100μm. Next, the surface of this n - layer 12 is oxidized to form a gate oxide film 15, and on top of that a gate oxide film 15 is formed.
A gate electrode 16 is formed of a poly-Si film of 5000 Å. After this, using the gate electrode 16 as a mask, boron is diffused to a thickness of about 8 μm to form a p base layer (second base layer).
form 13. Next, an oxide film (not shown) having an opening for forming a source layer is formed in the window formed by the gate electrode 16, and using this oxide film and the gate electrode 16 as a mask, the dose for forming the source layer is 5×.
After AS ion implantation at 10 15 /cm 2 and heat treatment,
An n + source layer 14 is formed. As is clear from FIG. 3a, a plurality of source layers 14 are discontinuously arranged along the channel region 19 and the gate 16. After this, a high concentration is added to the p base layer 13.
A p + layer 20 is formed by diffusion, and a source electrode 17 is formed in contact with the p + layer 20 and the n + source layer 14 . A drain electrode 18 is formed on the back surface of the substrate by vapor deposition of a V-Ni-Au film. Channel area 19
In this case, effective channel portions 19a that perform normal MOSFET operation and portions 19b that do not perform MOSFET operation because there is no source are arranged alternately.
この実施例のMOSFETでは、素子がオンの時
に、ゲート電極１６下に開孔するn-層１２から
ｐベース層１３にドレインから注入される正孔電
流の内、チヤネル部分１９ｂを通るものはソース
層１４の下を通らず直接ソース電極１７に流れ
る。従つて従来の構造に比べてソース層下の横方
向抵抗が実効的に小さくなり、大電流までラツナ
アツプ現象を生じない。 In the MOSFET of this embodiment, when the device is on, of the hole current injected from the drain from the n - layer 12 opened below the gate electrode 16 to the p base layer 13, the one that passes through the channel portion 19b is the source. It flows directly to the source electrode 17 without passing under the layer 14. Therefore, compared to the conventional structure, the lateral resistance under the source layer is effectively reduced, and the latch-up phenomenon does not occur even at large currents.
第４図ａ，ｂは本発明の別の実施例の導電変調
型MOSFETを示す模式的平面図とそのＢ−B′断
面図である。先の実施例と対応する部分には同じ
符号を付して詳細な説明は省略する。この実施例
においては、ｐベース層１３内に拡散形成する
p+層２０を、そのエツジが凹凸パターンとなる
ように、即ち、チヤネル領域に終端するエツジと
ソース層１４下に終端するエツジが交互に現れる
パターンとする。つまり、チヤネル領域１９は
p+層２０が形成された部分１９ｂとp+層のない
部分１９ａが交互に形成される。なお、n+ソー
ス層１４は従来と同様にｐベース層１３内の両側
に連続的に形成している。 FIGS. 4a and 4b are a schematic plan view and a sectional view taken along the line B-B' of a conductivity modulation type MOSFET according to another embodiment of the present invention. Portions corresponding to those in the previous embodiment are given the same reference numerals and detailed explanations will be omitted. In this embodiment, the p base layer 13 is formed by diffusion.
The p + layer 20 is formed so that its edges have a concavo-convex pattern, that is, a pattern in which edges terminating in the channel region and edges terminating below the source layer 14 appear alternately. In other words, the channel area 19 is
Portions 19b where the p + layer 20 is formed and portions 19a where no p + layer is formed are alternately formed. Note that the n + source layer 14 is continuously formed on both sides of the p base layer 13 as in the conventional case.
この実施例では、チヤネル部分１９ｂは、その
しきい値がチヤネル部分１９ａでのそれに比べて
高く実効的にはチヤネルとして寄与しない。即
ち、素子のしきい値はチヤネル部分１９ａで決ま
る。従つてゲート電極１６にオンゲート信号を与
えた時、チヤネル部分１９ａがMOSFET動作に
よりオンし、チヤネル部分１９ｂではオンしな
い。n-層１２で導電変調が起こつて大電流が流
れるオン状態では、n-層１２からの電流がチヤ
ネル部分１９ｂをも流れるが、チヤネル部分１９
ａに比べると、p+層がソース層１４の下全体に
渡つて形成されているため、ソース層１４下の横
方向抵抗が小さく、従つてこのチヤネル部分１９
ｂを通る電流による電圧降下は小さい。この結果
この実施例によつても、ラツチアツプを生じるこ
となく大電流を渡すことができる。 In this embodiment, channel portion 19b has a higher threshold value than channel portion 19a and does not effectively contribute as a channel. That is, the threshold value of the element is determined by the channel portion 19a. Therefore, when an on-gate signal is applied to the gate electrode 16, the channel portion 19a is turned on due to MOSFET operation, but the channel portion 19b is not turned on. In the on state where conductivity modulation occurs in the n - layer 12 and a large current flows, the current from the n - layer 12 also flows through the channel portion 19b;
Compared to a, since the p + layer is formed entirely under the source layer 14, the lateral resistance under the source layer 14 is small, and therefore this channel portion 19
The voltage drop due to the current through b is small. As a result, even in this embodiment, a large current can be passed without causing latch-up.
第４図の実施例では、n+ソース層１４をｐベ
ース層１３の両側に連続的に形成しているが、こ
のソース層１４を第３図の実施例と同様に実効的
にチヤネルとなる部分１９ａにのみ残して不連続
的に形成すれば、即ち第３図の実施例と第４図の
実施例を組合わせた構造とすれば、一層効果的で
ある。その実施例の模式的平面図を第５図に示
す。これにより、1500A／cm2程度までラツチアツ
プを生じない導電変調型MOSFETが得られる。 In the embodiment shown in FIG. 4, the n + source layer 14 is formed continuously on both sides of the p base layer 13, and this source layer 14 effectively becomes a channel as in the embodiment shown in FIG. It is even more effective if it is formed discontinuously by leaving it only in the portion 19a, that is, if the structure is a combination of the embodiment of FIG. 3 and the embodiment of FIG. 4. A schematic plan view of this embodiment is shown in FIG. As a result, a conduction modulation type MOSFET that does not cause latch-up up to about 1500 A/cm 2 can be obtained.
また第３図或いは第５図の実施例では、ｐベー
ス層１３内の両側にそれぞれ複数のn+ソース層
１４を設けたが、n+ソース層をｐベース層の一
方の端部には連続的に設け、他方の端部には全く
設けないようにしてもよい。第６図はその実施例
で、ａが模式的平面図、ｂはそのＣ−C′断面図で
ある。この実施例の場合、チヤネル領域１９のう
ち、ソース層１４のある側のチヤネル部分１９ａ
のみ実効的なMOSFET動作のチヤネルとして寄
与し、もう一方のチヤネル部分１９ｂは
MOSFET動作のチヤネルとしては働かない。そ
して先の各実施例と同じように、n-層１２から
ｐベース層１３に注入される電流のうちチヤネル
部分１９ｂを通る成分はソース層１４の下を通ら
ず直接ソース電極に流れるため、やはりラツプア
ツプ現象が効果的に抑制される。 Further, in the embodiment shown in FIG. 3 or FIG. 5, a plurality of n + source layers 14 are provided on both sides of the p base layer 13, but an n + source layer is provided continuously at one end of the p base layer. It may be provided at one end and not provided at all at the other end. FIG. 6 shows the embodiment, in which a is a schematic plan view and b is a sectional view taken along the line C-C'. In this embodiment, a channel portion 19a of the channel region 19 on the side where the source layer 14 is located
contributes as a channel for effective MOSFET operation, and the other channel portion 19b contributes as a channel for effective MOSFET operation.
It does not work as a channel for MOSFET operation. As in the previous embodiments, the component of the current injected from the n - layer 12 to the p base layer 13 that passes through the channel portion 19b does not pass under the source layer 14 but flows directly to the source electrode. The wrap-up phenomenon is effectively suppressed.
以上の実施例は、第１導電型としてｐ型、第２
導電型としてｎ型を用いたが、各部の導電型を逆
にしても本発明は有効である。更に以上の実施例
において、n-型層１２を出発基板としてp+型ド
レインを拡散により形成するようにしてもよい。 In the above embodiments, the first conductivity type is p-type, the second conductivity type is p-type, and the second conductivity type is p-type.
Although n-type is used as the conductivity type, the present invention is effective even if the conductivity types of each part are reversed. Furthermore, in the above embodiments, the p + -type drain may be formed by diffusion using the n - -type layer 12 as a starting substrate.
第１図は一般的な導電変調型MOSFETを示す
断面図、第２図はこれを改良した導電変調型
MOSFETを示す断面図、第３図ａ，ｂは本発明
の一実施例の導電変調型MOSFETを示す平面図
とそのＡ−A′断面図、第４図ａ，ｂは本発明の
別の実施例の導電変調型MOSFETを示す平面図
とそのＢ−B′断面図、第５図は上記実施例を組
合わせた実施例の導電変調型MOSFETを示す平
面図、第６図ａ，ｂは更に別の実施例の導電変調
型MOSFETを示す平面図とそのＣ−C′断面図で
ある。
１１……p+Si基板、１２……n-層、１３……
ｐベース層、１４……n+ソース層、１５……ゲ
ート酸化膜、１６……ゲート電極、１７……ソー
ス電極、１８……ドレイン電極、１９……チヤネ
ル領域、１９ａ……実効的チヤネル部分、１９ｂ
……MOSFET動作に寄与しないチヤネル部分、
２０……p+層。
Figure 1 is a cross-sectional view of a typical conduction modulation type MOSFET, and Figure 2 is an improved conduction modulation type MOSFET.
A sectional view showing a MOSFET, FIGS. 3a and 3b are a plan view and an A-A' sectional view of a conductivity modulation type MOSFET according to an embodiment of the present invention, and FIGS. 4a and 4b are another embodiment of the present invention. FIG. 5 is a plan view showing a conductivity modulation type MOSFET as an example and its BB' sectional view, FIG. FIG. 7 is a plan view and a cross-sectional view taken along the line C-C' of a conductivity modulation MOSFET according to another embodiment. 11... p + Si substrate, 12... n - layer, 13...
p base layer, 14...n + source layer, 15... gate oxide film, 16... gate electrode, 17... source electrode, 18... drain electrode, 19... channel region, 19a... effective channel part , 19b
...Channel part that does not contribute to MOSFET operation,
20...p + layer.
Claims (1)
に接する低不純物濃度で第２導電型の第１ベース
層と、この第１ベース層の表面に選択的に形成さ
れた第１導通型の第２ベース層と、この第２ベー
ス層の表面に選択的に拡散形成された第２導電型
のソース層と、このソース層と前記第１ベース層
に挟まれた領域の第２ベース層表面をチヤネル領
域としてこの上にゲート絶縁膜を介して形成され
たゲート電極と、前記ドレイン層にコンタクトす
るドレイン電極と、前記ソース層と前記第２ベー
ス層に同時にコンタクトするソース電極とを備え
た導電変調型MOSFETにおいて、前記ソース電
極と、前記第２ベース層が形成されていない第１
ベース層の表面領域との間にMOSFET動作をし
ない部分が周期的に形成されていることを特徴と
する導電変調型MOSFET。 ２ 前記MOSFET動作をしない部分は、チヤネ
ル領域に沿つてソース層を不連続的に形成するこ
とにより、ドレイン側からのキヤリアがソース層
の下を通らずソース電極に流れる通路を形成した
ものである特許請求の範囲第１項記載の導電変調
型MOSFET。 ３ 前記MOSFET動作をしない部分は、第２ベ
ース層内に高濃度の第１導電型層を、チヤネル領
域に終端する部分とソース層下に終端する部分が
周期的に現れるような凹凸パターンのエツジをも
つて形成することにより、しきい値を他の部分よ
り高くしたものである特許請求の範囲第１項記載
の導電変調型MOSFET。 ４ 前記MOSFET動作をしない部分は、ゲート
電極に沿つてソース層を第２ベース層内に不連続
的に形成することにより、ドレイン側からのキヤ
リアがソース層の下を通らずソース電極に流れる
通路を形成したものである特許請求の範囲第１項
記載の導電変調型MOSFET。[Claims] 1. A drain layer of a first conductivity type, a first base layer of a second conductivity type with a low impurity concentration in contact with the drain layer, and a first base layer of a second conductivity type selectively formed on the surface of the first base layer. a second base layer of a first conductivity type; a source layer of a second conductivity type selectively diffused on the surface of the second base layer; and a region sandwiched between the source layer and the first base layer. A gate electrode formed on the surface of the second base layer as a channel region through a gate insulating film, a drain electrode in contact with the drain layer, and a source electrode in contact with the source layer and the second base layer at the same time. A conductivity modulation type MOSFET comprising: the source electrode and a first base layer on which the second base layer is not formed;
A conductivity modulation type MOSFET characterized by periodically forming portions that do not operate as a MOSFET between the surface region of the base layer. 2 In the part where the MOSFET does not operate, the source layer is discontinuously formed along the channel region, thereby forming a path through which carriers from the drain side flow to the source electrode without passing under the source layer. A conduction modulation type MOSFET according to claim 1. 3 The portion that does not operate as a MOSFET is formed by forming a highly concentrated layer of the first conductivity type in the second base layer at the edge of a concavo-convex pattern in which a portion terminating in the channel region and a portion terminating below the source layer appear periodically. 2. The conductivity modulation type MOSFET according to claim 1, wherein the conduction modulation type MOSFET has a threshold value higher than that of other parts by forming the conduction modulation type MOSFET. 4 The portion where the MOSFET does not operate is a path where carriers from the drain side do not pass under the source layer but flow to the source electrode by discontinuously forming the source layer in the second base layer along the gate electrode. A conductivity modulation type MOSFET according to claim 1, which is formed of a conductive modulation type MOSFET.
Priority Applications (13)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11024484A JPS60254658A (en) | 1984-05-30 | 1984-05-30 | Conductive modulation type mosfet |
| US06/738,188 US4672407A (en) | 1984-05-30 | 1985-05-28 | Conductivity modulated MOSFET |
| DE3546745A DE3546745C2 (en) | 1984-05-30 | 1985-05-30 | Variable conductivity power MOSFET |
| GB08513599A GB2161649B (en) | 1984-05-30 | 1985-05-30 | Conductivity modulated mosfet |
| DE19853519389 DE3519389A1 (en) | 1984-05-30 | 1985-05-30 | VARIABLE CONDUCTIVITY MOSFET |
| US07/019,337 US4782372A (en) | 1984-05-30 | 1987-02-26 | Lateral conductivity modulated MOSFET |
| US07/116,357 US4881120A (en) | 1984-05-30 | 1987-11-04 | Conductive modulated MOSFET |
| US07/146,405 US5093701A (en) | 1984-05-30 | 1988-01-21 | Conductivity modulated mosfet |
| US07/205,365 US4928155A (en) | 1984-05-30 | 1988-06-10 | Lateral conductivity modulated MOSFET |
| US07/712,997 US5086323A (en) | 1984-05-30 | 1991-06-10 | Conductivity modulated mosfet |
| US07/799,311 US5286984A (en) | 1984-05-30 | 1991-11-27 | Conductivity modulated MOSFET |
| US08/261,254 US5780887A (en) | 1984-05-30 | 1994-06-14 | Conductivity modulated MOSFET |
| US09/104,326 US6025622A (en) | 1984-05-30 | 1998-06-25 | Conductivity modulated MOSFET |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11024484A JPS60254658A (en) | 1984-05-30 | 1984-05-30 | Conductive modulation type mosfet |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60254658A JPS60254658A (en) | 1985-12-16 |
| JPH0512868B2 true JPH0512868B2 (en) | 1993-02-19 |
Family
ID=14530759
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11024484A Granted JPS60254658A (en) | 1984-05-30 | 1984-05-30 | Conductive modulation type mosfet |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60254658A (en) |
Families Citing this family (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5212396A (en) * | 1983-11-30 | 1993-05-18 | Kabushiki Kaisha Toshiba | Conductivity modulated field effect transistor with optimized anode emitter and anode base impurity concentrations |
| US4641162A (en) * | 1985-12-11 | 1987-02-03 | General Electric Company | Current limited insulated gate device |
| US4779123A (en) * | 1985-12-13 | 1988-10-18 | Siliconix Incorporated | Insulated gate transistor array |
| JPS62282465A (en) * | 1986-03-05 | 1987-12-08 | イクシス・コーポレーション | Monolithic semiconductor device and manufacture of the same |
| US5237186A (en) * | 1987-02-26 | 1993-08-17 | Kabushiki Kaisha Toshiba | Conductivity-modulation metal oxide field effect transistor with single gate structure |
| US5105243A (en) * | 1987-02-26 | 1992-04-14 | Kabushiki Kaisha Toshiba | Conductivity-modulation metal oxide field effect transistor with single gate structure |
| JPH0821713B2 (en) * | 1987-02-26 | 1996-03-04 | 株式会社東芝 | Conduction modulation type MOSFET |
| JPH0834312B2 (en) * | 1988-12-06 | 1996-03-29 | 富士電機株式会社 | Vertical field effect transistor |
| JPH02312280A (en) * | 1989-05-26 | 1990-12-27 | Mitsubishi Electric Corp | Insulated gate bipolar transistor |
| JPH05160407A (en) * | 1991-12-09 | 1993-06-25 | Nippondenso Co Ltd | Vertical insulating gate type semiconductor device and manufacture thereof |
| US6204533B1 (en) * | 1995-06-02 | 2001-03-20 | Siliconix Incorporated | Vertical trench-gated power MOSFET having stripe geometry and high cell density |
| US6492663B1 (en) | 1999-05-20 | 2002-12-10 | Richard A. Blanchard | Universal source geometry for MOS-gated power devices |
| JP4839578B2 (en) * | 2004-04-26 | 2011-12-21 | 富士電機株式会社 | Horizontal semiconductor device |
| JP4830263B2 (en) * | 2004-04-26 | 2011-12-07 | 富士電機株式会社 | High voltage insulated gate bipolar transistor |
| JP2007049061A (en) * | 2005-08-12 | 2007-02-22 | Toshiba Corp | Semiconductor device |
| JP6206599B2 (en) * | 2014-09-11 | 2017-10-04 | 富士電機株式会社 | Semiconductor device and manufacturing method of semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57211773A (en) * | 1981-06-16 | 1982-12-25 | Thomson Csf | Semiconductor structure |
-
1984
- 1984-05-30 JP JP11024484A patent/JPS60254658A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57211773A (en) * | 1981-06-16 | 1982-12-25 | Thomson Csf | Semiconductor structure |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60254658A (en) | 1985-12-16 |
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